reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/Analysis/TargetTransformInfoImpl.h
   68     case Instruction::SRem:
include/llvm/IR/IRBuilder.h
 1218     if (Value *V = foldConstant(Instruction::SRem, LHS, RHS, Name)) return V;
include/llvm/IR/Instruction.h
  156     return Opcode == UDiv || Opcode == SDiv || Opcode == URem || Opcode == SRem;
include/llvm/IR/PatternMatch.h
  862 inline BinaryOp_match<LHS, RHS, Instruction::SRem> m_SRem(const LHS &L,
  864   return BinaryOp_match<LHS, RHS, Instruction::SRem>(L, R);
 1051     return Opcode == Instruction::SRem || Opcode == Instruction::URem;
lib/Analysis/CFLGraph.h
  571       case Instruction::SRem:
lib/Analysis/InstructionSimplify.cpp
 1075   if ((Opcode == Instruction::SRem &&
 1083       ((Opcode == Instruction::SRem &&
 1102   if (isDivZero(Op0, Op1, Q, MaxRecurse, Opcode == Instruction::SRem))
 1148   return simplifyRem(Instruction::SRem, Op0, Op1, Q, MaxRecurse);
 4782   case Instruction::SRem:
 5287   case Instruction::SRem:
lib/Analysis/ObjCARCInstKind.cpp
  261     case Instruction::SRem:
lib/Analysis/TargetTransformInfo.cpp
 1164   case Instruction::SRem:
lib/Analysis/ValueTracking.cpp
 1233   case Instruction::SRem:
 2420     case Instruction::SRem: {
 3918   case Instruction::SRem: {
 4370     case Instruction::SRem:
 5554   case Instruction::SRem:
lib/AsmParser/LLLexer.cpp
  845   INSTKEYWORD(urem,  URem); INSTKEYWORD(srem,  SRem); INSTKEYWORD(frem,  FRem);
lib/AsmParser/LLParser.cpp
 3491     case Instruction::SRem:
lib/Bitcode/Reader/BitcodeReader.cpp
 1093     return IsFP ? Instruction::FRem : Instruction::SRem;
lib/Bitcode/Writer/BitcodeWriter.cpp
  541   case Instruction::SRem: return bitc::BINOP_SREM;
lib/CodeGen/AsmPrinter/AsmPrinter.cpp
 2294   case Instruction::SRem:
 2307     case Instruction::SRem: return MCBinaryExpr::createMod(LHS, RHS, Ctx);
lib/CodeGen/CodeGenPrepare.cpp
 6452     case Instruction::SRem:
lib/CodeGen/SelectionDAG/FastISel.cpp
 1816   case Instruction::SRem:
lib/CodeGen/TargetLoweringBase.cpp
 1602   case SRem:           return ISD::SREM;
lib/ExecutionEngine/ExecutionEngine.cpp
  787     case Instruction::SRem:
  805           case Instruction::SRem:GV.IntVal = LHS.IntVal.srem(RHS.IntVal); break;
lib/ExecutionEngine/Interpreter/Execution.cpp
  792     case Instruction::SRem:  INTEGER_VECTOR_FUNCTION(srem) break;
  834     case Instruction::SRem:  R.IntVal = Src1.IntVal.srem(Src2.IntVal); break;
 2084   case Instruction::SRem: Dest.IntVal = Op0.IntVal.srem(Op1.IntVal); break;
lib/FuzzMutate/Operations.cpp
   24   Ops.push_back(binOpDescriptor(1, Instruction::SRem));
  102   case Instruction::SRem:
lib/IR/ConstantFold.cpp
 1034     case Instruction::SRem:
 1121     case Instruction::SRem:
 1243       case Instruction::SRem:
 1273     case Instruction::SRem:
 1365     case Instruction::SRem:
lib/IR/ConstantRange.cpp
  793   case Instruction::SRem:
lib/IR/Constants.cpp
  449   case Instruction::SRem:
 1884   case Instruction::SRem:
 2302   return get(Instruction::SRem, C1, C2);
lib/IR/Instruction.cpp
  322   case SRem: return "srem";
lib/IR/Instructions.cpp
 2306   case SRem:
lib/IR/Verifier.cpp
 3170   case Instruction::SRem:
lib/Target/AArch64/AArch64FastISel.cpp
 5160   case Instruction::SRem:
lib/Target/AArch64/AArch64TargetTransformInfo.cpp
  111   case Instruction::SRem:
lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
  220       I.getOpcode() == Instruction::SDiv || I.getOpcode() == Instruction::SRem;
  289       I.getOpcode() == Instruction::SRem ||
  744          Opc == Instruction::SRem || Opc == Instruction::SDiv);
  754   bool IsSigned = Opc == Instruction::SRem || Opc == Instruction::SDiv;
  898        Opc == Instruction::SRem || Opc == Instruction::SDiv) &&
lib/Target/ARM/ARMCodeGenPrepare.cpp
  187          Opc == Instruction::SRem || Opc == Instruction::SExt;
lib/Target/ARM/ARMFastISel.cpp
 2860     case Instruction::SRem:
lib/Target/ARM/ARMTargetTransformInfo.cpp
  114        Opcode == Instruction::SRem || Opcode == Instruction::URem) &&
lib/Target/Mips/MipsFastISel.cpp
 2053   case Instruction::SRem:
lib/Target/PowerPC/PPCTargetTransformInfo.cpp
  449                 J->getOpcode() == Instruction::SRem)) {
lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
  165   case Instruction::SRem:
  374       Opcode == Instruction::SDiv || Opcode == Instruction::SRem;
lib/Target/X86/X86FastISel.cpp
 1928   case Instruction::SRem: OpIndex = 1; break;
 1985   if ((I->getOpcode() == Instruction::SRem ||
 3626   case Instruction::SRem:
lib/Target/X86/X86InstructionSelector.cpp
 1687   if ((I.getOpcode() == Instruction::SRem ||
lib/Target/X86/X86TargetTransformInfo.cpp
 3015   case Instruction::SRem:
lib/Target/XCore/XCoreLowerThreadLocal.cpp
   95     case Instruction::SRem:
lib/Transforms/InstCombine/InstCombineCompares.cpp
 2851     case Instruction::SRem:
 2918   case Instruction::SRem:
 3899   if (BO0 && BO0->getOpcode() == Instruction::SRem && Op1 == BO0->getOperand(1))
 3902   else if (BO1 && BO1->getOpcode() == Instruction::SRem &&
lib/Transforms/InstCombine/InstCombineInternal.h
  256       case Instruction::SRem: // X % 1 = 0
  273       case Instruction::SRem: // 0 % X = 0
lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
  323                                                           : Instruction::SRem;
lib/Transforms/InstCombine/InstCombineSelect.cpp
 2575     case Instruction::SRem:
lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
  600   case Instruction::SRem:
lib/Transforms/InstCombine/InstCombineVectorOps.cpp
 1146     case Instruction::SRem:
 1227     case Instruction::SRem:
 1325     case Instruction::SRem:
lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
  860       case Instruction::SRem:
lib/Transforms/Scalar/DivRemPairs.cpp
  105     case Instruction::SRem:
  133       else if (I.getOpcode() == Instruction::SRem)
lib/Transforms/Scalar/GVN.cpp
  507     case Instruction::SRem:
lib/Transforms/Scalar/GVNSink.cpp
  455     case Instruction::SRem:
lib/Transforms/Scalar/NewGVN.cpp
 2010     case Instruction::SRem:
lib/Transforms/Scalar/SCCP.cpp
 1572       case Instruction::SRem:
lib/Transforms/Utils/BypassSlowDivision.cpp
   94            SlowDivOrRem->getOpcode() == Instruction::SRem;
  118   case Instruction::SRem:
lib/Transforms/Utils/IntegerDivision.cpp
  376   assert((Rem->getOpcode() == Instruction::SRem ||
  388   if (Rem->getOpcode() == Instruction::SRem) {
  486   assert((Rem->getOpcode() == Instruction::SRem ||
  511   if (Rem->getOpcode() == Instruction::SRem) {
  535   assert((Rem->getOpcode() == Instruction::SRem ||
  559   if (Rem->getOpcode() == Instruction::SRem) {
lib/Transforms/Utils/Local.cpp
 1701     case Instruction::SRem:
lib/Transforms/Utils/SimplifyIndVar.cpp
  623     bool IsSRem = Bin->getOpcode() == Instruction::SRem;
lib/Transforms/Vectorize/LoopVectorize.cpp
 4055           I.getOpcode() == Instruction::SRem) &&
 4138   case Instruction::SRem:
 4572   case Instruction::SRem:
 6159   case Instruction::SRem:
 6874     case Instruction::SRem:
lib/Transforms/Vectorize/SLPVectorizer.cpp
 2577     case Instruction::SRem:
 3091     case Instruction::SRem:
 3975     case Instruction::SRem:
tools/lldb/source/Expression/IRInterpreter.cpp
  586       case Instruction::SRem:
  702     case Instruction::SRem:
  766       case Instruction::SRem:
tools/llvm-stress/llvm-stress.cpp
  400     case 5:{Op = (isFloat?Instruction::FRem : Instruction::SRem); break; }
tools/polly/lib/Support/SCEVAffinator.cpp
  514   assert(SRem->getOpcode() == Instruction::SRem && "Assumed SRem instruction!");
  539     case Instruction::SRem:
tools/polly/lib/Support/SCEVValidator.cpp
  417     assert(SRem->getOpcode() == Instruction::SRem &&
  453       case Instruction::SRem:
  593     if (!Inst || (Inst->getOpcode() != Instruction::SRem &&
tools/polly/lib/Support/ScopHelper.cpp
  311     if (!Inst || (Inst->getOpcode() != Instruction::SRem &&
unittests/Transforms/Utils/IntegerDivisionTest.cpp
  101   EXPECT_TRUE(BB->front().getOpcode() == Instruction::SRem);
  222   EXPECT_TRUE(BB->front().getOpcode() == Instruction::SRem);