|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/CodeGen/MachineRegisterInfo.h 219 return shouldTrackSubRegLiveness(*getRegClass(VReg));
1180 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
lib/CodeGen/AllocationOrder.cpp 36 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
lib/CodeGen/CalcSpillWeights.cpp 72 const TargetRegisterClass *rc = mri.getRegClass(reg);
lib/CodeGen/DetectDeadLanes.cpp 158 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
254 const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
373 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
438 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
487 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
lib/CodeGen/EarlyIfConversion.cpp 597 DstReg = MRI->createVirtualRegister(MRI->getRegClass(PHIDst));
lib/CodeGen/GlobalISel/InstructionSelect.cpp 174 auto SrcRC = MRI.getRegClass(SrcReg);
175 auto DstRC = MRI.getRegClass(DstReg);
lib/CodeGen/InlineSpiller.cpp 413 MRI.getRegClass(SrcReg), &TRI);
910 MRI.getRegClass(NewVReg), &TRI);
950 MRI.getRegClass(NewVReg), &TRI);
1067 StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original));
1120 << TRI.getRegClassName(MRI.getRegClass(edit.getReg()))
1512 MRI.getRegClass(LiveReg), &TRI);
lib/CodeGen/LiveDebugVariables.cpp 1184 const TargetRegisterClass *TRC = MRI.getRegClass(VirtReg);
lib/CodeGen/LiveIntervals.cpp 1660 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
lib/CodeGen/LiveRangeEdit.cpp 35 Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
55 Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
472 << TRI->getRegClassName(MRI.getRegClass(LI.reg)) << '\n';
lib/CodeGen/LiveRangeShrink.cpp 192 MRI.getRegClass(DefMO->getReg()) ==
193 MRI.getRegClass(MO.getReg())) {
lib/CodeGen/MIRCanonicalizerPass.cpp 337 if (MRI.getRegClass(Dst) != MRI.getRegClass(Src))
337 if (MRI.getRegClass(Dst) != MRI.getRegClass(Src))
lib/CodeGen/MachineFunction.cpp 588 const TargetRegisterClass *VRegRC = MRI.getRegClass(VReg);
lib/CodeGen/MachineLICM.cpp 860 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
1394 OrigRCs.push_back(MRI->getRegClass(DupReg));
1396 if (!MRI->constrainRegClass(DupReg, MRI->getRegClass(Reg))) {
lib/CodeGen/MachineLoopUtils.cpp 55 R = MRI.createVirtualRegister(MRI.getRegClass(OrigR));
67 MRI.constrainRegClass(R, MRI.getRegClass(Use->getReg()));
lib/CodeGen/MachinePipeliner.cpp 355 auto *RC = MRI.getRegClass(DefOp.getReg());
lib/CodeGen/MachineRegisterInfo.cpp 88 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs);
124 const TargetRegisterClass *OldRC = getRegClass(Reg);
502 const TargetRegisterClass &TRC = *getRegClass(Reg);
lib/CodeGen/MachineSSAUpdater.cpp 61 VRC = MRI->getRegClass(VR);
lib/CodeGen/MachineSink.cpp 212 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
213 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg);
660 if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg)))
lib/CodeGen/ModuloSchedule.cpp 547 const TargetRegisterClass *RC = MRI.getRegClass(Def);
663 const TargetRegisterClass *RC = MRI.getRegClass(Def);
811 SplitReg = MRI.createVirtualRegister(MRI.getRegClass(Def));
1032 const TargetRegisterClass *RC = MRI.getRegClass(reg);
1183 MRI.constrainRegClass(ReplaceReg, MRI.getRegClass(OldReg));
1231 MRI.getRegClass(MI.getOperand(0).getReg()));
1427 LoopReg = phi(LoopReg, *DefaultI++, MRI.getRegClass(Reg));
1435 auto RC = MRI.getRegClass(Reg);
1475 MRI.constrainRegClass(R, MRI.getRegClass(InitReg.getValue()));
1482 RC = MRI.getRegClass(LoopReg);
1485 MRI.constrainRegClass(R, MRI.getRegClass(*InitReg));
1679 auto RC = MRI.getRegClass(MI.getOperand(0).getReg());
1728 MRI.setRegClass(R, MRI.getRegClass(PhiR));
lib/CodeGen/OptimizePHIs.cpp 180 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
lib/CodeGen/PHIElimination.cpp 281 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
lib/CodeGen/PeepholeOptimizer.cpp 473 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
484 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr;
570 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
668 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
730 const TargetRegisterClass *SrcRC = MRI->getRegClass(CurSrcPair.Reg);
760 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg);
1231 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg);
1424 if (MRI->getRegClass(DstReg) != MRI->getRegClass(PrevDstReg))
1424 if (MRI->getRegClass(DstReg) != MRI->getRegClass(PrevDstReg))
1959 if (MRI.getRegClass(MODef.getReg()) != MRI.getRegClass(BaseReg.Reg) ||
1959 if (MRI.getRegClass(MODef.getReg()) != MRI.getRegClass(BaseReg.Reg) ||
lib/CodeGen/RegAllocBase.cpp 107 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg))
137 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
lib/CodeGen/RegAllocFast.cpp 255 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
321 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
347 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
667 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
761 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
lib/CodeGen/RegAllocGreedy.cpp 711 const TargetRegisterClass &RC = *MRI->getRegClass(Reg);
922 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) <
923 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg)));
1127 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg);
1690 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
2023 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
2088 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg);
2532 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg);
2551 MRI->getRegClass(Intf->reg) == CurRC) &&
2946 if (CurrPhys != PhysReg && (!MRI->getRegClass(Reg)->contains(PhysReg) ||
lib/CodeGen/RegAllocPBQP.cpp 604 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
756 const TargetRegisterClass &RC = *MRI.getRegClass(LI.reg);
882 const char *RegClassName = TRI->getRegClassName(MRI.getRegClass(VReg));
lib/CodeGen/RegisterCoalescer.cpp 429 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
431 } else if (!MRI.getRegClass(Src)->contains(Dst)) {
436 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
437 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
840 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
1296 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
1762 auto SrcRC = MRI->getRegClass(CP.getSrcReg());
1763 auto DstRC = MRI->getRegClass(CP.getDstReg());
3721 << TRI->getRegClassName(MRI->getRegClass(Reg)) << '\n');
lib/CodeGen/RegisterScavenging.cpp 666 const TargetRegisterClass &RC = *MRI.getRegClass(VReg);
lib/CodeGen/RenameIndependentSubregs.cpp 133 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
lib/CodeGen/ScheduleDAGInstrs.cpp 365 const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
lib/CodeGen/SelectionDAG/FastISel.cpp 2232 const TargetRegisterClass *RC = MRI.getRegClass(Op0);
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 161 DstRC = MRI->getRegClass(VRBase);
233 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
451 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
517 TRC == MRI->getRegClass(SrcReg)) {
574 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
654 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp 325 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg);
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 958 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 529 MRI.constrainRegClass(To, MRI.getRegClass(From));
675 MRI.constrainRegClass(To, MRI.getRegClass(From));
lib/CodeGen/SplitKit.cpp 560 const TargetRegisterClass *RC = MRI.getRegClass(FromReg);
561 assert(RC == MRI.getRegClass(ToReg) && "Should have same reg class");
lib/CodeGen/TailDuplicator.cpp 241 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) {
348 const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
391 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
403 auto *OrigRC = MRI->getRegClass(Reg);
404 auto *MappedRC = MRI->getRegClass(VI->second.Reg);
lib/CodeGen/TargetInstrInfo.cpp 452 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
457 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
515 MF.getRegInfo().getRegClass(MO.getReg());
lib/CodeGen/TargetRegisterInfo.cpp 157 OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
488 RC = MRI.getRegClass(Reg);
lib/CodeGen/TwoAddressInstructionPass.cpp 1557 const TargetRegisterClass *RC = MRI->getRegClass(RegB);
1560 assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),
1566 assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))
lib/CodeGen/UnreachableBlockElim.cpp 186 MRI.constrainRegClass(InputReg, MRI.getRegClass(OutputReg)) &&
lib/CodeGen/VirtRegMap.cpp 123 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
144 << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
152 << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp 109 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass);
116 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) &&
118 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) &&
lib/Target/AArch64/AArch64FastISel.cpp 3894 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
lib/Target/AArch64/AArch64InstrInfo.cpp 436 bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg));
504 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
504 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
1077 } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) &&
3246 return Register::isVirtualRegister(Reg) ? MRI.getRegClass(Reg)
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 552 return MRI.getRegClass(Reg);
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp 1408 MRI->createVirtualRegister(MRI->getRegClass(DestReg));
1933 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectReg);
2000 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg);
2060 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
2176 MRI->getRegClass(CurrentBackedgeReg);
2313 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectRegIn);
2450 const TargetRegisterClass *RegClass = MRI->getRegClass(PHIDest);
2740 MRI->createVirtualRegister(MRI->getRegClass(InReg));
2741 Register NewInReg = MRI->createVirtualRegister(MRI->getRegClass(InReg));
lib/Target/AMDGPU/GCNNSAReassign.cpp 194 if (MRI->getRegClass(Reg) != &AMDGPU::VGPR_32RegClass || Op.getSubReg())
lib/Target/AMDGPU/GCNRegBankReassign.cpp 591 const TargetRegisterClass *RC = MRI->getRegClass(LI.reg);
lib/Target/AMDGPU/GCNRegPressure.cpp 88 const auto RC = MRI.getRegClass(Reg);
lib/Target/AMDGPU/R600MachineScheduler.cpp 215 return MRI->getRegClass(Reg) == RC;
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 160 if (TRI->hasVectorRegisters(MRI.getRegClass(MI.getOperand(i).getReg())))
174 ? MRI.getRegClass(SrcReg)
181 ? MRI.getRegClass(DstReg)
222 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg)));
246 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg)))
291 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
676 DstRC = MRI->getRegClass(MI.getOperand(0).getReg());
677 Src0RC = MRI->getRegClass(MI.getOperand(1).getReg());
678 Src1RC = MRI->getRegClass(MI.getOperand(2).getReg());
786 const TargetRegisterClass *UseRC = MRI->getRegClass(Use.getReg());
803 const TargetRegisterClass *RC0 = MRI->getRegClass(PHIRes);
lib/Target/AMDGPU/SIFixupVectorISel.cpp 127 IdxRC = MRI.getRegClass(MI->getOperand(1).getReg());
137 BaseRC = MRI.getRegClass(BaseReg);
143 if (!TRI->hasVGPRs(MRI.getRegClass(IndexReg)))
lib/Target/AMDGPU/SIFoldOperands.cpp 257 const TargetRegisterClass *Dst0RC = MRI.getRegClass(Dst0.getReg());
621 const TargetRegisterClass *DestRC = MRI->getRegClass(DestReg);
625 const TargetRegisterClass * SrcRC = MRI->getRegClass(SrcReg);
847 const TargetRegisterClass *UseRC = MRI->getRegClass(UseReg);
lib/Target/AMDGPU/SIFormMemoryClauses.cpp 161 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
lib/Target/AMDGPU/SIISelLowering.cpp 3343 const TargetRegisterClass *IdxRC = MRI.getRegClass(Idx->getReg());
3401 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcReg);
3493 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg());
lib/Target/AMDGPU/SIInstrInfo.cpp 481 ? MRI.getRegClass(Reg)
756 const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg);
823 assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass &&
2126 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
2127 assert(MRI.getRegClass(FalseReg) == RC);
2140 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
2141 assert(MRI.getRegClass(FalseReg) == RC);
2168 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
2374 if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))
2377 if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))
2444 RI.isSGPRClass(MRI->getRegClass(Src0->getReg())))))
2460 RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
3115 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
3816 return MRI.getRegClass(Reg);
3921 ? MRI.getRegClass(Reg)
4140 if (Src1.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) {
4146 if (Src2.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src2.getReg()))) {
4186 if (RI.hasAGPRs(MRI.getRegClass(MO.getReg())) &&
4192 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
4213 const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg);
4261 if (SBase && !RI.isSGPRClass(MRI.getRegClass(SBase->getReg()))) {
4266 if (SOff && !RI.isSGPRClass(MRI.getRegClass(SOff->getReg()))) {
4546 MRI.getRegClass(MI.getOperand(i).getReg());
4607 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg());
4625 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
4626 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
4638 if (Src.isReg() && RI.hasVectorRegisters(MRI.getRegClass(Src.getReg())))
4652 if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))) {
4658 if (SSamp && !RI.isSGPRClass(MRI.getRegClass(SSamp->getReg()))) {
4672 if (RI.getCommonSubClass(MRI.getRegClass(Rsrc->getReg()),
5191 RI.isSGPRClass(MRI.getRegClass(Src0.getReg()));
5193 RI.isSGPRClass(MRI.getRegClass(Src1.getReg()));
5300 MRI.getRegClass(Src0.getReg()) :
5308 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
5362 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());
5363 const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg());
5427 MRI.getRegClass(Src0.getReg()) :
5432 MRI.getRegClass(Src1.getReg()) :
5446 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
5489 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
5531 MRI.getRegClass(Src.getReg()) :
5821 const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);
lib/Target/AMDGPU/SIInstrInfo.h 823 getRegClass(MO.getReg()), SubReg)) >= 32 &&
1036 auto *RC = MRI.getRegClass(P.Reg);
lib/Target/AMDGPU/SILowerI1Copies.cpp 100 MRI->getRegClass(Reg) == &AMDGPU::VReg_1RegClass;
lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp 106 for (unsigned PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) {
lib/Target/AMDGPU/SIRegisterInfo.cpp 1693 return MRI.getRegClass(Reg);
lib/Target/AMDGPU/SIRegisterInfo.h 141 RC = MRI.getRegClass(Reg);
lib/Target/AMDGPU/SIWholeQuadMode.cpp 862 ? MRI->getRegClass(Reg)
lib/Target/ARM/A15SDOptimizer.cpp 139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
272 MRI->getRegClass(MI->getOperand(1).getReg());
273 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) {
518 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) ||
519 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) {
535 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) {
541 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) &&
642 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
lib/Target/ARM/ARMBaseInstrInfo.cpp 2250 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
3317 Register NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
lib/Target/ARM/ARMFastISel.cpp 2158 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
lib/Target/AVR/AVRISelDAGToDAG.cpp 219 RI.getRegClass(RegNode->getReg()) == &AVR::PTRDISPREGSRegClass) {
265 if (RI.getRegClass(Reg) != &AVR::PTRDISPREGSRegClass) {
lib/Target/BPF/BPFMIPeephole.cpp 110 MRI->getRegClass(Reg) == &BPF::GPRRegClass))
lib/Target/BPF/BPFMISimplifyPatchable.cpp 127 if (MRI->getRegClass(DstReg) == &BPF::GPR32RegClass) {
lib/Target/Hexagon/BitTracker.cpp 339 const auto &VC = composeWithSubRegIndex(*MRI.getRegClass(RR.Reg), RR.Sub);
360 const TargetRegisterClass *C = MRI.getRegClass(RR.Reg);
lib/Target/Hexagon/HexagonBitSimplify.cpp 406 const TargetRegisterClass *RC = MRI.getRegClass(RR.Reg);
436 auto &DstRC = *MRI.getRegClass(I.getOperand(0).getReg());
898 auto *RC = MRI.getRegClass(RR.Reg);
1478 unsigned ImmReg = genTfrConst(MRI.getRegClass(DR), C, B, At, DL);
1551 if (FRC != MRI.getRegClass(R))
1566 if (MRI.getRegClass(R) != &Hexagon::DoubleRegsRegClass)
1685 const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg);
1695 const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg);
2226 unsigned SRC = MRI.getRegClass(S)->getID();
2269 if (MRI.getRegClass(SrcR)->getID() == Hexagon::DoubleRegsRegClassID)
2342 const TargetRegisterClass *TC = MRI.getRegClass(V.RefI.Reg);
3070 const TargetRegisterClass *PhiRC = MRI->getRegClass(NewPredR);
3082 const TargetRegisterClass *RC = MRI->getRegClass(DR);
3282 const TargetRegisterClass *RC = MRI->getRegClass(G.Inp.Reg);
3283 if (RC != MRI->getRegClass(F->PR.Reg)) {
3300 if (MRI->getRegClass(PrehR) != MRI->getRegClass(G.Inp.Reg))
3300 if (MRI->getRegClass(PrehR) != MRI->getRegClass(G.Inp.Reg))
lib/Target/Hexagon/HexagonBitTracker.cpp 92 const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
964 if (MRI.getRegClass(DefR) == &Hexagon::PredRegsRegClass) {
lib/Target/Hexagon/HexagonBlockRanges.cpp 279 auto &RC = *MRI.getRegClass(R.Reg);
lib/Target/Hexagon/HexagonConstExtenders.cpp 1926 MRI->getRegClass(Op.getReg()) != &Hexagon::PredRegsRegClass)
lib/Target/Hexagon/HexagonConstPropagation.cpp 1944 const TargetRegisterClass &DefRC = *MRI->getRegClass(DefR.Reg);
2200 const TargetRegisterClass *RC = MRI->getRegClass(R.Reg);
2352 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
2857 const TargetRegisterClass *RC = MRI->getRegClass(R);
2982 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
3011 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
3048 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
3080 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 698 const TargetRegisterClass *RC = MRI->getRegClass(R);
841 const TargetRegisterClass *RC = MRI->getRegClass(DR);
999 const TargetRegisterClass *RC = MRI->getRegClass(DefR);
lib/Target/Hexagon/HexagonExpandCondsets.cpp 585 const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg);
1096 const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg);
lib/Target/Hexagon/HexagonFrameLowering.cpp 1959 SpillRCs.insert(MRI.getRegClass(VR));
lib/Target/Hexagon/HexagonGenInsert.cpp 681 const TargetRegisterClass *DstRC = MRI->getRegClass(DstR);
682 const TargetRegisterClass *SrcRC = MRI->getRegClass(SrcR);
683 const TargetRegisterClass *InsRC = MRI->getRegClass(InsR);
1401 const TargetRegisterClass *RC = MRI->getRegClass(VR);
1414 bool R32 = MRI->getRegClass(NewR) == &Hexagon::IntRegsRegClass;
1420 if (R32 && MRI->getRegClass(IF.InsR) == &Hexagon::DoubleRegsRegClass) {
lib/Target/Hexagon/HexagonGenPredicate.cpp 138 const TargetRegisterClass *RC = MRI->getRegClass(R);
335 if (MRI->getRegClass(PR.R) != PredRC)
434 const TargetRegisterClass *RC = MRI->getRegClass(OutR.R);
478 if (MRI->getRegClass(DR.R) != PredRC)
480 if (MRI->getRegClass(SR.R) != PredRC)
lib/Target/Hexagon/HexagonHardwareLoops.cpp 894 const TargetRegisterClass *RC = MRI->getRegClass(R);
1588 const TargetRegisterClass *RC = MRI->getRegClass(R);
1907 const TargetRegisterClass *RC = MRI->getRegClass(PR);
lib/Target/Hexagon/HexagonPeephole.cpp 241 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
lib/Target/Hexagon/HexagonSplitDouble.cpp 228 if (MRI->getRegClass(R) == DoubleRC)
266 if (MRI->getRegClass(T) != DoubleRC)
503 assert(MRI->getRegClass(PR) == &Hexagon::PredRegsRegClass);
517 if (CmpR1 && MRI->getRegClass(CmpR1) != DoubleRC)
519 if (CmpR2 && MRI->getRegClass(CmpR2) != DoubleRC)
539 if (MRI->getRegClass(R) == DoubleRC)
610 if (isVirtReg && MRI->getRegClass(R) == DoubleRC) {
676 const TargetRegisterClass *RC = MRI->getRegClass(UpdOp.getReg());
1006 if (MRI->getRegClass(DstR) == DoubleRC) {
1110 if (MRI->getRegClass(R) != DoubleRC || Op.getSubReg())
lib/Target/Hexagon/HexagonVExtract.cpp 124 const auto &VecRC = *MRI.getRegClass(VecR);
lib/Target/Lanai/LanaiInstrInfo.cpp 508 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
lib/Target/Mips/MipsFastISel.cpp 1733 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
lib/Target/Mips/MipsISelLowering.cpp 1481 Register Scratch = RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal));
1520 Register PtrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Ptr));
1521 Register IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr));
1752 Register PtrCopy = MRI.createVirtualRegister(MRI.getRegClass(Ptr));
1753 Register OldValCopy = MRI.createVirtualRegister(MRI.getRegClass(OldVal));
1754 Register NewValCopy = MRI.createVirtualRegister(MRI.getRegClass(NewVal));
lib/Target/Mips/MipsOptimizePICCall.cpp 139 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg);
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 118 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
lib/Target/Mips/MipsSEISelLowering.cpp 3523 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3575 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
lib/Target/NVPTX/NVPTXAsmPrinter.cpp 286 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
579 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
1655 const TargetRegisterClass *RC = MRI->getRegClass(vr);
lib/Target/NVPTX/NVPTXInstrInfo.cpp 37 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
38 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
lib/Target/PowerPC/PPCFastISel.cpp 469 (ResultReg ? MRI.getRegClass(ResultReg) :
613 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
629 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg);
867 auto RC1 = MRI.getRegClass(SrcReg1);
868 auto RC2 = SrcReg2 != 0 ? MRI.getRegClass(SrcReg2) : nullptr;
990 auto RC = MRI.getRegClass(SrcReg);
1177 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
1217 const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg);
1227 auto RC = MRI.getRegClass(SrcReg);
1282 (AssignedReg ? MRI.getRegClass(AssignedReg) :
1923 (AssignedReg ? MRI.getRegClass(AssignedReg) :
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 375 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
lib/Target/PowerPC/PPCISelLowering.cpp10623 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
11529 const TargetRegisterClass *RC = RegInfo.getRegClass(SrcReg);
11532 assert((RegInfo.getRegClass(DestReg) == &PPC::G8RCRegClass) &&
11539 assert((RegInfo.getRegClass(SrcReg) == &PPC::G8RCRegClass) &&
11540 (RegInfo.getRegClass(DestReg) == &PPC::F8RCRegClass) &&
lib/Target/PowerPC/PPCInstrInfo.cpp 192 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
193 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
770 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
770 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
803 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
803 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
861 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
862 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
864 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
3839 MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ?
lib/Target/PowerPC/PPCVSXCopy.cpp 54 return RC->hasSubClassEq(MRI.getRegClass(Reg));
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 131 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) !=
132 MRI.getRegClass(AddendSrcReg))
137 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg())
237 MRI.getRegClass(OldFMAReg)))
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 162 return RC->hasSubClassEq(MRI->getRegClass(Reg));
898 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
lib/Target/SystemZ/SystemZISelLowering.cpp 7520 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
lib/Target/SystemZ/SystemZInstrInfo.cpp 547 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
547 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
573 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
1040 .getRegClass(MI.getOperand(OpNum).getReg())) &&
lib/Target/SystemZ/SystemZRegisterInfo.cpp 32 const TargetRegisterClass *RC = MRI->getRegClass(MO.getReg());
90 if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) {
125 if (MRI->getRegClass(OtherReg) == &SystemZ::GRX32BitRegClass)
179 MRI->getRegClass(VirtReg));
lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp 59 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo);
lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp 242 const TargetRegisterClass *RC = MRI.getRegClass(OldReg);
275 const TargetRegisterClass *RC = MRI.getRegClass(OldReg);
347 const TargetRegisterClass *RC = MRI.getRegClass(OldReg);
378 typeForRegClass(MRI.getRegClass(Reg)));
lib/Target/WebAssembly/WebAssemblyFastISel.cpp 580 assert(MRI.getRegClass(Reg) == &WebAssembly::I32RegClass);
590 unsigned ResultReg = createResultReg(MRI.getRegClass(Reg));
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 375 Tmp0 = MRI.createVirtualRegister(MRI.getRegClass(InReg));
376 Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg));
379 FalseReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg));
380 TrueReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg));
396 Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg));
lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp 64 ? MRI.getRegClass(DestReg)
196 bool IsBrOnExn = Cond[1].isReg() && MRI.getRegClass(Cond[1].getReg()) ==
227 MRI.getRegClass(Cond[1].getReg()) == &WebAssembly::EXNREFRegClass)
lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp 242 Returns.push_back(getType(MRI.getRegClass(MO.getReg())));
245 Params.push_back(getType(MRI.getRegClass(MO.getReg())));
lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp 171 if (MRI.getRegClass(FromReg) != MRI.getRegClass(ToReg))
171 if (MRI.getRegClass(FromReg) != MRI.getRegClass(ToReg))
lib/Target/WebAssembly/WebAssemblyPeephole.cpp 66 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
170 if (MRI.getRegClass(NewReg) != MRI.getRegClass(OldReg))
170 if (MRI.getRegClass(NewReg) != MRI.getRegClass(OldReg))
lib/Target/WebAssembly/WebAssemblyRegColoring.cpp 140 const TargetRegisterClass *RC = MRI->getRegClass(Old);
145 if (MRI->getRegClass(SortedIntervals[C]->reg) != RC)
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 105 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg());
502 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(Reg));
538 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(Reg));
609 const auto *RegClass = MRI.getRegClass(Reg);
lib/Target/X86/X86CmovConversion.cpp 755 const TargetRegisterClass *RC = MRI->getRegClass(MI.getOperand(0).getReg());
lib/Target/X86/X86DomainReassignment.cpp 247 RegDomain OpDomain = getDomain(MRI->getRegClass(MO.getReg()),
445 RegDomain RD = getDomain(MRI->getRegClass(Reg), MRI->getTargetRegisterInfo());
511 MRI->setRegClass(Reg, getDstRC(MRI->getRegClass(Reg), Domain));
757 if (!isGPR(MRI->getRegClass(Reg)))
lib/Target/X86/X86FastISel.cpp 1247 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
1761 if (MRI.getRegClass(OpReg) == &X86::VK1RegClass) {
2107 if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) {
2325 if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) {
lib/Target/X86/X86FlagsCopyLowering.cpp 909 auto &SetBRC = *MRI->getRegClass(SetBI.getOperand(0).getReg());
916 auto &OrigRC = *MRI->getRegClass(Reg);
lib/Target/X86/X86ISelLowering.cpp29213 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
30486 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
lib/Target/X86/X86InstrInfo.cpp 766 *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
2845 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
2845 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
2872 const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
5077 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
lib/Target/X86/X86OptimizeLEAs.cpp 357 MRI->getRegClass(DefMI->getOperand(0).getReg()))
425 if (MRI->getRegClass(First.getOperand(0).getReg()) !=
426 MRI->getRegClass(Last.getOperand(0).getReg()))
lib/Target/X86/X86SpeculativeLoadHardening.cpp 2035 auto *OpRC = MRI->getRegClass(OpReg);
2238 auto *RC = MRI->getRegClass(Reg);
2286 auto *RC = MRI->getRegClass(Reg);
2336 auto *DefRC = MRI->getRegClass(OldDefReg);