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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenCallingConv.inc 89 static const MCPhysReg RegList1[] = {
92 static const MCPhysReg RegList2[] = {
160 static const MCPhysReg RegList3[] = {
189 static const MCPhysReg RegList4[] = {
219 static const MCPhysReg RegList5[] = {
222 static const MCPhysReg RegList6[] = {
233 static const MCPhysReg RegList7[] = {
236 static const MCPhysReg RegList8[] = {
248 static const MCPhysReg ShadowRegList9[] = {
258 static const MCPhysReg RegList11[] = {
261 static const MCPhysReg RegList12[] = {
271 static const MCPhysReg RegList13[] = {
274 static const MCPhysReg RegList14[] = {
284 static const MCPhysReg RegList15[] = {
287 static const MCPhysReg RegList16[] = {
297 static const MCPhysReg RegList17[] = {
300 static const MCPhysReg RegList18[] = {
316 static const MCPhysReg RegList19[] = {
319 static const MCPhysReg RegList20[] = {
336 static const MCPhysReg RegList21[] = {
463 static const MCPhysReg RegList1[] = {
466 static const MCPhysReg RegList2[] = {
477 static const MCPhysReg RegList3[] = {
480 static const MCPhysReg RegList4[] = {
492 static const MCPhysReg ShadowRegList5[] = {
502 static const MCPhysReg RegList7[] = {
505 static const MCPhysReg RegList8[] = {
515 static const MCPhysReg RegList9[] = {
518 static const MCPhysReg RegList10[] = {
528 static const MCPhysReg RegList11[] = {
531 static const MCPhysReg RegList12[] = {
541 static const MCPhysReg RegList13[] = {
544 static const MCPhysReg RegList14[] = {
560 static const MCPhysReg RegList15[] = {
563 static const MCPhysReg RegList16[] = {
579 static const MCPhysReg RegList17[] = {
847 static const MCPhysReg RegList1[] = {
857 static const MCPhysReg RegList2[] = {
867 static const MCPhysReg RegList3[] = {
889 static const MCPhysReg RegList4[] = {
1058 static const MCPhysReg RegList1[] = {
1061 static const MCPhysReg RegList2[] = {
1071 static const MCPhysReg RegList3[] = {
1074 static const MCPhysReg RegList4[] = {
1084 static const MCPhysReg RegList5[] = {
1087 static const MCPhysReg RegList6[] = {
1097 static const MCPhysReg RegList7[] = {
1100 static const MCPhysReg RegList8[] = {
1110 static const MCPhysReg RegList9[] = {
1113 static const MCPhysReg RegList10[] = {
1129 static const MCPhysReg RegList11[] = {
1132 static const MCPhysReg RegList12[] = {
1149 static const MCPhysReg RegList13[] = {
1170 static const MCPhysReg RegList14[] = {
1183 static const MCPhysReg RegList15[] = {
1201 static const MCPhysReg RegList1[] = {
1204 static const MCPhysReg RegList2[] = {
1214 static const MCPhysReg RegList3[] = {
1217 static const MCPhysReg RegList4[] = {
1227 static const MCPhysReg RegList5[] = {
1230 static const MCPhysReg RegList6[] = {
1240 static const MCPhysReg RegList7[] = {
1243 static const MCPhysReg RegList8[] = {
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 6392 static const MCPhysReg ImplicitList1[] = { AArch64::NZCV, 0 };
6393 static const MCPhysReg ImplicitList2[] = { AArch64::SP, 0 };
6394 static const MCPhysReg ImplicitList3[] = { AArch64::X16, AArch64::X17, 0 };
6395 static const MCPhysReg ImplicitList4[] = { AArch64::X17, 0 };
6396 static const MCPhysReg ImplicitList5[] = { AArch64::LR, AArch64::SP, 0 };
6397 static const MCPhysReg ImplicitList6[] = { AArch64::LR, 0 };
6398 static const MCPhysReg ImplicitList7[] = { AArch64::FFR, 0 };
6399 static const MCPhysReg ImplicitList8[] = { AArch64::X9, 0 };
6400 static const MCPhysReg ImplicitList9[] = { AArch64::X16, AArch64::X17, AArch64::LR, AArch64::NZCV, 0 };
6401 static const MCPhysReg ImplicitList10[] = { AArch64::LR, AArch64::X0, AArch64::X1, 0 };
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 908 extern const MCPhysReg AArch64RegDiffLists[] = {
2159 extern const MCPhysReg AArch64RegUnitRoots[][2] = {
2279 const MCPhysReg FPR8[] = {
2289 const MCPhysReg FPR16[] = {
2299 const MCPhysReg PPR[] = {
2309 const MCPhysReg PPR_3b[] = {
2319 const MCPhysReg GPR32all[] = {
2329 const MCPhysReg FPR32[] = {
2339 const MCPhysReg GPR32[] = {
2349 const MCPhysReg GPR32sp[] = {
2359 const MCPhysReg GPR32common[] = {
2369 const MCPhysReg GPR32arg[] = {
2379 const MCPhysReg CCR[] = {
2389 const MCPhysReg GPR32sponly[] = {
2399 const MCPhysReg WSeqPairsClass[] = {
2409 const MCPhysReg WSeqPairsClass_with_subo32_in_GPR32common[] = {
2419 const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32arg[] = {
2429 const MCPhysReg GPR64all[] = {
2439 const MCPhysReg FPR64[] = {
2449 const MCPhysReg GPR64[] = {
2459 const MCPhysReg GPR64sp[] = {
2469 const MCPhysReg GPR64common[] = {
2479 const MCPhysReg GPR64noip[] = {
2489 const MCPhysReg GPR64common_and_GPR64noip[] = {
2499 const MCPhysReg tcGPR64[] = {
2509 const MCPhysReg GPR64noip_and_tcGPR64[] = {
2519 const MCPhysReg GPR64arg[] = {
2529 const MCPhysReg rtcGPR64[] = {
2539 const MCPhysReg GPR64sponly[] = {
2549 const MCPhysReg DD[] = {
2559 const MCPhysReg XSeqPairsClass[] = {
2569 const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64common[] = {
2579 const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64noip[] = {
2589 const MCPhysReg XSeqPairsClass_with_sube64_in_GPR64noip[] = {
2599 const MCPhysReg XSeqPairsClass_with_sube64_in_tcGPR64[] = {
2609 const MCPhysReg XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64[] = {
2619 const MCPhysReg XSeqPairsClass_with_subo64_in_tcGPR64[] = {
2629 const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64[] = {
2639 const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32arg[] = {
2649 const MCPhysReg XSeqPairsClass_with_sube64_in_rtcGPR64[] = {
2659 const MCPhysReg FPR128[] = {
2669 const MCPhysReg ZPR[] = {
2679 const MCPhysReg FPR128_lo[] = {
2689 const MCPhysReg ZPR_4b[] = {
2699 const MCPhysReg ZPR_3b[] = {
2709 const MCPhysReg DDD[] = {
2719 const MCPhysReg DDDD[] = {
2729 const MCPhysReg QQ[] = {
2739 const MCPhysReg ZPR2[] = {
2749 const MCPhysReg QQ_with_qsub0_in_FPR128_lo[] = {
2759 const MCPhysReg QQ_with_qsub1_in_FPR128_lo[] = {
2769 const MCPhysReg ZPR2_with_zsub1_in_ZPR_4b[] = {
2779 const MCPhysReg ZPR2_with_zsub_in_FPR128_lo[] = {
2789 const MCPhysReg QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo[] = {
2799 const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b[] = {
2809 const MCPhysReg ZPR2_with_zsub0_in_ZPR_3b[] = {
2819 const MCPhysReg ZPR2_with_zsub1_in_ZPR_3b[] = {
2829 const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b[] = {
2839 const MCPhysReg QQQ[] = {
2849 const MCPhysReg ZPR3[] = {
2859 const MCPhysReg QQQ_with_qsub0_in_FPR128_lo[] = {
2869 const MCPhysReg QQQ_with_qsub1_in_FPR128_lo[] = {
2879 const MCPhysReg QQQ_with_qsub2_in_FPR128_lo[] = {
2889 const MCPhysReg ZPR3_with_zsub1_in_ZPR_4b[] = {
2899 const MCPhysReg ZPR3_with_zsub2_in_ZPR_4b[] = {
2909 const MCPhysReg ZPR3_with_zsub_in_FPR128_lo[] = {
2919 const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo[] = {
2929 const MCPhysReg QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
2939 const MCPhysReg ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b[] = {
2949 const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b[] = {
2959 const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
2969 const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b[] = {
2979 const MCPhysReg ZPR3_with_zsub0_in_ZPR_3b[] = {
2989 const MCPhysReg ZPR3_with_zsub1_in_ZPR_3b[] = {
2999 const MCPhysReg ZPR3_with_zsub2_in_ZPR_3b[] = {
3009 const MCPhysReg ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b[] = {
3019 const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b[] = {
3029 const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b[] = {
3039 const MCPhysReg QQQQ[] = {
3049 const MCPhysReg ZPR4[] = {
3059 const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo[] = {
3069 const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo[] = {
3079 const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo[] = {
3089 const MCPhysReg QQQQ_with_qsub3_in_FPR128_lo[] = {
3099 const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b[] = {
3109 const MCPhysReg ZPR4_with_zsub2_in_ZPR_4b[] = {
3119 const MCPhysReg ZPR4_with_zsub3_in_ZPR_4b[] = {
3129 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo[] = {
3139 const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo[] = {
3149 const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
3159 const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
3169 const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b[] = {
3179 const MCPhysReg ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b[] = {
3189 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b[] = {
3199 const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
3209 const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
3219 const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b[] = {
3229 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b[] = {
3239 const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
3249 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b[] = {
3259 const MCPhysReg ZPR4_with_zsub0_in_ZPR_3b[] = {
3269 const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b[] = {
3279 const MCPhysReg ZPR4_with_zsub2_in_ZPR_3b[] = {
3289 const MCPhysReg ZPR4_with_zsub3_in_ZPR_3b[] = {
3299 const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b[] = {
3309 const MCPhysReg ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b[] = {
3319 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b[] = {
3329 const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b[] = {
3339 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b[] = {
3349 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b[] = {
6810 static ArrayRef<MCPhysReg> GPR32GetRawAllocationOrder(const MachineFunction &MF) {
6811 static const MCPhysReg AltOrder1[] = { AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 };
6813 const ArrayRef<MCPhysReg> Order[] = {
6824 static ArrayRef<MCPhysReg> GPR32spGetRawAllocationOrder(const MachineFunction &MF) {
6825 static const MCPhysReg AltOrder1[] = { AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 };
6827 const ArrayRef<MCPhysReg> Order[] = {
6838 static ArrayRef<MCPhysReg> GPR32commonGetRawAllocationOrder(const MachineFunction &MF) {
6839 static const MCPhysReg AltOrder1[] = { AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 };
6841 const ArrayRef<MCPhysReg> Order[] = {
6852 static ArrayRef<MCPhysReg> GPR64GetRawAllocationOrder(const MachineFunction &MF) {
6853 static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 };
6855 const ArrayRef<MCPhysReg> Order[] = {
6866 static ArrayRef<MCPhysReg> GPR64spGetRawAllocationOrder(const MachineFunction &MF) {
6867 static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 };
6869 const ArrayRef<MCPhysReg> Order[] = {
6880 static ArrayRef<MCPhysReg> GPR64commonGetRawAllocationOrder(const MachineFunction &MF) {
6881 static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 };
6883 const ArrayRef<MCPhysReg> Order[] = {
20338 extern const MCPhysReg AArch64RegDiffLists[];
20342 extern const MCPhysReg AArch64RegUnitRoots[][2];
20408 static const MCPhysReg CSR_AArch64_AAPCS_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, 0 };
20410 static const MCPhysReg CSR_AArch64_AAPCS_SCS_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X18, 0 };
20412 static const MCPhysReg CSR_AArch64_AAPCS_SwiftError_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, 0 };
20414 static const MCPhysReg CSR_AArch64_AAPCS_SwiftError_SCS_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X18, 0 };
20416 static const MCPhysReg CSR_AArch64_AAPCS_ThisReturn_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X0, 0 };
20418 static const MCPhysReg CSR_AArch64_AAVPCS_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, 0 };
20420 static const MCPhysReg CSR_AArch64_AAVPCS_SCS_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::X18, 0 };
20422 static const MCPhysReg CSR_AArch64_AllRegs_SaveList[] = { AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, AArch64::B30, AArch64::B31, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, AArch64::H30, AArch64::H31, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, AArch64::S30, AArch64::S31, AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
20424 static const MCPhysReg CSR_AArch64_AllRegs_SCS_SaveList[] = { AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, AArch64::B30, AArch64::B31, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, AArch64::H30, AArch64::H31, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, AArch64::S30, AArch64::S31, AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
20426 static const MCPhysReg CSR_AArch64_CXX_TLS_Darwin_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, 0 };
20428 static const MCPhysReg CSR_AArch64_CXX_TLS_Darwin_PE_SaveList[] = { AArch64::LR, AArch64::FP, 0 };
20430 static const MCPhysReg CSR_AArch64_CXX_TLS_Darwin_SCS_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, AArch64::X18, 0 };
20432 static const MCPhysReg CSR_AArch64_CXX_TLS_Darwin_ViaCopy_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, 0 };
20434 static const MCPhysReg CSR_AArch64_NoRegs_SaveList[] = { 0 };
20436 static const MCPhysReg CSR_AArch64_NoRegs_SCS_SaveList[] = { AArch64::X18, 0 };
20438 static const MCPhysReg CSR_AArch64_RT_MostRegs_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, 0 };
20440 static const MCPhysReg CSR_AArch64_RT_MostRegs_SCS_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18, 0 };
20442 static const MCPhysReg CSR_AArch64_SVE_AAPCS_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15, 0 };
20444 static const MCPhysReg CSR_AArch64_StackProbe_Windows_SaveList[] = { AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::SP, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
20446 static const MCPhysReg CSR_AArch64_TLS_Darwin_SaveList[] = { AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
20448 static const MCPhysReg CSR_AArch64_TLS_ELF_SaveList[] = { AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
20450 static const MCPhysReg CSR_Darwin_AArch64_AAPCS_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, 0 };
20452 static const MCPhysReg CSR_Win_AArch64_AAPCS_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, 0 };
20454 static const MCPhysReg CSR_Win_AArch64_CFGuard_Check_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, 0 };
gen/lib/Target/AMDGPU/AMDGPUGenCallingConv.inc 84 static const MCPhysReg RegList1[] = {
165 static const MCPhysReg RegList1[] = {
181 static const MCPhysReg RegList2[] = {
228 static const MCPhysReg RegList1[] = {
246 static const MCPhysReg RegList1[] = {
258 static const MCPhysReg RegList2[] = {
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc15329 static const MCPhysReg ImplicitList1[] = { AMDGPU::SCC, 0 };
15330 static const MCPhysReg ImplicitList2[] = { AMDGPU::EXEC, 0 };
15331 static const MCPhysReg ImplicitList3[] = { AMDGPU::EXEC, AMDGPU::M0, 0 };
15332 static const MCPhysReg ImplicitList4[] = { AMDGPU::M0, AMDGPU::EXEC, 0 };
15333 static const MCPhysReg ImplicitList5[] = { AMDGPU::EXEC, AMDGPU::FLAT_SCR, 0 };
15334 static const MCPhysReg ImplicitList6[] = { AMDGPU::EXEC, AMDGPU::SCC, 0 };
15335 static const MCPhysReg ImplicitList7[] = { AMDGPU::EXEC, AMDGPU::VCC, 0 };
15336 static const MCPhysReg ImplicitList8[] = { AMDGPU::M0, AMDGPU::EXEC, AMDGPU::SCC, 0 };
15337 static const MCPhysReg ImplicitList9[] = { AMDGPU::EXEC_LO, 0 };
15338 static const MCPhysReg ImplicitList10[] = { AMDGPU::M0, 0 };
15339 static const MCPhysReg ImplicitList11[] = { AMDGPU::EXEC, AMDGPU::VCC, AMDGPU::SCC, 0 };
15340 static const MCPhysReg ImplicitList12[] = { AMDGPU::FLAT_SCR, 0 };
15341 static const MCPhysReg ImplicitList13[] = { AMDGPU::VCC, AMDGPU::EXEC, 0 };
15342 static const MCPhysReg ImplicitList14[] = { AMDGPU::VCC, 0 };
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc 4032 extern const MCPhysReg AMDGPURegDiffLists[] = {
9300 extern const MCPhysReg AMDGPURegUnitRoots[][2] = {
10004 const MCPhysReg SCC_CLASS[] = {
10014 const MCPhysReg SReg_1[] = {
10024 const MCPhysReg SReg_1_XEXEC[] = {
10034 const MCPhysReg SReg_1_with_sub0[] = {
10044 const MCPhysReg SReg_1_XEXEC_with_sub0[] = {
10054 const MCPhysReg SReg_1_with_sub0_with_sub0_in_SGPR_32[] = {
10064 const MCPhysReg SReg_1_with_sub0_with_sub0_in_TTMP_32[] = {
10074 const MCPhysReg VReg_1[] = {
10084 const MCPhysReg AV_32[] = {
10094 const MCPhysReg VS_32[] = {
10104 const MCPhysReg VRegOrLds_32[] = {
10114 const MCPhysReg AGPR_32[] = {
10124 const MCPhysReg VGPR_32[] = {
10134 const MCPhysReg SRegOrLds_32[] = {
10144 const MCPhysReg SReg_32[] = {
10154 const MCPhysReg SReg_32_XEXEC_HI[] = {
10164 const MCPhysReg SReg_32_XM0[] = {
10174 const MCPhysReg SRegOrLds_32_and_SReg_1[] = {
10184 const MCPhysReg SReg_32_XM0_XEXEC[] = {
10194 const MCPhysReg SGPR_32[] = {
10204 const MCPhysReg TTMP_32[] = {
10214 const MCPhysReg Pseudo_SReg_32[] = {
10224 const MCPhysReg LDS_DIRECT_CLASS[] = {
10234 const MCPhysReg M0_CLASS[] = {
10244 const MCPhysReg AV_64[] = {
10254 const MCPhysReg VS_64[] = {
10264 const MCPhysReg AReg_64[] = {
10274 const MCPhysReg VReg_64[] = {
10284 const MCPhysReg SReg_64[] = {
10294 const MCPhysReg SReg_64_XEXEC[] = {
10304 const MCPhysReg SGPR_64[] = {
10314 const MCPhysReg CCR_SGPR_64[] = {
10324 const MCPhysReg TTMP_64[] = {
10334 const MCPhysReg VReg_96[] = {
10344 const MCPhysReg SGPR_96[] = {
10354 const MCPhysReg SReg_96[] = {
10364 const MCPhysReg SGPR_96_with_sub0_sub1[] = {
10374 const MCPhysReg SGPR_96_with_sub1_sub2[] = {
10384 const MCPhysReg SGPR_96_with_sub0_sub1_with_sub0_sub1_in_CCR_SGPR_64[] = {
10394 const MCPhysReg SGPR_96_with_sub1_sub2_with_sub1_sub2_in_CCR_SGPR_64[] = {
10404 const MCPhysReg AReg_128[] = {
10414 const MCPhysReg VReg_128[] = {
10424 const MCPhysReg SReg_128[] = {
10434 const MCPhysReg SGPR_128[] = {
10444 const MCPhysReg SGPR_128_with_sub0_sub1_sub2[] = {
10454 const MCPhysReg SGPR_128_with_sub0_sub1_in_CCR_SGPR_64[] = {
10464 const MCPhysReg SGPR_128_with_sub1_sub2_sub3[] = {
10474 const MCPhysReg TTMP_128[] = {
10484 const MCPhysReg SGPR_128_with_sub0_sub1_sub2_and_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64[] = {
10494 const MCPhysReg SGPR_128_with_sub1_sub2_sub3_and_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64[] = {
10504 const MCPhysReg Pseudo_SReg_128[] = {
10514 const MCPhysReg VReg_160[] = {
10524 const MCPhysReg SGPR_160[] = {
10534 const MCPhysReg SReg_160[] = {
10544 const MCPhysReg SGPR_160_with_sub0_sub1_sub2[] = {
10554 const MCPhysReg SGPR_160_with_sub2_sub3_sub4[] = {
10564 const MCPhysReg SGPR_160_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64[] = {
10574 const MCPhysReg SGPR_160_with_sub1_sub2_sub3[] = {
10584 const MCPhysReg SGPR_160_with_sub0_sub1_sub2_and_SGPR_160_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64[] = {
10594 const MCPhysReg SGPR_160_with_sub2_sub3_sub4_and_SGPR_160_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64[] = {
10604 const MCPhysReg SGPR_160_with_sub1_sub2_sub3_and_SGPR_160_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64[] = {
10614 const MCPhysReg VReg_256[] = {
10624 const MCPhysReg SReg_256[] = {
10634 const MCPhysReg SGPR_256[] = {
10644 const MCPhysReg SGPR_256_with_sub0_sub1_sub2[] = {
10654 const MCPhysReg SGPR_256_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64[] = {
10664 const MCPhysReg SGPR_256_with_sub1_sub2_sub3[] = {
10674 const MCPhysReg SGPR_256_with_sub2_sub3_sub4[] = {
10684 const MCPhysReg SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64[] = {
10694 const MCPhysReg SGPR_256_with_sub0_sub1_sub2_and_SGPR_256_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64[] = {
10704 const MCPhysReg SGPR_256_with_sub2_sub3_sub4_and_SGPR_256_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64[] = {
10714 const MCPhysReg TTMP_256[] = {
10724 const MCPhysReg SGPR_256_with_sub1_sub2_sub3_and_SGPR_256_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64[] = {
10734 const MCPhysReg SGPR_256_with_sub2_sub3_sub4_and_SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64[] = {
10744 const MCPhysReg AReg_512[] = {
10754 const MCPhysReg VReg_512[] = {
10764 const MCPhysReg SReg_512[] = {
10774 const MCPhysReg SGPR_512[] = {
10784 const MCPhysReg SGPR_512_with_sub0_sub1_sub2[] = {
10794 const MCPhysReg SGPR_512_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64[] = {
10804 const MCPhysReg SGPR_512_with_sub2_sub3_sub4[] = {
10814 const MCPhysReg SGPR_512_with_sub1_sub2_sub3[] = {
10824 const MCPhysReg SGPR_512_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64[] = {
10834 const MCPhysReg SGPR_512_with_sub8_sub9_sub10_sub11_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64[] = {
10844 const MCPhysReg SGPR_512_with_sub12_sub13_sub14_sub15_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64[] = {
10854 const MCPhysReg SGPR_512_with_sub0_sub1_sub2_and_SGPR_512_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64[] = {
10864 const MCPhysReg SGPR_512_with_sub2_sub3_sub4_and_SGPR_512_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64[] = {
10874 const MCPhysReg SGPR_512_with_sub0_sub1_sub2_and_SGPR_512_with_sub8_sub9_sub10_sub11_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64[] = {
10884 const MCPhysReg SGPR_512_with_sub1_sub2_sub3_and_SGPR_512_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64[] = {
10894 const MCPhysReg SGPR_512_with_sub2_sub3_sub4_and_SGPR_512_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64[] = {
10904 const MCPhysReg SGPR_512_with_sub1_sub2_sub3_and_SGPR_512_with_sub12_sub13_sub14_sub15_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64[] = {
10914 const MCPhysReg TTMP_512[] = {
10924 const MCPhysReg AReg_1024[] = {
10934 const MCPhysReg VReg_1024[] = {
10944 const MCPhysReg SGPR_1024[] = {
10954 const MCPhysReg SReg_1024[] = {
10964 const MCPhysReg SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64[] = {
10974 const MCPhysReg SGPR_1024_with_sub0_sub1_sub2[] = {
10984 const MCPhysReg SGPR_1024_with_sub4_sub5_in_CCR_SGPR_64[] = {
10994 const MCPhysReg SGPR_1024_with_sub1_sub2_sub3[] = {
11004 const MCPhysReg SGPR_1024_with_sub2_sub3_sub4[] = {
11014 const MCPhysReg SGPR_1024_with_sub8_sub9_in_CCR_SGPR_64[] = {
11024 const MCPhysReg SGPR_1024_with_sub12_sub13_in_CCR_SGPR_64[] = {
11034 const MCPhysReg SGPR_1024_with_sub16_sub17_in_CCR_SGPR_64[] = {
11044 const MCPhysReg SGPR_1024_with_sub0_sub1_sub2_and_SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64[] = {
11054 const MCPhysReg SGPR_1024_with_sub20_sub21_in_CCR_SGPR_64[] = {
11064 const MCPhysReg SGPR_1024_with_sub2_sub3_sub4_and_SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64[] = {
11074 const MCPhysReg SGPR_1024_with_sub0_sub1_sub2_and_SGPR_1024_with_sub8_sub9_in_CCR_SGPR_64[] = {
11084 const MCPhysReg SGPR_1024_with_sub1_sub2_sub3_and_SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64[] = {
11094 const MCPhysReg SGPR_1024_with_sub24_sub25_in_CCR_SGPR_64[] = {
11104 const MCPhysReg SGPR_1024_with_sub2_sub3_sub4_and_SGPR_1024_with_sub4_sub5_in_CCR_SGPR_64[] = {
11114 const MCPhysReg SGPR_1024_with_sub1_sub2_sub3_and_SGPR_1024_with_sub12_sub13_in_CCR_SGPR_64[] = {
11124 const MCPhysReg SGPR_1024_with_sub28_sub29_in_CCR_SGPR_64[] = {
11134 const MCPhysReg SGPR_1024_with_sub2_sub3_sub4_and_SGPR_1024_with_sub16_sub17_in_CCR_SGPR_64[] = {
48699 extern const MCPhysReg AMDGPURegDiffLists[];
48703 extern const MCPhysReg AMDGPURegUnitRoots[][2];
48769 static const MCPhysReg CSR_AMDGPU_AllAllocatableSRegs_SaveList[] = { AMDGPU::SGPR0, AMDGPU::SGPR1, AMDGPU::SGPR2, AMDGPU::SGPR3, AMDGPU::SGPR4, AMDGPU::SGPR5, AMDGPU::SGPR6, AMDGPU::SGPR7, AMDGPU::SGPR8, AMDGPU::SGPR9, AMDGPU::SGPR10, AMDGPU::SGPR11, AMDGPU::SGPR12, AMDGPU::SGPR13, AMDGPU::SGPR14, AMDGPU::SGPR15, AMDGPU::SGPR16, AMDGPU::SGPR17, AMDGPU::SGPR18, AMDGPU::SGPR19, AMDGPU::SGPR20, AMDGPU::SGPR21, AMDGPU::SGPR22, AMDGPU::SGPR23, AMDGPU::SGPR24, AMDGPU::SGPR25, AMDGPU::SGPR26, AMDGPU::SGPR27, AMDGPU::SGPR28, AMDGPU::SGPR29, AMDGPU::SGPR30, AMDGPU::SGPR31, AMDGPU::SGPR32, AMDGPU::SGPR33, AMDGPU::SGPR34, AMDGPU::SGPR35, AMDGPU::SGPR36, AMDGPU::SGPR37, AMDGPU::SGPR38, AMDGPU::SGPR39, AMDGPU::SGPR40, AMDGPU::SGPR41, AMDGPU::SGPR42, AMDGPU::SGPR43, AMDGPU::SGPR44, AMDGPU::SGPR45, AMDGPU::SGPR46, AMDGPU::SGPR47, AMDGPU::SGPR48, AMDGPU::SGPR49, AMDGPU::SGPR50, AMDGPU::SGPR51, AMDGPU::SGPR52, AMDGPU::SGPR53, AMDGPU::SGPR54, AMDGPU::SGPR55, AMDGPU::SGPR56, AMDGPU::SGPR57, AMDGPU::SGPR58, AMDGPU::SGPR59, AMDGPU::SGPR60, AMDGPU::SGPR61, AMDGPU::SGPR62, AMDGPU::SGPR63, AMDGPU::SGPR64, AMDGPU::SGPR65, AMDGPU::SGPR66, AMDGPU::SGPR67, AMDGPU::SGPR68, AMDGPU::SGPR69, AMDGPU::SGPR70, AMDGPU::SGPR71, AMDGPU::SGPR72, AMDGPU::SGPR73, AMDGPU::SGPR74, AMDGPU::SGPR75, AMDGPU::SGPR76, AMDGPU::SGPR77, AMDGPU::SGPR78, AMDGPU::SGPR79, AMDGPU::SGPR80, AMDGPU::SGPR81, AMDGPU::SGPR82, AMDGPU::SGPR83, AMDGPU::SGPR84, AMDGPU::SGPR85, AMDGPU::SGPR86, AMDGPU::SGPR87, AMDGPU::SGPR88, AMDGPU::SGPR89, AMDGPU::SGPR90, AMDGPU::SGPR91, AMDGPU::SGPR92, AMDGPU::SGPR93, AMDGPU::SGPR94, AMDGPU::SGPR95, AMDGPU::SGPR96, AMDGPU::SGPR97, AMDGPU::SGPR98, AMDGPU::SGPR99, AMDGPU::SGPR100, AMDGPU::SGPR101, AMDGPU::SGPR102, AMDGPU::SGPR103, AMDGPU::SGPR104, AMDGPU::SGPR105, AMDGPU::VCC_LO, AMDGPU::VCC_HI, 0 };
48771 static const MCPhysReg CSR_AMDGPU_AllVGPRs_SaveList[] = { AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31, AMDGPU::VGPR32, AMDGPU::VGPR33, AMDGPU::VGPR34, AMDGPU::VGPR35, AMDGPU::VGPR36, AMDGPU::VGPR37, AMDGPU::VGPR38, AMDGPU::VGPR39, AMDGPU::VGPR40, AMDGPU::VGPR41, AMDGPU::VGPR42, AMDGPU::VGPR43, AMDGPU::VGPR44, AMDGPU::VGPR45, AMDGPU::VGPR46, AMDGPU::VGPR47, AMDGPU::VGPR48, AMDGPU::VGPR49, AMDGPU::VGPR50, AMDGPU::VGPR51, AMDGPU::VGPR52, AMDGPU::VGPR53, AMDGPU::VGPR54, AMDGPU::VGPR55, AMDGPU::VGPR56, AMDGPU::VGPR57, AMDGPU::VGPR58, AMDGPU::VGPR59, AMDGPU::VGPR60, AMDGPU::VGPR61, AMDGPU::VGPR62, AMDGPU::VGPR63, AMDGPU::VGPR64, AMDGPU::VGPR65, AMDGPU::VGPR66, AMDGPU::VGPR67, AMDGPU::VGPR68, AMDGPU::VGPR69, AMDGPU::VGPR70, AMDGPU::VGPR71, AMDGPU::VGPR72, AMDGPU::VGPR73, AMDGPU::VGPR74, AMDGPU::VGPR75, AMDGPU::VGPR76, AMDGPU::VGPR77, AMDGPU::VGPR78, AMDGPU::VGPR79, AMDGPU::VGPR80, AMDGPU::VGPR81, AMDGPU::VGPR82, AMDGPU::VGPR83, AMDGPU::VGPR84, AMDGPU::VGPR85, AMDGPU::VGPR86, AMDGPU::VGPR87, AMDGPU::VGPR88, AMDGPU::VGPR89, AMDGPU::VGPR90, AMDGPU::VGPR91, AMDGPU::VGPR92, AMDGPU::VGPR93, AMDGPU::VGPR94, AMDGPU::VGPR95, AMDGPU::VGPR96, AMDGPU::VGPR97, AMDGPU::VGPR98, AMDGPU::VGPR99, AMDGPU::VGPR100, AMDGPU::VGPR101, AMDGPU::VGPR102, AMDGPU::VGPR103, AMDGPU::VGPR104, AMDGPU::VGPR105, AMDGPU::VGPR106, AMDGPU::VGPR107, AMDGPU::VGPR108, AMDGPU::VGPR109, AMDGPU::VGPR110, AMDGPU::VGPR111, AMDGPU::VGPR112, AMDGPU::VGPR113, AMDGPU::VGPR114, AMDGPU::VGPR115, AMDGPU::VGPR116, AMDGPU::VGPR117, AMDGPU::VGPR118, AMDGPU::VGPR119, AMDGPU::VGPR120, AMDGPU::VGPR121, AMDGPU::VGPR122, AMDGPU::VGPR123, AMDGPU::VGPR124, AMDGPU::VGPR125, AMDGPU::VGPR126, AMDGPU::VGPR127, AMDGPU::VGPR128, AMDGPU::VGPR129, AMDGPU::VGPR130, AMDGPU::VGPR131, AMDGPU::VGPR132, AMDGPU::VGPR133, AMDGPU::VGPR134, AMDGPU::VGPR135, AMDGPU::VGPR136, AMDGPU::VGPR137, AMDGPU::VGPR138, AMDGPU::VGPR139, AMDGPU::VGPR140, AMDGPU::VGPR141, AMDGPU::VGPR142, AMDGPU::VGPR143, AMDGPU::VGPR144, AMDGPU::VGPR145, AMDGPU::VGPR146, AMDGPU::VGPR147, AMDGPU::VGPR148, AMDGPU::VGPR149, AMDGPU::VGPR150, AMDGPU::VGPR151, AMDGPU::VGPR152, AMDGPU::VGPR153, AMDGPU::VGPR154, AMDGPU::VGPR155, AMDGPU::VGPR156, AMDGPU::VGPR157, AMDGPU::VGPR158, AMDGPU::VGPR159, AMDGPU::VGPR160, AMDGPU::VGPR161, AMDGPU::VGPR162, AMDGPU::VGPR163, AMDGPU::VGPR164, AMDGPU::VGPR165, AMDGPU::VGPR166, AMDGPU::VGPR167, AMDGPU::VGPR168, AMDGPU::VGPR169, AMDGPU::VGPR170, AMDGPU::VGPR171, AMDGPU::VGPR172, AMDGPU::VGPR173, AMDGPU::VGPR174, AMDGPU::VGPR175, AMDGPU::VGPR176, AMDGPU::VGPR177, AMDGPU::VGPR178, AMDGPU::VGPR179, AMDGPU::VGPR180, AMDGPU::VGPR181, AMDGPU::VGPR182, AMDGPU::VGPR183, AMDGPU::VGPR184, AMDGPU::VGPR185, AMDGPU::VGPR186, AMDGPU::VGPR187, AMDGPU::VGPR188, AMDGPU::VGPR189, AMDGPU::VGPR190, AMDGPU::VGPR191, AMDGPU::VGPR192, AMDGPU::VGPR193, AMDGPU::VGPR194, AMDGPU::VGPR195, AMDGPU::VGPR196, AMDGPU::VGPR197, AMDGPU::VGPR198, AMDGPU::VGPR199, AMDGPU::VGPR200, AMDGPU::VGPR201, AMDGPU::VGPR202, AMDGPU::VGPR203, AMDGPU::VGPR204, AMDGPU::VGPR205, AMDGPU::VGPR206, AMDGPU::VGPR207, AMDGPU::VGPR208, AMDGPU::VGPR209, AMDGPU::VGPR210, AMDGPU::VGPR211, AMDGPU::VGPR212, AMDGPU::VGPR213, AMDGPU::VGPR214, AMDGPU::VGPR215, AMDGPU::VGPR216, AMDGPU::VGPR217, AMDGPU::VGPR218, AMDGPU::VGPR219, AMDGPU::VGPR220, AMDGPU::VGPR221, AMDGPU::VGPR222, AMDGPU::VGPR223, AMDGPU::VGPR224, AMDGPU::VGPR225, AMDGPU::VGPR226, AMDGPU::VGPR227, AMDGPU::VGPR228, AMDGPU::VGPR229, AMDGPU::VGPR230, AMDGPU::VGPR231, AMDGPU::VGPR232, AMDGPU::VGPR233, AMDGPU::VGPR234, AMDGPU::VGPR235, AMDGPU::VGPR236, AMDGPU::VGPR237, AMDGPU::VGPR238, AMDGPU::VGPR239, AMDGPU::VGPR240, AMDGPU::VGPR241, AMDGPU::VGPR242, AMDGPU::VGPR243, AMDGPU::VGPR244, AMDGPU::VGPR245, AMDGPU::VGPR246, AMDGPU::VGPR247, AMDGPU::VGPR248, AMDGPU::VGPR249, AMDGPU::VGPR250, AMDGPU::VGPR251, AMDGPU::VGPR252, AMDGPU::VGPR253, AMDGPU::VGPR254, AMDGPU::VGPR255, 0 };
48773 static const MCPhysReg CSR_AMDGPU_HighRegs_SaveList[] = { AMDGPU::VGPR32, AMDGPU::VGPR33, AMDGPU::VGPR34, AMDGPU::VGPR35, AMDGPU::VGPR36, AMDGPU::VGPR37, AMDGPU::VGPR38, AMDGPU::VGPR39, AMDGPU::VGPR40, AMDGPU::VGPR41, AMDGPU::VGPR42, AMDGPU::VGPR43, AMDGPU::VGPR44, AMDGPU::VGPR45, AMDGPU::VGPR46, AMDGPU::VGPR47, AMDGPU::VGPR48, AMDGPU::VGPR49, AMDGPU::VGPR50, AMDGPU::VGPR51, AMDGPU::VGPR52, AMDGPU::VGPR53, AMDGPU::VGPR54, AMDGPU::VGPR55, AMDGPU::VGPR56, AMDGPU::VGPR57, AMDGPU::VGPR58, AMDGPU::VGPR59, AMDGPU::VGPR60, AMDGPU::VGPR61, AMDGPU::VGPR62, AMDGPU::VGPR63, AMDGPU::VGPR64, AMDGPU::VGPR65, AMDGPU::VGPR66, AMDGPU::VGPR67, AMDGPU::VGPR68, AMDGPU::VGPR69, AMDGPU::VGPR70, AMDGPU::VGPR71, AMDGPU::VGPR72, AMDGPU::VGPR73, AMDGPU::VGPR74, AMDGPU::VGPR75, AMDGPU::VGPR76, AMDGPU::VGPR77, AMDGPU::VGPR78, AMDGPU::VGPR79, AMDGPU::VGPR80, AMDGPU::VGPR81, AMDGPU::VGPR82, AMDGPU::VGPR83, AMDGPU::VGPR84, AMDGPU::VGPR85, AMDGPU::VGPR86, AMDGPU::VGPR87, AMDGPU::VGPR88, AMDGPU::VGPR89, AMDGPU::VGPR90, AMDGPU::VGPR91, AMDGPU::VGPR92, AMDGPU::VGPR93, AMDGPU::VGPR94, AMDGPU::VGPR95, AMDGPU::VGPR96, AMDGPU::VGPR97, AMDGPU::VGPR98, AMDGPU::VGPR99, AMDGPU::VGPR100, AMDGPU::VGPR101, AMDGPU::VGPR102, AMDGPU::VGPR103, AMDGPU::VGPR104, AMDGPU::VGPR105, AMDGPU::VGPR106, AMDGPU::VGPR107, AMDGPU::VGPR108, AMDGPU::VGPR109, AMDGPU::VGPR110, AMDGPU::VGPR111, AMDGPU::VGPR112, AMDGPU::VGPR113, AMDGPU::VGPR114, AMDGPU::VGPR115, AMDGPU::VGPR116, AMDGPU::VGPR117, AMDGPU::VGPR118, AMDGPU::VGPR119, AMDGPU::VGPR120, AMDGPU::VGPR121, AMDGPU::VGPR122, AMDGPU::VGPR123, AMDGPU::VGPR124, AMDGPU::VGPR125, AMDGPU::VGPR126, AMDGPU::VGPR127, AMDGPU::VGPR128, AMDGPU::VGPR129, AMDGPU::VGPR130, AMDGPU::VGPR131, AMDGPU::VGPR132, AMDGPU::VGPR133, AMDGPU::VGPR134, AMDGPU::VGPR135, AMDGPU::VGPR136, AMDGPU::VGPR137, AMDGPU::VGPR138, AMDGPU::VGPR139, AMDGPU::VGPR140, AMDGPU::VGPR141, AMDGPU::VGPR142, AMDGPU::VGPR143, AMDGPU::VGPR144, AMDGPU::VGPR145, AMDGPU::VGPR146, AMDGPU::VGPR147, AMDGPU::VGPR148, AMDGPU::VGPR149, AMDGPU::VGPR150, AMDGPU::VGPR151, AMDGPU::VGPR152, AMDGPU::VGPR153, AMDGPU::VGPR154, AMDGPU::VGPR155, AMDGPU::VGPR156, AMDGPU::VGPR157, AMDGPU::VGPR158, AMDGPU::VGPR159, AMDGPU::VGPR160, AMDGPU::VGPR161, AMDGPU::VGPR162, AMDGPU::VGPR163, AMDGPU::VGPR164, AMDGPU::VGPR165, AMDGPU::VGPR166, AMDGPU::VGPR167, AMDGPU::VGPR168, AMDGPU::VGPR169, AMDGPU::VGPR170, AMDGPU::VGPR171, AMDGPU::VGPR172, AMDGPU::VGPR173, AMDGPU::VGPR174, AMDGPU::VGPR175, AMDGPU::VGPR176, AMDGPU::VGPR177, AMDGPU::VGPR178, AMDGPU::VGPR179, AMDGPU::VGPR180, AMDGPU::VGPR181, AMDGPU::VGPR182, AMDGPU::VGPR183, AMDGPU::VGPR184, AMDGPU::VGPR185, AMDGPU::VGPR186, AMDGPU::VGPR187, AMDGPU::VGPR188, AMDGPU::VGPR189, AMDGPU::VGPR190, AMDGPU::VGPR191, AMDGPU::VGPR192, AMDGPU::VGPR193, AMDGPU::VGPR194, AMDGPU::VGPR195, AMDGPU::VGPR196, AMDGPU::VGPR197, AMDGPU::VGPR198, AMDGPU::VGPR199, AMDGPU::VGPR200, AMDGPU::VGPR201, AMDGPU::VGPR202, AMDGPU::VGPR203, AMDGPU::VGPR204, AMDGPU::VGPR205, AMDGPU::VGPR206, AMDGPU::VGPR207, AMDGPU::VGPR208, AMDGPU::VGPR209, AMDGPU::VGPR210, AMDGPU::VGPR211, AMDGPU::VGPR212, AMDGPU::VGPR213, AMDGPU::VGPR214, AMDGPU::VGPR215, AMDGPU::VGPR216, AMDGPU::VGPR217, AMDGPU::VGPR218, AMDGPU::VGPR219, AMDGPU::VGPR220, AMDGPU::VGPR221, AMDGPU::VGPR222, AMDGPU::VGPR223, AMDGPU::VGPR224, AMDGPU::VGPR225, AMDGPU::VGPR226, AMDGPU::VGPR227, AMDGPU::VGPR228, AMDGPU::VGPR229, AMDGPU::VGPR230, AMDGPU::VGPR231, AMDGPU::VGPR232, AMDGPU::VGPR233, AMDGPU::VGPR234, AMDGPU::VGPR235, AMDGPU::VGPR236, AMDGPU::VGPR237, AMDGPU::VGPR238, AMDGPU::VGPR239, AMDGPU::VGPR240, AMDGPU::VGPR241, AMDGPU::VGPR242, AMDGPU::VGPR243, AMDGPU::VGPR244, AMDGPU::VGPR245, AMDGPU::VGPR246, AMDGPU::VGPR247, AMDGPU::VGPR248, AMDGPU::VGPR249, AMDGPU::VGPR250, AMDGPU::VGPR251, AMDGPU::VGPR252, AMDGPU::VGPR253, AMDGPU::VGPR254, AMDGPU::VGPR255, AMDGPU::SGPR32, AMDGPU::SGPR33, AMDGPU::SGPR34, AMDGPU::SGPR35, AMDGPU::SGPR36, AMDGPU::SGPR37, AMDGPU::SGPR38, AMDGPU::SGPR39, AMDGPU::SGPR40, AMDGPU::SGPR41, AMDGPU::SGPR42, AMDGPU::SGPR43, AMDGPU::SGPR44, AMDGPU::SGPR45, AMDGPU::SGPR46, AMDGPU::SGPR47, AMDGPU::SGPR48, AMDGPU::SGPR49, AMDGPU::SGPR50, AMDGPU::SGPR51, AMDGPU::SGPR52, AMDGPU::SGPR53, AMDGPU::SGPR54, AMDGPU::SGPR55, AMDGPU::SGPR56, AMDGPU::SGPR57, AMDGPU::SGPR58, AMDGPU::SGPR59, AMDGPU::SGPR60, AMDGPU::SGPR61, AMDGPU::SGPR62, AMDGPU::SGPR63, AMDGPU::SGPR64, AMDGPU::SGPR65, AMDGPU::SGPR66, AMDGPU::SGPR67, AMDGPU::SGPR68, AMDGPU::SGPR69, AMDGPU::SGPR70, AMDGPU::SGPR71, AMDGPU::SGPR72, AMDGPU::SGPR73, AMDGPU::SGPR74, AMDGPU::SGPR75, AMDGPU::SGPR76, AMDGPU::SGPR77, AMDGPU::SGPR78, AMDGPU::SGPR79, AMDGPU::SGPR80, AMDGPU::SGPR81, AMDGPU::SGPR82, AMDGPU::SGPR83, AMDGPU::SGPR84, AMDGPU::SGPR85, AMDGPU::SGPR86, AMDGPU::SGPR87, AMDGPU::SGPR88, AMDGPU::SGPR89, AMDGPU::SGPR90, AMDGPU::SGPR91, AMDGPU::SGPR92, AMDGPU::SGPR93, AMDGPU::SGPR94, AMDGPU::SGPR95, AMDGPU::SGPR96, AMDGPU::SGPR97, AMDGPU::SGPR98, AMDGPU::SGPR99, AMDGPU::SGPR100, AMDGPU::SGPR101, AMDGPU::SGPR102, AMDGPU::SGPR103, AMDGPU::SGPR104, AMDGPU::SGPR105, 0 };
48775 static const MCPhysReg CSR_AMDGPU_SGPRs_32_105_SaveList[] = { AMDGPU::SGPR32, AMDGPU::SGPR33, AMDGPU::SGPR34, AMDGPU::SGPR35, AMDGPU::SGPR36, AMDGPU::SGPR37, AMDGPU::SGPR38, AMDGPU::SGPR39, AMDGPU::SGPR40, AMDGPU::SGPR41, AMDGPU::SGPR42, AMDGPU::SGPR43, AMDGPU::SGPR44, AMDGPU::SGPR45, AMDGPU::SGPR46, AMDGPU::SGPR47, AMDGPU::SGPR48, AMDGPU::SGPR49, AMDGPU::SGPR50, AMDGPU::SGPR51, AMDGPU::SGPR52, AMDGPU::SGPR53, AMDGPU::SGPR54, AMDGPU::SGPR55, AMDGPU::SGPR56, AMDGPU::SGPR57, AMDGPU::SGPR58, AMDGPU::SGPR59, AMDGPU::SGPR60, AMDGPU::SGPR61, AMDGPU::SGPR62, AMDGPU::SGPR63, AMDGPU::SGPR64, AMDGPU::SGPR65, AMDGPU::SGPR66, AMDGPU::SGPR67, AMDGPU::SGPR68, AMDGPU::SGPR69, AMDGPU::SGPR70, AMDGPU::SGPR71, AMDGPU::SGPR72, AMDGPU::SGPR73, AMDGPU::SGPR74, AMDGPU::SGPR75, AMDGPU::SGPR76, AMDGPU::SGPR77, AMDGPU::SGPR78, AMDGPU::SGPR79, AMDGPU::SGPR80, AMDGPU::SGPR81, AMDGPU::SGPR82, AMDGPU::SGPR83, AMDGPU::SGPR84, AMDGPU::SGPR85, AMDGPU::SGPR86, AMDGPU::SGPR87, AMDGPU::SGPR88, AMDGPU::SGPR89, AMDGPU::SGPR90, AMDGPU::SGPR91, AMDGPU::SGPR92, AMDGPU::SGPR93, AMDGPU::SGPR94, AMDGPU::SGPR95, AMDGPU::SGPR96, AMDGPU::SGPR97, AMDGPU::SGPR98, AMDGPU::SGPR99, AMDGPU::SGPR100, AMDGPU::SGPR101, AMDGPU::SGPR102, AMDGPU::SGPR103, AMDGPU::SGPR104, AMDGPU::SGPR105, 0 };
48777 static const MCPhysReg CSR_AMDGPU_VGPRs_24_255_SaveList[] = { AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31, AMDGPU::VGPR32, AMDGPU::VGPR33, AMDGPU::VGPR34, AMDGPU::VGPR35, AMDGPU::VGPR36, AMDGPU::VGPR37, AMDGPU::VGPR38, AMDGPU::VGPR39, AMDGPU::VGPR40, AMDGPU::VGPR41, AMDGPU::VGPR42, AMDGPU::VGPR43, AMDGPU::VGPR44, AMDGPU::VGPR45, AMDGPU::VGPR46, AMDGPU::VGPR47, AMDGPU::VGPR48, AMDGPU::VGPR49, AMDGPU::VGPR50, AMDGPU::VGPR51, AMDGPU::VGPR52, AMDGPU::VGPR53, AMDGPU::VGPR54, AMDGPU::VGPR55, AMDGPU::VGPR56, AMDGPU::VGPR57, AMDGPU::VGPR58, AMDGPU::VGPR59, AMDGPU::VGPR60, AMDGPU::VGPR61, AMDGPU::VGPR62, AMDGPU::VGPR63, AMDGPU::VGPR64, AMDGPU::VGPR65, AMDGPU::VGPR66, AMDGPU::VGPR67, AMDGPU::VGPR68, AMDGPU::VGPR69, AMDGPU::VGPR70, AMDGPU::VGPR71, AMDGPU::VGPR72, AMDGPU::VGPR73, AMDGPU::VGPR74, AMDGPU::VGPR75, AMDGPU::VGPR76, AMDGPU::VGPR77, AMDGPU::VGPR78, AMDGPU::VGPR79, AMDGPU::VGPR80, AMDGPU::VGPR81, AMDGPU::VGPR82, AMDGPU::VGPR83, AMDGPU::VGPR84, AMDGPU::VGPR85, AMDGPU::VGPR86, AMDGPU::VGPR87, AMDGPU::VGPR88, AMDGPU::VGPR89, AMDGPU::VGPR90, AMDGPU::VGPR91, AMDGPU::VGPR92, AMDGPU::VGPR93, AMDGPU::VGPR94, AMDGPU::VGPR95, AMDGPU::VGPR96, AMDGPU::VGPR97, AMDGPU::VGPR98, AMDGPU::VGPR99, AMDGPU::VGPR100, AMDGPU::VGPR101, AMDGPU::VGPR102, AMDGPU::VGPR103, AMDGPU::VGPR104, AMDGPU::VGPR105, AMDGPU::VGPR106, AMDGPU::VGPR107, AMDGPU::VGPR108, AMDGPU::VGPR109, AMDGPU::VGPR110, AMDGPU::VGPR111, AMDGPU::VGPR112, AMDGPU::VGPR113, AMDGPU::VGPR114, AMDGPU::VGPR115, AMDGPU::VGPR116, AMDGPU::VGPR117, AMDGPU::VGPR118, AMDGPU::VGPR119, AMDGPU::VGPR120, AMDGPU::VGPR121, AMDGPU::VGPR122, AMDGPU::VGPR123, AMDGPU::VGPR124, AMDGPU::VGPR125, AMDGPU::VGPR126, AMDGPU::VGPR127, AMDGPU::VGPR128, AMDGPU::VGPR129, AMDGPU::VGPR130, AMDGPU::VGPR131, AMDGPU::VGPR132, AMDGPU::VGPR133, AMDGPU::VGPR134, AMDGPU::VGPR135, AMDGPU::VGPR136, AMDGPU::VGPR137, AMDGPU::VGPR138, AMDGPU::VGPR139, AMDGPU::VGPR140, AMDGPU::VGPR141, AMDGPU::VGPR142, AMDGPU::VGPR143, AMDGPU::VGPR144, AMDGPU::VGPR145, AMDGPU::VGPR146, AMDGPU::VGPR147, AMDGPU::VGPR148, AMDGPU::VGPR149, AMDGPU::VGPR150, AMDGPU::VGPR151, AMDGPU::VGPR152, AMDGPU::VGPR153, AMDGPU::VGPR154, AMDGPU::VGPR155, AMDGPU::VGPR156, AMDGPU::VGPR157, AMDGPU::VGPR158, AMDGPU::VGPR159, AMDGPU::VGPR160, AMDGPU::VGPR161, AMDGPU::VGPR162, AMDGPU::VGPR163, AMDGPU::VGPR164, AMDGPU::VGPR165, AMDGPU::VGPR166, AMDGPU::VGPR167, AMDGPU::VGPR168, AMDGPU::VGPR169, AMDGPU::VGPR170, AMDGPU::VGPR171, AMDGPU::VGPR172, AMDGPU::VGPR173, AMDGPU::VGPR174, AMDGPU::VGPR175, AMDGPU::VGPR176, AMDGPU::VGPR177, AMDGPU::VGPR178, AMDGPU::VGPR179, AMDGPU::VGPR180, AMDGPU::VGPR181, AMDGPU::VGPR182, AMDGPU::VGPR183, AMDGPU::VGPR184, AMDGPU::VGPR185, AMDGPU::VGPR186, AMDGPU::VGPR187, AMDGPU::VGPR188, AMDGPU::VGPR189, AMDGPU::VGPR190, AMDGPU::VGPR191, AMDGPU::VGPR192, AMDGPU::VGPR193, AMDGPU::VGPR194, AMDGPU::VGPR195, AMDGPU::VGPR196, AMDGPU::VGPR197, AMDGPU::VGPR198, AMDGPU::VGPR199, AMDGPU::VGPR200, AMDGPU::VGPR201, AMDGPU::VGPR202, AMDGPU::VGPR203, AMDGPU::VGPR204, AMDGPU::VGPR205, AMDGPU::VGPR206, AMDGPU::VGPR207, AMDGPU::VGPR208, AMDGPU::VGPR209, AMDGPU::VGPR210, AMDGPU::VGPR211, AMDGPU::VGPR212, AMDGPU::VGPR213, AMDGPU::VGPR214, AMDGPU::VGPR215, AMDGPU::VGPR216, AMDGPU::VGPR217, AMDGPU::VGPR218, AMDGPU::VGPR219, AMDGPU::VGPR220, AMDGPU::VGPR221, AMDGPU::VGPR222, AMDGPU::VGPR223, AMDGPU::VGPR224, AMDGPU::VGPR225, AMDGPU::VGPR226, AMDGPU::VGPR227, AMDGPU::VGPR228, AMDGPU::VGPR229, AMDGPU::VGPR230, AMDGPU::VGPR231, AMDGPU::VGPR232, AMDGPU::VGPR233, AMDGPU::VGPR234, AMDGPU::VGPR235, AMDGPU::VGPR236, AMDGPU::VGPR237, AMDGPU::VGPR238, AMDGPU::VGPR239, AMDGPU::VGPR240, AMDGPU::VGPR241, AMDGPU::VGPR242, AMDGPU::VGPR243, AMDGPU::VGPR244, AMDGPU::VGPR245, AMDGPU::VGPR246, AMDGPU::VGPR247, AMDGPU::VGPR248, AMDGPU::VGPR249, AMDGPU::VGPR250, AMDGPU::VGPR251, AMDGPU::VGPR252, AMDGPU::VGPR253, AMDGPU::VGPR254, AMDGPU::VGPR255, 0 };
48779 static const MCPhysReg CSR_AMDGPU_VGPRs_32_255_SaveList[] = { AMDGPU::VGPR32, AMDGPU::VGPR33, AMDGPU::VGPR34, AMDGPU::VGPR35, AMDGPU::VGPR36, AMDGPU::VGPR37, AMDGPU::VGPR38, AMDGPU::VGPR39, AMDGPU::VGPR40, AMDGPU::VGPR41, AMDGPU::VGPR42, AMDGPU::VGPR43, AMDGPU::VGPR44, AMDGPU::VGPR45, AMDGPU::VGPR46, AMDGPU::VGPR47, AMDGPU::VGPR48, AMDGPU::VGPR49, AMDGPU::VGPR50, AMDGPU::VGPR51, AMDGPU::VGPR52, AMDGPU::VGPR53, AMDGPU::VGPR54, AMDGPU::VGPR55, AMDGPU::VGPR56, AMDGPU::VGPR57, AMDGPU::VGPR58, AMDGPU::VGPR59, AMDGPU::VGPR60, AMDGPU::VGPR61, AMDGPU::VGPR62, AMDGPU::VGPR63, AMDGPU::VGPR64, AMDGPU::VGPR65, AMDGPU::VGPR66, AMDGPU::VGPR67, AMDGPU::VGPR68, AMDGPU::VGPR69, AMDGPU::VGPR70, AMDGPU::VGPR71, AMDGPU::VGPR72, AMDGPU::VGPR73, AMDGPU::VGPR74, AMDGPU::VGPR75, AMDGPU::VGPR76, AMDGPU::VGPR77, AMDGPU::VGPR78, AMDGPU::VGPR79, AMDGPU::VGPR80, AMDGPU::VGPR81, AMDGPU::VGPR82, AMDGPU::VGPR83, AMDGPU::VGPR84, AMDGPU::VGPR85, AMDGPU::VGPR86, AMDGPU::VGPR87, AMDGPU::VGPR88, AMDGPU::VGPR89, AMDGPU::VGPR90, AMDGPU::VGPR91, AMDGPU::VGPR92, AMDGPU::VGPR93, AMDGPU::VGPR94, AMDGPU::VGPR95, AMDGPU::VGPR96, AMDGPU::VGPR97, AMDGPU::VGPR98, AMDGPU::VGPR99, AMDGPU::VGPR100, AMDGPU::VGPR101, AMDGPU::VGPR102, AMDGPU::VGPR103, AMDGPU::VGPR104, AMDGPU::VGPR105, AMDGPU::VGPR106, AMDGPU::VGPR107, AMDGPU::VGPR108, AMDGPU::VGPR109, AMDGPU::VGPR110, AMDGPU::VGPR111, AMDGPU::VGPR112, AMDGPU::VGPR113, AMDGPU::VGPR114, AMDGPU::VGPR115, AMDGPU::VGPR116, AMDGPU::VGPR117, AMDGPU::VGPR118, AMDGPU::VGPR119, AMDGPU::VGPR120, AMDGPU::VGPR121, AMDGPU::VGPR122, AMDGPU::VGPR123, AMDGPU::VGPR124, AMDGPU::VGPR125, AMDGPU::VGPR126, AMDGPU::VGPR127, AMDGPU::VGPR128, AMDGPU::VGPR129, AMDGPU::VGPR130, AMDGPU::VGPR131, AMDGPU::VGPR132, AMDGPU::VGPR133, AMDGPU::VGPR134, AMDGPU::VGPR135, AMDGPU::VGPR136, AMDGPU::VGPR137, AMDGPU::VGPR138, AMDGPU::VGPR139, AMDGPU::VGPR140, AMDGPU::VGPR141, AMDGPU::VGPR142, AMDGPU::VGPR143, AMDGPU::VGPR144, AMDGPU::VGPR145, AMDGPU::VGPR146, AMDGPU::VGPR147, AMDGPU::VGPR148, AMDGPU::VGPR149, AMDGPU::VGPR150, AMDGPU::VGPR151, AMDGPU::VGPR152, AMDGPU::VGPR153, AMDGPU::VGPR154, AMDGPU::VGPR155, AMDGPU::VGPR156, AMDGPU::VGPR157, AMDGPU::VGPR158, AMDGPU::VGPR159, AMDGPU::VGPR160, AMDGPU::VGPR161, AMDGPU::VGPR162, AMDGPU::VGPR163, AMDGPU::VGPR164, AMDGPU::VGPR165, AMDGPU::VGPR166, AMDGPU::VGPR167, AMDGPU::VGPR168, AMDGPU::VGPR169, AMDGPU::VGPR170, AMDGPU::VGPR171, AMDGPU::VGPR172, AMDGPU::VGPR173, AMDGPU::VGPR174, AMDGPU::VGPR175, AMDGPU::VGPR176, AMDGPU::VGPR177, AMDGPU::VGPR178, AMDGPU::VGPR179, AMDGPU::VGPR180, AMDGPU::VGPR181, AMDGPU::VGPR182, AMDGPU::VGPR183, AMDGPU::VGPR184, AMDGPU::VGPR185, AMDGPU::VGPR186, AMDGPU::VGPR187, AMDGPU::VGPR188, AMDGPU::VGPR189, AMDGPU::VGPR190, AMDGPU::VGPR191, AMDGPU::VGPR192, AMDGPU::VGPR193, AMDGPU::VGPR194, AMDGPU::VGPR195, AMDGPU::VGPR196, AMDGPU::VGPR197, AMDGPU::VGPR198, AMDGPU::VGPR199, AMDGPU::VGPR200, AMDGPU::VGPR201, AMDGPU::VGPR202, AMDGPU::VGPR203, AMDGPU::VGPR204, AMDGPU::VGPR205, AMDGPU::VGPR206, AMDGPU::VGPR207, AMDGPU::VGPR208, AMDGPU::VGPR209, AMDGPU::VGPR210, AMDGPU::VGPR211, AMDGPU::VGPR212, AMDGPU::VGPR213, AMDGPU::VGPR214, AMDGPU::VGPR215, AMDGPU::VGPR216, AMDGPU::VGPR217, AMDGPU::VGPR218, AMDGPU::VGPR219, AMDGPU::VGPR220, AMDGPU::VGPR221, AMDGPU::VGPR222, AMDGPU::VGPR223, AMDGPU::VGPR224, AMDGPU::VGPR225, AMDGPU::VGPR226, AMDGPU::VGPR227, AMDGPU::VGPR228, AMDGPU::VGPR229, AMDGPU::VGPR230, AMDGPU::VGPR231, AMDGPU::VGPR232, AMDGPU::VGPR233, AMDGPU::VGPR234, AMDGPU::VGPR235, AMDGPU::VGPR236, AMDGPU::VGPR237, AMDGPU::VGPR238, AMDGPU::VGPR239, AMDGPU::VGPR240, AMDGPU::VGPR241, AMDGPU::VGPR242, AMDGPU::VGPR243, AMDGPU::VGPR244, AMDGPU::VGPR245, AMDGPU::VGPR246, AMDGPU::VGPR247, AMDGPU::VGPR248, AMDGPU::VGPR249, AMDGPU::VGPR250, AMDGPU::VGPR251, AMDGPU::VGPR252, AMDGPU::VGPR253, AMDGPU::VGPR254, AMDGPU::VGPR255, 0 };
gen/lib/Target/AMDGPU/R600GenCallingConv.inc 21 static const MCPhysReg RegList1[] = {
gen/lib/Target/AMDGPU/R600GenRegisterInfo.inc 1788 extern const MCPhysReg R600RegDiffLists[] = {
5289 extern const MCPhysReg R600RegUnitRoots[][2] = {
6636 const MCPhysReg R600_Reg32[] = {
6646 const MCPhysReg R600_TReg32[] = {
6656 const MCPhysReg R600_TReg32_X[] = {
6666 const MCPhysReg R600_Addr[] = {
6676 const MCPhysReg R600_KC0[] = {
6686 const MCPhysReg R600_KC1[] = {
6696 const MCPhysReg R600_TReg32_W[] = {
6706 const MCPhysReg R600_TReg32_Y[] = {
6716 const MCPhysReg R600_TReg32_Z[] = {
6726 const MCPhysReg R600_ArrayBase[] = {
6736 const MCPhysReg R600_KC0_W[] = {
6746 const MCPhysReg R600_KC0_X[] = {
6756 const MCPhysReg R600_KC0_Y[] = {
6766 const MCPhysReg R600_KC0_Z[] = {
6776 const MCPhysReg R600_KC1_W[] = {
6786 const MCPhysReg R600_KC1_X[] = {
6796 const MCPhysReg R600_KC1_Y[] = {
6806 const MCPhysReg R600_KC1_Z[] = {
6816 const MCPhysReg R600_LDS_SRC_REG[] = {
6826 const MCPhysReg R600_Predicate[] = {
6836 const MCPhysReg R600_Addr_W[] = {
6846 const MCPhysReg R600_Addr_Y[] = {
6856 const MCPhysReg R600_Addr_Z[] = {
6866 const MCPhysReg R600_LDS_SRC_REG_and_R600_Reg32[] = {
6876 const MCPhysReg R600_Predicate_Bit[] = {
6886 const MCPhysReg R600_Reg64[] = {
6896 const MCPhysReg R600_Reg64Vertical[] = {
6906 const MCPhysReg R600_Reg64Vertical_with_sub0_in_R600_TReg32_W[] = {
6916 const MCPhysReg R600_Reg64Vertical_with_sub0_in_R600_TReg32_X[] = {
6926 const MCPhysReg R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y[] = {
6936 const MCPhysReg R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z[] = {
6946 const MCPhysReg R600_Reg128[] = {
6956 const MCPhysReg R600_Reg128Vertical[] = {
6966 const MCPhysReg R600_Reg128Vertical_with_sub0_in_R600_TReg32_W[] = {
6976 const MCPhysReg R600_Reg128Vertical_with_sub0_in_R600_TReg32_X[] = {
6986 const MCPhysReg R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y[] = {
6996 const MCPhysReg R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z[] = {
12343 extern const MCPhysReg R600RegDiffLists[];
12347 extern const MCPhysReg R600RegUnitRoots[][2];
gen/lib/Target/ARC/ARCGenCallingConv.inc 34 static const MCPhysReg RegList1[] = {
65 static const MCPhysReg RegList1[] = {
gen/lib/Target/ARC/ARCGenInstrInfo.inc 582 static const MCPhysReg ImplicitList1[] = { ARC::SP, 0 };
583 static const MCPhysReg ImplicitList2[] = { ARC::STATUS32, 0 };
584 static const MCPhysReg ImplicitList3[] = { ARC::BLINK, 0 };
585 static const MCPhysReg ImplicitList4[] = { ARC::BLINK, ARC::SP, 0 };
gen/lib/Target/ARC/ARCGenRegisterInfo.inc 88 extern const MCPhysReg ARCRegDiffLists[] = {
177 extern const MCPhysReg ARCRegUnitRoots[][2] = {
215 const MCPhysReg SREG[] = {
225 const MCPhysReg GPR_S[] = {
235 const MCPhysReg GPR32[] = {
245 const MCPhysReg GPR32_and_GPR_S[] = {
775 extern const MCPhysReg ARCRegDiffLists[];
779 extern const MCPhysReg ARCRegUnitRoots[][2];
845 static const MCPhysReg CSR_ARC_SaveList[] = { ARC::R13, ARC::R14, ARC::R15, ARC::R16, ARC::R17, ARC::R18, ARC::R19, ARC::R20, ARC::R21, ARC::R22, ARC::R23, ARC::R24, ARC::R25, ARC::GP, ARC::FP, 0 };
gen/lib/Target/ARM/ARMGenCallingConv.inc 139 static const MCPhysReg RegList1[] = {
142 static const MCPhysReg RegList2[] = {
154 static const MCPhysReg RegList3[] = {
166 static const MCPhysReg ShadowRegList4[] = {
176 static const MCPhysReg ShadowRegList6[] = {
185 static const MCPhysReg ShadowRegList8[] = {
194 static const MCPhysReg ShadowRegList10[] = {
204 static const MCPhysReg ShadowRegList12[] = {
214 static const MCPhysReg ShadowRegList14[] = {
281 static const MCPhysReg RegList1[] = {
291 static const MCPhysReg RegList2[] = {
301 static const MCPhysReg RegList3[] = {
388 static const MCPhysReg RegList1[] = {
444 static const MCPhysReg RegList1[] = {
454 static const MCPhysReg RegList2[] = {
464 static const MCPhysReg RegList3[] = {
485 static const MCPhysReg RegList4[] = {
538 static const MCPhysReg RegList1[] = {
548 static const MCPhysReg RegList2[] = {
558 static const MCPhysReg RegList3[] = {
568 static const MCPhysReg ShadowRegList4[] = {
577 static const MCPhysReg ShadowRegList6[] = {
586 static const MCPhysReg ShadowRegList8[] = {
680 static const MCPhysReg RegList1[] = {
690 static const MCPhysReg RegList2[] = {
693 static const MCPhysReg RegList3[] = {
751 static const MCPhysReg RegList1[] = {
761 static const MCPhysReg RegList2[] = {
771 static const MCPhysReg RegList3[] = {
853 static const MCPhysReg RegList1[] = {
863 static const MCPhysReg RegList2[] = {
866 static const MCPhysReg RegList3[] = {
904 static const MCPhysReg RegList1[] = {
914 static const MCPhysReg RegList2[] = {
924 static const MCPhysReg RegList3[] = {
gen/lib/Target/ARM/ARMGenInstrInfo.inc 5296 static const MCPhysReg ImplicitList1[] = { ARM::CPSR, 0 };
5297 static const MCPhysReg ImplicitList2[] = { ARM::SP, 0 };
5298 static const MCPhysReg ImplicitList3[] = { ARM::LR, 0 };
5299 static const MCPhysReg ImplicitList4[] = { ARM::R7, ARM::LR, ARM::SP, 0 };
5300 static const MCPhysReg ImplicitList5[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 0 };
5301 static const MCPhysReg ImplicitList6[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, 0 };
5302 static const MCPhysReg ImplicitList7[] = { ARM::R0, ARM::R12, ARM::LR, ARM::CPSR, 0 };
5303 static const MCPhysReg ImplicitList8[] = { ARM::R4, 0 };
5304 static const MCPhysReg ImplicitList9[] = { ARM::R4, ARM::SP, 0 };
5305 static const MCPhysReg ImplicitList10[] = { ARM::PC, 0 };
5306 static const MCPhysReg ImplicitList11[] = { ARM::FPSCR_NZCV, 0 };
5307 static const MCPhysReg ImplicitList12[] = { ARM::VPR, 0 };
5308 static const MCPhysReg ImplicitList13[] = { ARM::FPSCR, 0 };
5309 static const MCPhysReg ImplicitList14[] = { ARM::ITSTATE, 0 };
5310 static const MCPhysReg ImplicitList15[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 0 };
5311 static const MCPhysReg ImplicitList16[] = { ARM::R11, ARM::LR, ARM::SP, 0 };
5312 static const MCPhysReg ImplicitList17[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::CPSR, 0 };
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 544 extern const MCPhysReg ARMRegDiffLists[] = {
1478 extern const MCPhysReg ARMRegUnitRoots[][2] = {
1566 const MCPhysReg HPR[] = {
1576 const MCPhysReg FPWithVPR[] = {
1586 const MCPhysReg SPR[] = {
1596 const MCPhysReg FPWithVPR_with_ssub_0[] = {
1606 const MCPhysReg GPR[] = {
1616 const MCPhysReg GPRwithAPSR[] = {
1626 const MCPhysReg GPRwithZR[] = {
1636 const MCPhysReg SPR_8[] = {
1646 const MCPhysReg GPRnopc[] = {
1656 const MCPhysReg GPRwithAPSRnosp[] = {
1666 const MCPhysReg GPRwithZRnosp[] = {
1676 const MCPhysReg rGPR[] = {
1686 const MCPhysReg tGPRwithpc[] = {
1696 const MCPhysReg FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8[] = {
1706 const MCPhysReg hGPR[] = {
1716 const MCPhysReg tGPR[] = {
1726 const MCPhysReg tGPREven[] = {
1736 const MCPhysReg GPRnopc_and_hGPR[] = {
1746 const MCPhysReg GPRwithAPSRnosp_and_hGPR[] = {
1756 const MCPhysReg tGPROdd[] = {
1766 const MCPhysReg tcGPR[] = {
1776 const MCPhysReg hGPR_and_tGPREven[] = {
1786 const MCPhysReg tGPR_and_tGPREven[] = {
1796 const MCPhysReg tGPR_and_tGPROdd[] = {
1806 const MCPhysReg tGPR_and_tcGPR[] = {
1816 const MCPhysReg tGPREven_and_tcGPR[] = {
1826 const MCPhysReg hGPR_and_tGPROdd[] = {
1836 const MCPhysReg tGPREven_and_tGPR_and_tcGPR[] = {
1846 const MCPhysReg tGPROdd_and_tcGPR[] = {
1856 const MCPhysReg CCR[] = {
1866 const MCPhysReg GPRlr[] = {
1876 const MCPhysReg GPRsp[] = {
1886 const MCPhysReg VCCR[] = {
1896 const MCPhysReg cl_FPSCR_NZCV[] = {
1906 const MCPhysReg hGPR_and_tGPRwithpc[] = {
1916 const MCPhysReg hGPR_and_tcGPR[] = {
1926 const MCPhysReg DPR[] = {
1936 const MCPhysReg DPR_VFP2[] = {
1946 const MCPhysReg DPR_8[] = {
1956 const MCPhysReg GPRPair[] = {
1966 const MCPhysReg GPRPairnosp[] = {
1976 const MCPhysReg GPRPair_with_gsub_0_in_tGPR[] = {
1986 const MCPhysReg GPRPair_with_gsub_0_in_hGPR[] = {
1996 const MCPhysReg GPRPair_with_gsub_0_in_tcGPR[] = {
2006 const MCPhysReg GPRPair_with_gsub_1_in_tcGPR[] = {
2016 const MCPhysReg GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR[] = {
2026 const MCPhysReg GPRPair_with_gsub_1_in_GPRsp[] = {
2036 const MCPhysReg DPairSpc[] = {
2046 const MCPhysReg DPairSpc_with_ssub_0[] = {
2056 const MCPhysReg DPairSpc_with_ssub_4[] = {
2066 const MCPhysReg DPairSpc_with_dsub_0_in_DPR_8[] = {
2076 const MCPhysReg DPairSpc_with_dsub_2_in_DPR_8[] = {
2086 const MCPhysReg DPair[] = {
2096 const MCPhysReg DPair_with_ssub_0[] = {
2106 const MCPhysReg QPR[] = {
2116 const MCPhysReg DPair_with_ssub_2[] = {
2126 const MCPhysReg DPair_with_dsub_0_in_DPR_8[] = {
2136 const MCPhysReg MQPR[] = {
2146 const MCPhysReg QPR_VFP2[] = {
2156 const MCPhysReg DPair_with_dsub_1_in_DPR_8[] = {
2166 const MCPhysReg QPR_8[] = {
2176 const MCPhysReg DTriple[] = {
2186 const MCPhysReg DTripleSpc[] = {
2196 const MCPhysReg DTripleSpc_with_ssub_0[] = {
2206 const MCPhysReg DTriple_with_ssub_0[] = {
2216 const MCPhysReg DTriple_with_qsub_0_in_QPR[] = {
2226 const MCPhysReg DTriple_with_ssub_2[] = {
2236 const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2246 const MCPhysReg DTripleSpc_with_ssub_4[] = {
2256 const MCPhysReg DTriple_with_ssub_4[] = {
2266 const MCPhysReg DTripleSpc_with_ssub_8[] = {
2276 const MCPhysReg DTripleSpc_with_dsub_0_in_DPR_8[] = {
2286 const MCPhysReg DTriple_with_dsub_0_in_DPR_8[] = {
2296 const MCPhysReg DTriple_with_qsub_0_in_MQPR[] = {
2306 const MCPhysReg DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2316 const MCPhysReg DTriple_with_dsub_1_in_DPR_8[] = {
2326 const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
2336 const MCPhysReg DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR[] = {
2346 const MCPhysReg DTripleSpc_with_dsub_2_in_DPR_8[] = {
2356 const MCPhysReg DTriple_with_dsub_2_in_DPR_8[] = {
2366 const MCPhysReg DTripleSpc_with_dsub_4_in_DPR_8[] = {
2376 const MCPhysReg DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
2386 const MCPhysReg DTriple_with_qsub_0_in_QPR_8[] = {
2396 const MCPhysReg DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR[] = {
2406 const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
2416 const MCPhysReg DQuadSpc[] = {
2426 const MCPhysReg DQuadSpc_with_ssub_0[] = {
2436 const MCPhysReg DQuadSpc_with_ssub_4[] = {
2446 const MCPhysReg DQuadSpc_with_ssub_8[] = {
2456 const MCPhysReg DQuadSpc_with_dsub_0_in_DPR_8[] = {
2466 const MCPhysReg DQuadSpc_with_dsub_2_in_DPR_8[] = {
2476 const MCPhysReg DQuadSpc_with_dsub_4_in_DPR_8[] = {
2486 const MCPhysReg DQuad[] = {
2496 const MCPhysReg DQuad_with_ssub_0[] = {
2506 const MCPhysReg DQuad_with_ssub_2[] = {
2516 const MCPhysReg QQPR[] = {
2526 const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2536 const MCPhysReg DQuad_with_ssub_4[] = {
2546 const MCPhysReg DQuad_with_ssub_6[] = {
2556 const MCPhysReg DQuad_with_dsub_0_in_DPR_8[] = {
2566 const MCPhysReg DQuad_with_qsub_0_in_MQPR[] = {
2576 const MCPhysReg DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2586 const MCPhysReg DQuad_with_dsub_1_in_DPR_8[] = {
2596 const MCPhysReg DQuad_with_qsub_1_in_MQPR[] = {
2606 const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
2616 const MCPhysReg DQuad_with_dsub_2_in_DPR_8[] = {
2626 const MCPhysReg DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
2636 const MCPhysReg DQuad_with_dsub_3_in_DPR_8[] = {
2646 const MCPhysReg DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
2656 const MCPhysReg DQuad_with_qsub_0_in_QPR_8[] = {
2666 const MCPhysReg DQuad_with_qsub_1_in_QPR_8[] = {
2676 const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
2686 const MCPhysReg DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
2696 const MCPhysReg QQQQPR[] = {
2706 const MCPhysReg QQQQPR_with_ssub_0[] = {
2716 const MCPhysReg QQQQPR_with_ssub_4[] = {
2726 const MCPhysReg QQQQPR_with_ssub_8[] = {
2736 const MCPhysReg QQQQPR_with_ssub_12[] = {
2746 const MCPhysReg QQQQPR_with_dsub_0_in_DPR_8[] = {
2756 const MCPhysReg QQQQPR_with_dsub_2_in_DPR_8[] = {
2766 const MCPhysReg QQQQPR_with_dsub_4_in_DPR_8[] = {
2776 const MCPhysReg QQQQPR_with_dsub_6_in_DPR_8[] = {
5902 static ArrayRef<MCPhysReg> HPRGetRawAllocationOrder(const MachineFunction &MF) {
5903 static const MCPhysReg AltOrder1[] = { ARM::S0, ARM::S2, ARM::S4, ARM::S6, ARM::S8, ARM::S10, ARM::S12, ARM::S14, ARM::S16, ARM::S18, ARM::S20, ARM::S22, ARM::S24, ARM::S26, ARM::S28, ARM::S30, ARM::S1, ARM::S3, ARM::S5, ARM::S7, ARM::S9, ARM::S11, ARM::S13, ARM::S15, ARM::S17, ARM::S19, ARM::S21, ARM::S23, ARM::S25, ARM::S27, ARM::S29, ARM::S31 };
5904 static const MCPhysReg AltOrder2[] = { ARM::S0, ARM::S4, ARM::S8, ARM::S12, ARM::S16, ARM::S20, ARM::S24, ARM::S28, ARM::S2, ARM::S6, ARM::S10, ARM::S14, ARM::S18, ARM::S22, ARM::S26, ARM::S30, ARM::S1, ARM::S5, ARM::S9, ARM::S13, ARM::S17, ARM::S21, ARM::S25, ARM::S29, ARM::S3, ARM::S7, ARM::S11, ARM::S15, ARM::S19, ARM::S23, ARM::S27, ARM::S31 };
5906 const ArrayRef<MCPhysReg> Order[] = {
5920 static ArrayRef<MCPhysReg> SPRGetRawAllocationOrder(const MachineFunction &MF) {
5921 static const MCPhysReg AltOrder1[] = { ARM::S0, ARM::S2, ARM::S4, ARM::S6, ARM::S8, ARM::S10, ARM::S12, ARM::S14, ARM::S16, ARM::S18, ARM::S20, ARM::S22, ARM::S24, ARM::S26, ARM::S28, ARM::S30, ARM::S1, ARM::S3, ARM::S5, ARM::S7, ARM::S9, ARM::S11, ARM::S13, ARM::S15, ARM::S17, ARM::S19, ARM::S21, ARM::S23, ARM::S25, ARM::S27, ARM::S29, ARM::S31 };
5922 static const MCPhysReg AltOrder2[] = { ARM::S0, ARM::S4, ARM::S8, ARM::S12, ARM::S16, ARM::S20, ARM::S24, ARM::S28, ARM::S2, ARM::S6, ARM::S10, ARM::S14, ARM::S18, ARM::S22, ARM::S26, ARM::S30, ARM::S1, ARM::S5, ARM::S9, ARM::S13, ARM::S17, ARM::S21, ARM::S25, ARM::S29, ARM::S3, ARM::S7, ARM::S11, ARM::S15, ARM::S19, ARM::S23, ARM::S27, ARM::S31 };
5924 const ArrayRef<MCPhysReg> Order[] = {
5938 static ArrayRef<MCPhysReg> GPRGetRawAllocationOrder(const MachineFunction &MF) {
5939 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::PC };
5940 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
5941 static const MCPhysReg AltOrder3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::LR, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP, ARM::PC };
5943 const ArrayRef<MCPhysReg> Order[] = {
5958 static ArrayRef<MCPhysReg> GPRwithAPSRGetRawAllocationOrder(const MachineFunction &MF) {
5959 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP };
5960 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
5962 const ArrayRef<MCPhysReg> Order[] = {
5976 static ArrayRef<MCPhysReg> GPRwithZRGetRawAllocationOrder(const MachineFunction &MF) {
5977 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::ZR };
5978 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
5980 const ArrayRef<MCPhysReg> Order[] = {
5994 static ArrayRef<MCPhysReg> GPRnopcGetRawAllocationOrder(const MachineFunction &MF) {
5995 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP };
5996 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
5997 static const MCPhysReg AltOrder3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::LR, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP };
5999 const ArrayRef<MCPhysReg> Order[] = {
6014 static ArrayRef<MCPhysReg> GPRwithZRnospGetRawAllocationOrder(const MachineFunction &MF) {
6015 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::ZR };
6016 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
6018 const ArrayRef<MCPhysReg> Order[] = {
6032 static ArrayRef<MCPhysReg> rGPRGetRawAllocationOrder(const MachineFunction &MF) {
6033 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12 };
6034 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
6035 static const MCPhysReg AltOrder3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::LR, ARM::R8, ARM::R9, ARM::R10, ARM::R11 };
6037 const ArrayRef<MCPhysReg> Order[] = {
6052 static ArrayRef<MCPhysReg> tGPREvenGetRawAllocationOrder(const MachineFunction &MF) {
6053 static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R2, ARM::R4, ARM::R6 };
6055 const ArrayRef<MCPhysReg> Order[] = {
6068 static ArrayRef<MCPhysReg> tGPROddGetRawAllocationOrder(const MachineFunction &MF) {
6069 static const MCPhysReg AltOrder1[] = { ARM::R1, ARM::R3, ARM::R5, ARM::R7 };
6071 const ArrayRef<MCPhysReg> Order[] = {
6084 static ArrayRef<MCPhysReg> tcGPRGetRawAllocationOrder(const MachineFunction &MF) {
6085 static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
6087 const ArrayRef<MCPhysReg> Order[] = {
6100 static ArrayRef<MCPhysReg> tGPR_and_tGPREvenGetRawAllocationOrder(const MachineFunction &MF) {
6101 static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R2, ARM::R4, ARM::R6 };
6103 const ArrayRef<MCPhysReg> Order[] = {
6116 static ArrayRef<MCPhysReg> tGPR_and_tGPROddGetRawAllocationOrder(const MachineFunction &MF) {
6117 static const MCPhysReg AltOrder1[] = { ARM::R1, ARM::R3, ARM::R5, ARM::R7 };
6119 const ArrayRef<MCPhysReg> Order[] = {
6132 static ArrayRef<MCPhysReg> tGPR_and_tcGPRGetRawAllocationOrder(const MachineFunction &MF) {
6133 static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
6135 const ArrayRef<MCPhysReg> Order[] = {
6148 static ArrayRef<MCPhysReg> tGPREven_and_tcGPRGetRawAllocationOrder(const MachineFunction &MF) {
6149 static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R2 };
6151 const ArrayRef<MCPhysReg> Order[] = {
6164 static ArrayRef<MCPhysReg> hGPR_and_tGPROddGetRawAllocationOrder(const MachineFunction &MF) {
6166 const ArrayRef<MCPhysReg> Order[] = {
6179 static ArrayRef<MCPhysReg> tGPREven_and_tGPR_and_tcGPRGetRawAllocationOrder(const MachineFunction &MF) {
6180 static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R2 };
6182 const ArrayRef<MCPhysReg> Order[] = {
6195 static ArrayRef<MCPhysReg> tGPROdd_and_tcGPRGetRawAllocationOrder(const MachineFunction &MF) {
6196 static const MCPhysReg AltOrder1[] = { ARM::R1, ARM::R3 };
6198 const ArrayRef<MCPhysReg> Order[] = {
6211 static ArrayRef<MCPhysReg> hGPR_and_tcGPRGetRawAllocationOrder(const MachineFunction &MF) {
6213 const ArrayRef<MCPhysReg> Order[] = {
6226 static ArrayRef<MCPhysReg> DPRGetRawAllocationOrder(const MachineFunction &MF) {
6227 static const MCPhysReg AltOrder1[] = { ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15 };
6228 static const MCPhysReg AltOrder2[] = { ARM::D16, ARM::D18, ARM::D20, ARM::D22, ARM::D24, ARM::D26, ARM::D28, ARM::D30, ARM::D0, ARM::D2, ARM::D4, ARM::D6, ARM::D8, ARM::D10, ARM::D12, ARM::D14, ARM::D17, ARM::D19, ARM::D21, ARM::D23, ARM::D25, ARM::D27, ARM::D29, ARM::D31, ARM::D1, ARM::D3, ARM::D5, ARM::D7, ARM::D9, ARM::D11, ARM::D13, ARM::D15 };
6230 const ArrayRef<MCPhysReg> Order[] = {
6244 static ArrayRef<MCPhysReg> DPairGetRawAllocationOrder(const MachineFunction &MF) {
6245 static const MCPhysReg AltOrder1[] = { ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D17_D18, ARM::D19_D20, ARM::D21_D22, ARM::D23_D24, ARM::D25_D26, ARM::D27_D28, ARM::D29_D30, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14, ARM::D15_D16 };
6246 static const MCPhysReg AltOrder2[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14, ARM::D15_D16 };
6248 const ArrayRef<MCPhysReg> Order[] = {
6262 static ArrayRef<MCPhysReg> DPair_with_ssub_0GetRawAllocationOrder(const MachineFunction &MF) {
6263 static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14, ARM::D15_D16 };
6264 static const MCPhysReg AltOrder2[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14, ARM::D15_D16 };
6266 const ArrayRef<MCPhysReg> Order[] = {
6280 static ArrayRef<MCPhysReg> QPRGetRawAllocationOrder(const MachineFunction &MF) {
6281 static const MCPhysReg AltOrder1[] = { ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7 };
6282 static const MCPhysReg AltOrder2[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7 };
6284 const ArrayRef<MCPhysReg> Order[] = {
6298 static ArrayRef<MCPhysReg> DPair_with_ssub_2GetRawAllocationOrder(const MachineFunction &MF) {
6299 static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14 };
6300 static const MCPhysReg AltOrder2[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14 };
6302 const ArrayRef<MCPhysReg> Order[] = {
6316 static ArrayRef<MCPhysReg> DPair_with_dsub_0_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
6317 static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8 };
6318 static const MCPhysReg AltOrder2[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8 };
6320 const ArrayRef<MCPhysReg> Order[] = {
6334 static ArrayRef<MCPhysReg> DPair_with_dsub_1_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
6335 static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6 };
6336 static const MCPhysReg AltOrder2[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6 };
6338 const ArrayRef<MCPhysReg> Order[] = {
6350 static ArrayRef<MCPhysReg> QQPRGetRawAllocationOrder(const MachineFunction &MF) {
6351 static const MCPhysReg AltOrder1[] = { ARM::Q8_Q9, ARM::Q9_Q10, ARM::Q10_Q11, ARM::Q11_Q12, ARM::Q12_Q13, ARM::Q13_Q14, ARM::Q14_Q15, ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8 };
6353 const ArrayRef<MCPhysReg> Order[] = {
6364 static ArrayRef<MCPhysReg> DQuad_with_qsub_0_in_MQPRGetRawAllocationOrder(const MachineFunction &MF) {
6365 static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8 };
6367 const ArrayRef<MCPhysReg> Order[] = {
6378 static ArrayRef<MCPhysReg> DQuad_with_qsub_1_in_MQPRGetRawAllocationOrder(const MachineFunction &MF) {
6379 static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 };
6381 const ArrayRef<MCPhysReg> Order[] = {
6392 static ArrayRef<MCPhysReg> DQuad_with_qsub_0_in_QPR_8GetRawAllocationOrder(const MachineFunction &MF) {
6393 static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4 };
6395 const ArrayRef<MCPhysReg> Order[] = {
6406 static ArrayRef<MCPhysReg> DQuad_with_qsub_1_in_QPR_8GetRawAllocationOrder(const MachineFunction &MF) {
6407 static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3 };
6409 const ArrayRef<MCPhysReg> Order[] = {
6420 static ArrayRef<MCPhysReg> QQQQPRGetRawAllocationOrder(const MachineFunction &MF) {
6421 static const MCPhysReg AltOrder1[] = { ARM::Q8_Q9_Q10_Q11, ARM::Q9_Q10_Q11_Q12, ARM::Q10_Q11_Q12_Q13, ARM::Q11_Q12_Q13_Q14, ARM::Q12_Q13_Q14_Q15, ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10 };
6423 const ArrayRef<MCPhysReg> Order[] = {
6434 static ArrayRef<MCPhysReg> QQQQPR_with_ssub_0GetRawAllocationOrder(const MachineFunction &MF) {
6435 static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10 };
6437 const ArrayRef<MCPhysReg> Order[] = {
6448 static ArrayRef<MCPhysReg> QQQQPR_with_ssub_4GetRawAllocationOrder(const MachineFunction &MF) {
6449 static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9 };
6451 const ArrayRef<MCPhysReg> Order[] = {
6462 static ArrayRef<MCPhysReg> QQQQPR_with_ssub_8GetRawAllocationOrder(const MachineFunction &MF) {
6463 static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8 };
6465 const ArrayRef<MCPhysReg> Order[] = {
6476 static ArrayRef<MCPhysReg> QQQQPR_with_ssub_12GetRawAllocationOrder(const MachineFunction &MF) {
6477 static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 };
6479 const ArrayRef<MCPhysReg> Order[] = {
6490 static ArrayRef<MCPhysReg> QQQQPR_with_dsub_0_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
6491 static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6 };
6493 const ArrayRef<MCPhysReg> Order[] = {
6504 static ArrayRef<MCPhysReg> QQQQPR_with_dsub_2_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
6505 static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5 };
6507 const ArrayRef<MCPhysReg> Order[] = {
6518 static ArrayRef<MCPhysReg> QQQQPR_with_dsub_4_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
6519 static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4 };
6521 const ArrayRef<MCPhysReg> Order[] = {
6532 static ArrayRef<MCPhysReg> QQQQPR_with_dsub_6_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
6533 static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3 };
6535 const ArrayRef<MCPhysReg> Order[] = {
15933 extern const MCPhysReg ARMRegDiffLists[];
15937 extern const MCPhysReg ARMRegUnitRoots[][2];
16003 static const MCPhysReg CSR_AAPCS_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
16005 static const MCPhysReg CSR_AAPCS_SplitPush_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
16007 static const MCPhysReg CSR_AAPCS_SplitPush_SwiftError_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R9, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
16009 static const MCPhysReg CSR_AAPCS_SwiftError_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
16011 static const MCPhysReg CSR_AAPCS_ThisReturn_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R0, 0 };
16013 static const MCPhysReg CSR_FIQ_SaveList[] = { ARM::LR, ARM::R11, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::R0, 0 };
16015 static const MCPhysReg CSR_FPRegs_SaveList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, 0 };
16017 static const MCPhysReg CSR_GenericInt_SaveList[] = { ARM::LR, ARM::R12, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::R0, 0 };
16019 static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
16021 static const MCPhysReg CSR_Win_AAPCS_CFGuard_Check_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 };
16023 static const MCPhysReg CSR_iOS_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
16025 static const MCPhysReg CSR_iOS_CXX_TLS_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R12, ARM::R9, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 };
16027 static const MCPhysReg CSR_iOS_CXX_TLS_PE_SaveList[] = { ARM::LR, ARM::R12, ARM::R11, ARM::R7, ARM::R5, ARM::R4, 0 };
16029 static const MCPhysReg CSR_iOS_CXX_TLS_ViaCopy_SaveList[] = { ARM::R6, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R9, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 };
16031 static const MCPhysReg CSR_iOS_SwiftError_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
16033 static const MCPhysReg CSR_iOS_TLSCall_SaveList[] = { ARM::LR, ARM::SP, ARM::R11, ARM::R10, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 };
16035 static const MCPhysReg CSR_iOS_ThisReturn_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R0, 0 };
gen/lib/Target/AVR/AVRGenCallingConv.inc 28 static const MCPhysReg RegList1[] = {
38 static const MCPhysReg RegList2[] = {
75 static const MCPhysReg RegList1[] = {
93 static const MCPhysReg RegList1[] = {
103 static const MCPhysReg RegList2[] = {
gen/lib/Target/AVR/AVRGenInstrInfo.inc 383 static const MCPhysReg ImplicitList1[] = { AVR::SREG, 0 };
384 static const MCPhysReg ImplicitList2[] = { AVR::SP, 0 };
385 static const MCPhysReg ImplicitList3[] = { AVR::SP, AVR::SREG, 0 };
386 static const MCPhysReg ImplicitList4[] = { AVR::R31R30, 0 };
387 static const MCPhysReg ImplicitList5[] = { AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R1, AVR::R0, 0 };
388 static const MCPhysReg ImplicitList6[] = { AVR::SP, AVR::R31R30, 0 };
389 static const MCPhysReg ImplicitList7[] = { AVR::R0, 0 };
390 static const MCPhysReg ImplicitList8[] = { AVR::R1, AVR::R0, AVR::SREG, 0 };
391 static const MCPhysReg ImplicitList9[] = { AVR::R31R30, AVR::R1, AVR::R0, 0 };
392 static const MCPhysReg ImplicitList10[] = { AVR::R1, AVR::R0, 0 };
gen/lib/Target/AVR/AVRGenRegisterInfo.inc 144 extern const MCPhysReg AVRRegDiffLists[] = {
295 extern const MCPhysReg AVRRegUnitRoots[][2] = {
335 const MCPhysReg GPR8[] = {
345 const MCPhysReg GPR8lo[] = {
355 const MCPhysReg LD8[] = {
365 const MCPhysReg LD8lo[] = {
375 const MCPhysReg CCR[] = {
385 const MCPhysReg DREGS[] = {
395 const MCPhysReg DREGS_WITHOUT_YZ_WORKAROUND[] = {
405 const MCPhysReg DLDREGS[] = {
415 const MCPhysReg DREGS_with_sub_hi_in_GPR8lo[] = {
425 const MCPhysReg DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUND[] = {
435 const MCPhysReg DLDREGS_with_sub_hi_in_LD8lo[] = {
445 const MCPhysReg IWREGS[] = {
455 const MCPhysReg PTRREGS[] = {
465 const MCPhysReg DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGS[] = {
475 const MCPhysReg PTRDISPREGS[] = {
485 const MCPhysReg DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGS[] = {
495 const MCPhysReg GPRSP[] = {
505 const MCPhysReg ZREG[] = {
1675 extern const MCPhysReg AVRRegDiffLists[];
1679 extern const MCPhysReg AVRRegUnitRoots[][2];
1745 static const MCPhysReg CSR_Interrupts_SaveList[] = { AVR::R31, AVR::R30, AVR::R29, AVR::R28, AVR::R27, AVR::R26, AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20, AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R1, AVR::R0, 0 };
1747 static const MCPhysReg CSR_Normal_SaveList[] = { AVR::R29, AVR::R28, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, 0 };
gen/lib/Target/BPF/BPFGenCallingConv.inc 28 static const MCPhysReg RegList1[] = {
31 static const MCPhysReg RegList2[] = {
41 static const MCPhysReg RegList3[] = {
44 static const MCPhysReg RegList4[] = {
78 static const MCPhysReg RegList1[] = {
gen/lib/Target/BPF/BPFGenInstrInfo.inc 350 static const MCPhysReg ImplicitList1[] = { BPF::R11, 0 };
351 static const MCPhysReg ImplicitList2[] = { BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5, 0 };
352 static const MCPhysReg ImplicitList3[] = { BPF::R6, 0 };
gen/lib/Target/BPF/BPFGenRegisterInfo.inc 88 extern const MCPhysReg BPFRegDiffLists[] = {
164 extern const MCPhysReg BPFRegUnitRoots[][2] = {
181 const MCPhysReg GPR32[] = {
191 const MCPhysReg GPR[] = {
661 extern const MCPhysReg BPFRegDiffLists[];
665 extern const MCPhysReg BPFRegUnitRoots[][2];
731 static const MCPhysReg CSR_SaveList[] = { BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, 0 };
gen/lib/Target/Hexagon/HexagonGenCallingConv.inc 72 static const MCPhysReg RegList1[] = {
93 static const MCPhysReg RegList2[] = {
142 static const MCPhysReg RegList1[] = {
156 static const MCPhysReg RegList2[] = {
190 static const MCPhysReg RegList5[] = {
204 static const MCPhysReg RegList6[] = {
268 static const MCPhysReg RegList1[] = {
280 static const MCPhysReg RegList2[] = {
gen/lib/Target/Hexagon/HexagonGenInstrInfo.inc 3289 static const MCPhysReg ImplicitList1[] = { Hexagon::R31, Hexagon::R30, Hexagon::R29, 0 };
3290 static const MCPhysReg ImplicitList2[] = { Hexagon::R29, Hexagon::R30, 0 };
3291 static const MCPhysReg ImplicitList3[] = { Hexagon::R29, 0 };
3292 static const MCPhysReg ImplicitList4[] = { Hexagon::R29, Hexagon::R30, Hexagon::R31, 0 };
3293 static const MCPhysReg ImplicitList5[] = { Hexagon::SA0, Hexagon::LC0, 0 };
3294 static const MCPhysReg ImplicitList6[] = { Hexagon::PC, Hexagon::LC0, 0 };
3295 static const MCPhysReg ImplicitList7[] = { Hexagon::SA0, Hexagon::SA1, Hexagon::LC0, Hexagon::LC1, 0 };
3296 static const MCPhysReg ImplicitList8[] = { Hexagon::PC, Hexagon::LC0, Hexagon::LC1, 0 };
3297 static const MCPhysReg ImplicitList9[] = { Hexagon::SA1, Hexagon::LC1, 0 };
3298 static const MCPhysReg ImplicitList10[] = { Hexagon::PC, Hexagon::LC1, 0 };
3299 static const MCPhysReg ImplicitList11[] = { Hexagon::LC0, Hexagon::SA0, 0 };
3300 static const MCPhysReg ImplicitList12[] = { Hexagon::LC0, Hexagon::P3, Hexagon::PC, Hexagon::USR, 0 };
3301 static const MCPhysReg ImplicitList13[] = { Hexagon::LC0, Hexagon::LC1, Hexagon::SA0, Hexagon::SA1, 0 };
3302 static const MCPhysReg ImplicitList14[] = { Hexagon::LC0, Hexagon::LC1, Hexagon::P3, Hexagon::PC, Hexagon::USR, 0 };
3303 static const MCPhysReg ImplicitList15[] = { Hexagon::LC1, Hexagon::SA1, 0 };
3304 static const MCPhysReg ImplicitList16[] = { Hexagon::LC1, Hexagon::PC, 0 };
3305 static const MCPhysReg ImplicitList17[] = { Hexagon::R30, 0 };
3306 static const MCPhysReg ImplicitList18[] = { Hexagon::CS, 0 };
3307 static const MCPhysReg ImplicitList19[] = { Hexagon::PC, 0 };
3308 static const MCPhysReg ImplicitList20[] = { Hexagon::USR_OVF, 0 };
3309 static const MCPhysReg ImplicitList21[] = { Hexagon::R16, 0 };
3310 static const MCPhysReg ImplicitList22[] = { Hexagon::R28, 0 };
3311 static const MCPhysReg ImplicitList23[] = { Hexagon::USR, 0 };
3312 static const MCPhysReg ImplicitList24[] = { Hexagon::PC, Hexagon::R31, 0 };
3313 static const MCPhysReg ImplicitList25[] = { Hexagon::LC0, Hexagon::SA0, Hexagon::USR, 0 };
3314 static const MCPhysReg ImplicitList26[] = { Hexagon::SA0, Hexagon::LC0, Hexagon::USR, 0 };
3315 static const MCPhysReg ImplicitList27[] = { Hexagon::LC0, Hexagon::P3, Hexagon::SA0, Hexagon::USR, 0 };
3316 static const MCPhysReg ImplicitList28[] = { Hexagon::GOSP, 0 };
3317 static const MCPhysReg ImplicitList29[] = { Hexagon::GOSP, Hexagon::PC, 0 };
3318 static const MCPhysReg ImplicitList30[] = { Hexagon::P0, 0 };
3319 static const MCPhysReg ImplicitList31[] = { Hexagon::P0, Hexagon::PC, 0 };
3320 static const MCPhysReg ImplicitList32[] = { Hexagon::P1, 0 };
3321 static const MCPhysReg ImplicitList33[] = { Hexagon::P1, Hexagon::PC, 0 };
3322 static const MCPhysReg ImplicitList34[] = { Hexagon::FRAMEKEY, 0 };
3323 static const MCPhysReg ImplicitList35[] = { Hexagon::GP, 0 };
3324 static const MCPhysReg ImplicitList36[] = { Hexagon::PC, Hexagon::R29, 0 };
3325 static const MCPhysReg ImplicitList37[] = { Hexagon::PC, Hexagon::R31, Hexagon::R6, Hexagon::R7, Hexagon::P0, 0 };
3326 static const MCPhysReg ImplicitList38[] = { Hexagon::R29, Hexagon::R30, Hexagon::R31, Hexagon::PC, 0 };
3327 static const MCPhysReg ImplicitList39[] = { Hexagon::R14, Hexagon::R15, Hexagon::R28, Hexagon::R29, Hexagon::R30, Hexagon::R31, Hexagon::PC, 0 };
3328 static const MCPhysReg ImplicitList40[] = { Hexagon::FRAMEKEY, Hexagon::FRAMELIMIT, Hexagon::R30, Hexagon::R31, 0 };
3329 static const MCPhysReg ImplicitList41[] = { Hexagon::R29, Hexagon::R31, 0 };
3330 static const MCPhysReg ImplicitList42[] = { Hexagon::R14, Hexagon::R15, Hexagon::R28, Hexagon::P0, 0 };
3331 static const MCPhysReg ImplicitList43[] = { Hexagon::R14, Hexagon::R15, Hexagon::R28, 0 };
3332 static const MCPhysReg ImplicitList44[] = { Hexagon::FRAMEKEY, Hexagon::R30, 0 };
3333 static const MCPhysReg ImplicitList45[] = { Hexagon::R30, Hexagon::R29, Hexagon::R31, 0 };
3334 static const MCPhysReg ImplicitList46[] = { Hexagon::R31, 0 };
3335 static const MCPhysReg ImplicitList47[] = { Hexagon::P0, Hexagon::R31, 0 };
3336 static const MCPhysReg ImplicitList48[] = { Hexagon::PC, Hexagon::R30, Hexagon::R29, Hexagon::R31, 0 };
3337 static const MCPhysReg ImplicitList49[] = { Hexagon::FRAMEKEY, Hexagon::P0, Hexagon::R30, 0 };
3338 static const MCPhysReg ImplicitList50[] = { Hexagon::FRAMEKEY, Hexagon::FRAMELIMIT, Hexagon::R30, Hexagon::R29, Hexagon::R31, 0 };
3339 static const MCPhysReg ImplicitList51[] = { Hexagon::R30, Hexagon::R29, 0 };
3340 static const MCPhysReg ImplicitList52[] = { Hexagon::VTMP, 0 };
gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc 291 extern const MCPhysReg HexagonRegDiffLists[] = {
872 extern const MCPhysReg HexagonRegUnitRoots[][2] = {
1004 const MCPhysReg UsrBits[] = {
1014 const MCPhysReg GuestRegs[] = {
1024 const MCPhysReg IntRegs[] = {
1034 const MCPhysReg CtrRegs[] = {
1044 const MCPhysReg GeneralSubRegs[] = {
1054 const MCPhysReg V62Regs[] = {
1064 const MCPhysReg IntRegsLow8[] = {
1074 const MCPhysReg CtrRegs_and_V62Regs[] = {
1084 const MCPhysReg PredRegs[] = {
1094 const MCPhysReg V62Regs_with_isub_hi[] = {
1104 const MCPhysReg ModRegs[] = {
1114 const MCPhysReg CtrRegs_with_subreg_overflow[] = {
1124 const MCPhysReg V65Regs[] = {
1134 const MCPhysReg DoubleRegs[] = {
1144 const MCPhysReg GuestRegs64[] = {
1154 const MCPhysReg CtrRegs64[] = {
1164 const MCPhysReg GeneralDoubleLow8Regs[] = {
1174 const MCPhysReg DoubleRegs_with_isub_hi_in_IntRegsLow8[] = {
1184 const MCPhysReg CtrRegs64_and_V62Regs[] = {
1194 const MCPhysReg CtrRegs64_with_isub_hi_in_ModRegs[] = {
1204 const MCPhysReg HvxVR[] = {
1214 const MCPhysReg HvxQR[] = {
1224 const MCPhysReg HvxVR_and_V65Regs[] = {
1234 const MCPhysReg HvxWR[] = {
1244 const MCPhysReg HvxVQR[] = {
3638 extern const MCPhysReg HexagonRegDiffLists[];
3642 extern const MCPhysReg HexagonRegUnitRoots[][2];
3708 static const MCPhysReg HexagonCSR_SaveList[] = { Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 };
gen/lib/Target/Lanai/LanaiGenCallingConv.inc 38 static const MCPhysReg RegList1[] = {
74 static const MCPhysReg RegList1[] = {
97 static const MCPhysReg RegList1[] = {
gen/lib/Target/Lanai/LanaiGenInstrInfo.inc 321 static const MCPhysReg ImplicitList1[] = { Lanai::SP, 0 };
322 static const MCPhysReg ImplicitList2[] = { Lanai::RCA, 0 };
323 static const MCPhysReg ImplicitList3[] = { Lanai::SR, 0 };
gen/lib/Target/Lanai/LanaiGenRegisterInfo.inc 105 extern const MCPhysReg LanaiRegDiffLists[] = {
226 extern const MCPhysReg LanaiRegUnitRoots[][2] = {
264 const MCPhysReg GPR[] = {
274 const MCPhysReg GPR_with_sub_32[] = {
284 const MCPhysReg CCR[] = {
887 extern const MCPhysReg LanaiRegDiffLists[];
891 extern const MCPhysReg LanaiRegUnitRoots[][2];
957 static const MCPhysReg CSR_SaveList[] = { 0 };
gen/lib/Target/MSP430/MSP430GenCallingConv.inc 51 static const MCPhysReg RegList1[] = {
61 static const MCPhysReg RegList2[] = {
gen/lib/Target/MSP430/MSP430GenInstrInfo.inc 558 static const MCPhysReg ImplicitList1[] = { MSP430::SR, 0 };
559 static const MCPhysReg ImplicitList2[] = { MSP430::SP, 0 };
560 static const MCPhysReg ImplicitList3[] = { MSP430::SP, MSP430::SR, 0 };
561 static const MCPhysReg ImplicitList4[] = { MSP430::R11, MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, MSP430::SR, 0 };
gen/lib/Target/MSP430/MSP430GenRegisterInfo.inc 96 extern const MCPhysReg MSP430RegDiffLists[] = {
194 extern const MCPhysReg MSP430RegUnitRoots[][2] = {
215 const MCPhysReg GR8[] = {
225 const MCPhysReg GR16[] = {
594 extern const MCPhysReg MSP430RegDiffLists[];
598 extern const MCPhysReg MSP430RegUnitRoots[][2];
gen/lib/Target/Mips/MipsGenCallingConv.inc 96 static const MCPhysReg RegList1[] = {
152 static const MCPhysReg RegList1[] = {
155 static const MCPhysReg RegList2[] = {
165 static const MCPhysReg RegList3[] = {
168 static const MCPhysReg RegList4[] = {
178 static const MCPhysReg RegList5[] = {
181 static const MCPhysReg RegList6[] = {
212 static const MCPhysReg RegList1[] = {
222 static const MCPhysReg RegList2[] = {
246 static const MCPhysReg RegList1[] = {
249 static const MCPhysReg RegList2[] = {
299 static const MCPhysReg RegList1[] = {
310 static const MCPhysReg RegList2[] = {
393 static const MCPhysReg RegList1[] = {
406 static const MCPhysReg RegList2[] = {
420 static const MCPhysReg RegList3[] = {
483 static const MCPhysReg RegList1[] = {
495 static const MCPhysReg RegList2[] = {
507 static const MCPhysReg RegList3[] = {
519 static const MCPhysReg RegList4[] = {
641 static const MCPhysReg RegList1[] = {
650 static const MCPhysReg RegList2[] = {
666 static const MCPhysReg RegList1[] = {
745 static const MCPhysReg RegList1[] = {
755 static const MCPhysReg RegList2[] = {
765 static const MCPhysReg RegList3[] = {
796 static const MCPhysReg RegList1[] = {
807 static const MCPhysReg RegList2[] = {
818 static const MCPhysReg RegList3[] = {
830 static const MCPhysReg RegList4[] = {
gen/lib/Target/Mips/MipsGenInstrInfo.inc 4429 static const MCPhysReg ImplicitList1[] = { Mips::SP, 0 };
4430 static const MCPhysReg ImplicitList2[] = { Mips::AT, 0 };
4431 static const MCPhysReg ImplicitList3[] = { Mips::RA, 0 };
4432 static const MCPhysReg ImplicitList4[] = { Mips::DSPPos, 0 };
4433 static const MCPhysReg ImplicitList5[] = { Mips::V0, Mips::V1, 0 };
4434 static const MCPhysReg ImplicitList6[] = { Mips::HI0, Mips::LO0, 0 };
4435 static const MCPhysReg ImplicitList7[] = { Mips::T8, 0 };
4436 static const MCPhysReg ImplicitList8[] = { Mips::DSPOutFlag20, 0 };
4437 static const MCPhysReg ImplicitList9[] = { Mips::DSPCarry, 0 };
4438 static const MCPhysReg ImplicitList10[] = { Mips::DSPCCond, 0 };
4439 static const MCPhysReg ImplicitList11[] = { Mips::HI0, Mips::LO0, Mips::P0, Mips::P1, Mips::P2, 0 };
4440 static const MCPhysReg ImplicitList12[] = { Mips::HI0_64, Mips::LO0_64, 0 };
4441 static const MCPhysReg ImplicitList13[] = { Mips::DSPOutFlag16_19, 0 };
4442 static const MCPhysReg ImplicitList14[] = { Mips::DSPEFI, 0 };
4443 static const MCPhysReg ImplicitList15[] = { Mips::DSPPos, Mips::DSPEFI, 0 };
4444 static const MCPhysReg ImplicitList16[] = { Mips::DSPOutFlag23, 0 };
4445 static const MCPhysReg ImplicitList17[] = { Mips::FCC0, 0 };
4446 static const MCPhysReg ImplicitList18[] = { Mips::DSPPos, Mips::DSPSCount, 0 };
4447 static const MCPhysReg ImplicitList19[] = { Mips::AC0, 0 };
4448 static const MCPhysReg ImplicitList20[] = { Mips::AC0_64, 0 };
4449 static const MCPhysReg ImplicitList21[] = { Mips::HI0, 0 };
4450 static const MCPhysReg ImplicitList22[] = { Mips::HI0_64, 0 };
4451 static const MCPhysReg ImplicitList23[] = { Mips::LO0, 0 };
4452 static const MCPhysReg ImplicitList24[] = { Mips::LO0_64, 0 };
4453 static const MCPhysReg ImplicitList25[] = { Mips::MPL0, Mips::P0, Mips::P1, Mips::P2, 0 };
4454 static const MCPhysReg ImplicitList26[] = { Mips::MPL1, Mips::P0, Mips::P1, Mips::P2, 0 };
4455 static const MCPhysReg ImplicitList27[] = { Mips::MPL2, Mips::P0, Mips::P1, Mips::P2, 0 };
4456 static const MCPhysReg ImplicitList28[] = { Mips::P0, 0 };
4457 static const MCPhysReg ImplicitList29[] = { Mips::P1, 0 };
4458 static const MCPhysReg ImplicitList30[] = { Mips::P2, 0 };
4459 static const MCPhysReg ImplicitList31[] = { Mips::DSPOutFlag21, 0 };
4460 static const MCPhysReg ImplicitList32[] = { Mips::DSPOutFlag22, 0 };
4461 static const MCPhysReg ImplicitList33[] = { Mips::P0, Mips::P1, Mips::P2, 0 };
4462 static const MCPhysReg ImplicitList34[] = { Mips::MPL1, Mips::MPL2, Mips::P0, Mips::P1, Mips::P2, 0 };
gen/lib/Target/Mips/MipsGenRegisterInfo.inc 583 extern const MCPhysReg MipsRegDiffLists[] = {
1590 extern const MCPhysReg MipsRegUnitRoots[][2] = {
1916 const MCPhysReg MSA128F16[] = {
1926 const MCPhysReg CCR[] = {
1936 const MCPhysReg COP0[] = {
1946 const MCPhysReg COP2[] = {
1956 const MCPhysReg COP3[] = {
1966 const MCPhysReg DSPR[] = {
1976 const MCPhysReg FGR32[] = {
1986 const MCPhysReg FGRCC[] = {
1996 const MCPhysReg GPR32[] = {
2006 const MCPhysReg HWRegs[] = {
2016 const MCPhysReg MSACtrl[] = {
2026 const MCPhysReg GPR32NONZERO[] = {
2036 const MCPhysReg CPU16RegsPlusSP[] = {
2046 const MCPhysReg CPU16Regs[] = {
2056 const MCPhysReg FCC[] = {
2066 const MCPhysReg GPRMM16[] = {
2076 const MCPhysReg GPRMM16MoveP[] = {
2086 const MCPhysReg GPRMM16Zero[] = {
2096 const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = {
2106 const MCPhysReg GPR32NONZERO_and_GPRMM16MoveP[] = {
2116 const MCPhysReg GPRMM16MovePPairSecond[] = {
2126 const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = {
2136 const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = {
2146 const MCPhysReg HI32DSP[] = {
2156 const MCPhysReg LO32DSP[] = {
2166 const MCPhysReg CPU16Regs_and_GPRMM16MovePPairSecond[] = {
2176 const MCPhysReg GPRMM16MovePPairFirst[] = {
2186 const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
2196 const MCPhysReg GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = {
2206 const MCPhysReg CPURAReg[] = {
2216 const MCPhysReg CPUSPReg[] = {
2226 const MCPhysReg DSPCC[] = {
2236 const MCPhysReg GP32[] = {
2246 const MCPhysReg GPR32ZERO[] = {
2256 const MCPhysReg HI32[] = {
2266 const MCPhysReg LO32[] = {
2276 const MCPhysReg SP32[] = {
2286 const MCPhysReg FGR64[] = {
2296 const MCPhysReg GPR64[] = {
2306 const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO[] = {
2316 const MCPhysReg AFGR64[] = {
2326 const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = {
2336 const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = {
2346 const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = {
2356 const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = {
2366 const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = {
2376 const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP[] = {
2386 const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairSecond[] = {
2396 const MCPhysReg ACC64DSP[] = {
2406 const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = {
2416 const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = {
2426 const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond[] = {
2436 const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst[] = {
2446 const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
2456 const MCPhysReg OCTEON_MPL[] = {
2466 const MCPhysReg OCTEON_P[] = {
2476 const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = {
2486 const MCPhysReg ACC64[] = {
2496 const MCPhysReg GP64[] = {
2506 const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = {
2516 const MCPhysReg GPR64_with_sub_32_in_GPR32ZERO[] = {
2526 const MCPhysReg HI64[] = {
2536 const MCPhysReg LO64[] = {
2546 const MCPhysReg SP64[] = {
2556 const MCPhysReg MSA128B[] = {
2566 const MCPhysReg MSA128D[] = {
2576 const MCPhysReg MSA128H[] = {
2586 const MCPhysReg MSA128W[] = {
2596 const MCPhysReg MSA128WEvens[] = {
2606 const MCPhysReg ACC128[] = {
4765 static ArrayRef<MCPhysReg> FGR32GetRawAllocationOrder(const MachineFunction &MF) {
4766 static const MCPhysReg AltOrder1[] = { Mips::F0, Mips::F2, Mips::F4, Mips::F6, Mips::F8, Mips::F10, Mips::F12, Mips::F14, Mips::F16, Mips::F18, Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30 };
4768 const ArrayRef<MCPhysReg> Order[] = {
4782 static ArrayRef<MCPhysReg> FGR64GetRawAllocationOrder(const MachineFunction &MF) {
4783 static const MCPhysReg AltOrder1[] = { Mips::D0_64, Mips::D2_64, Mips::D4_64, Mips::D6_64, Mips::D8_64, Mips::D10_64, Mips::D12_64, Mips::D14_64, Mips::D16_64, Mips::D18_64, Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64 };
4785 const ArrayRef<MCPhysReg> Order[] = {
7330 extern const MCPhysReg MipsRegDiffLists[];
7334 extern const MCPhysReg MipsRegUnitRoots[][2];
7400 static const MCPhysReg CSR_Interrupt_32_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, Mips::LO0, Mips::HI0, 0 };
7402 static const MCPhysReg CSR_Interrupt_32R6_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, 0 };
7404 static const MCPhysReg CSR_Interrupt_64_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::V1_64, Mips::V0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, Mips::LO0_64, Mips::HI0_64, 0 };
7406 static const MCPhysReg CSR_Interrupt_64R6_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::V1_64, Mips::V0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, 0 };
7408 static const MCPhysReg CSR_Mips16RetHelper_SaveList[] = { Mips::V0, Mips::V1, Mips::FP, Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, 0 };
7410 static const MCPhysReg CSR_N32_SaveList[] = { Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
7412 static const MCPhysReg CSR_N64_SaveList[] = { Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64, Mips::D26_64, Mips::D25_64, Mips::D24_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
7414 static const MCPhysReg CSR_O32_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
7416 static const MCPhysReg CSR_O32_FP64_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
7418 static const MCPhysReg CSR_O32_FPXX_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
7420 static const MCPhysReg CSR_SingleFloatOnly_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
gen/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc 159 extern const MCPhysReg NVPTXRegDiffLists[] = {
367 extern const MCPhysReg NVPTXRegUnitRoots[][2] = {
467 const MCPhysReg Int1Regs[] = {
477 const MCPhysReg Float16Regs[] = {
487 const MCPhysReg Int16Regs[] = {
497 const MCPhysReg SpecialRegs[] = {
507 const MCPhysReg Float16x2Regs[] = {
517 const MCPhysReg Float32ArgRegs[] = {
527 const MCPhysReg Float32Regs[] = {
537 const MCPhysReg Int32ArgRegs[] = {
547 const MCPhysReg Int32Regs[] = {
557 const MCPhysReg Float64ArgRegs[] = {
567 const MCPhysReg Float64Regs[] = {
577 const MCPhysReg Int64ArgRegs[] = {
587 const MCPhysReg Int64Regs[] = {
1295 extern const MCPhysReg NVPTXRegDiffLists[];
1299 extern const MCPhysReg NVPTXRegUnitRoots[][2];
gen/lib/Target/PowerPC/PPCGenCallingConv.inc 49 static const MCPhysReg RegList1[] = {
67 static const MCPhysReg RegList2[] = {
79 static const MCPhysReg RegList3[] = {
170 static const MCPhysReg RegList1[] = {
189 static const MCPhysReg RegList2[] = {
208 static const MCPhysReg RegList3[] = {
359 static const MCPhysReg RegList1[] = {
370 static const MCPhysReg RegList2[] = {
418 static const MCPhysReg RegList1[] = {
428 static const MCPhysReg RegList2[] = {
438 static const MCPhysReg RegList3[] = {
449 static const MCPhysReg RegList4[] = {
461 static const MCPhysReg RegList5[] = {
473 static const MCPhysReg RegList6[] = {
492 static const MCPhysReg RegList7[] = {
506 static const MCPhysReg RegList8[] = {
524 static const MCPhysReg RegList9[] = {
599 static const MCPhysReg RegList1[] = {
609 static const MCPhysReg RegList2[] = {
619 static const MCPhysReg RegList3[] = {
629 static const MCPhysReg RegList4[] = {
640 static const MCPhysReg RegList5[] = {
654 static const MCPhysReg RegList6[] = {
672 static const MCPhysReg RegList7[] = {
gen/lib/Target/PowerPC/PPCGenInstrInfo.inc 2574 static const MCPhysReg ImplicitList1[] = { PPC::CR7, 0 };
2575 static const MCPhysReg ImplicitList2[] = { PPC::RM, 0 };
2576 static const MCPhysReg ImplicitList3[] = { PPC::CR0, 0 };
2577 static const MCPhysReg ImplicitList4[] = { PPC::CARRY, 0 };
2578 static const MCPhysReg ImplicitList5[] = { PPC::CARRY, PPC::CR0, 0 };
2579 static const MCPhysReg ImplicitList6[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::LR8, PPC::CTR8, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
2580 static const MCPhysReg ImplicitList7[] = { PPC::R0, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::LR, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
2581 static const MCPhysReg ImplicitList8[] = { PPC::R1, 0 };
2582 static const MCPhysReg ImplicitList9[] = { PPC::CTR, 0 };
2583 static const MCPhysReg ImplicitList10[] = { PPC::CTR8, 0 };
2584 static const MCPhysReg ImplicitList11[] = { PPC::CTR, PPC::RM, 0 };
2585 static const MCPhysReg ImplicitList12[] = { PPC::LR, 0 };
2586 static const MCPhysReg ImplicitList13[] = { PPC::CTR8, PPC::RM, 0 };
2587 static const MCPhysReg ImplicitList14[] = { PPC::LR8, 0 };
2588 static const MCPhysReg ImplicitList15[] = { PPC::LR, PPC::RM, 0 };
2589 static const MCPhysReg ImplicitList16[] = { PPC::CR6, 0 };
2590 static const MCPhysReg ImplicitList17[] = { PPC::LR8, PPC::X2, 0 };
2591 static const MCPhysReg ImplicitList18[] = { PPC::CTR, PPC::LR, PPC::RM, 0 };
2592 static const MCPhysReg ImplicitList19[] = { PPC::CTR8, PPC::LR8, PPC::RM, 0 };
2593 static const MCPhysReg ImplicitList20[] = { PPC::LR8, PPC::RM, 0 };
2594 static const MCPhysReg ImplicitList21[] = { PPC::CR1EQ, 0 };
2595 static const MCPhysReg ImplicitList22[] = { PPC::X1, 0 };
2596 static const MCPhysReg ImplicitList23[] = { PPC::CR1, 0 };
2597 static const MCPhysReg ImplicitList24[] = { PPC::X0, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::LR8, PPC::CTR8, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
2598 static const MCPhysReg ImplicitList25[] = { PPC::R0, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::LR, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
2599 static const MCPhysReg ImplicitList26[] = { PPC::LR, PPC::CTR, 0 };
gen/lib/Target/PowerPC/PPCGenRegisterInfo.inc 444 extern const MCPhysReg PPCRegDiffLists[] = {
1159 extern const MCPhysReg PPCRegUnitRoots[][2] = {
1335 const MCPhysReg VSSRC[] = {
1345 const MCPhysReg GPRC[] = {
1355 const MCPhysReg GPRC_NOR0[] = {
1365 const MCPhysReg GPRC_and_GPRC_NOR0[] = {
1375 const MCPhysReg CRBITRC[] = {
1385 const MCPhysReg F4RC[] = {
1395 const MCPhysReg CRRC[] = {
1405 const MCPhysReg CARRYRC[] = {
1415 const MCPhysReg CTRRC[] = {
1425 const MCPhysReg VRSAVERC[] = {
1435 const MCPhysReg SPILLTOVSRRC[] = {
1445 const MCPhysReg VSFRC[] = {
1455 const MCPhysReg G8RC[] = {
1465 const MCPhysReg G8RC_NOX0[] = {
1475 const MCPhysReg SPILLTOVSRRC_and_VSFRC[] = {
1485 const MCPhysReg G8RC_and_G8RC_NOX0[] = {
1495 const MCPhysReg F8RC[] = {
1505 const MCPhysReg SPERC[] = {
1515 const MCPhysReg VFRC[] = {
1525 const MCPhysReg SPERC_with_sub_32_in_GPRC_NOR0[] = {
1535 const MCPhysReg SPILLTOVSRRC_and_VFRC[] = {
1545 const MCPhysReg SPILLTOVSRRC_and_F4RC[] = {
1555 const MCPhysReg CTRRC8[] = {
1565 const MCPhysReg VSRC[] = {
1575 const MCPhysReg VSRC_with_sub_64_in_SPILLTOVSRRC[] = {
1585 const MCPhysReg QSRC[] = {
1595 const MCPhysReg VRRC[] = {
1605 const MCPhysReg VSLRC[] = {
1615 const MCPhysReg VRRC_with_sub_64_in_SPILLTOVSRRC[] = {
1625 const MCPhysReg QSRC_with_sub_64_in_SPILLTOVSRRC[] = {
1635 const MCPhysReg VSLRC_with_sub_64_in_SPILLTOVSRRC[] = {
1645 const MCPhysReg QBRC[] = {
1655 const MCPhysReg QFRC[] = {
1665 const MCPhysReg QBRC_with_sub_64_in_SPILLTOVSRRC[] = {
4276 static ArrayRef<MCPhysReg> GPRCGetRawAllocationOrder(const MachineFunction &MF) {
4277 static const MCPhysReg AltOrder1[] = { PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R0, PPC::R1, PPC::FP, PPC::BP, PPC::R2 };
4279 const ArrayRef<MCPhysReg> Order[] = {
4292 static ArrayRef<MCPhysReg> GPRC_NOR0GetRawAllocationOrder(const MachineFunction &MF) {
4293 static const MCPhysReg AltOrder1[] = { PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP, PPC::ZERO, PPC::R2 };
4295 const ArrayRef<MCPhysReg> Order[] = {
4308 static ArrayRef<MCPhysReg> GPRC_and_GPRC_NOR0GetRawAllocationOrder(const MachineFunction &MF) {
4309 static const MCPhysReg AltOrder1[] = { PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP, PPC::R2 };
4311 const ArrayRef<MCPhysReg> Order[] = {
4324 static ArrayRef<MCPhysReg> G8RCGetRawAllocationOrder(const MachineFunction &MF) {
4325 static const MCPhysReg AltOrder1[] = { PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X0, PPC::X1, PPC::FP8, PPC::BP8, PPC::X2 };
4327 const ArrayRef<MCPhysReg> Order[] = {
4340 static ArrayRef<MCPhysReg> G8RC_NOX0GetRawAllocationOrder(const MachineFunction &MF) {
4341 static const MCPhysReg AltOrder1[] = { PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::ZERO8, PPC::X2 };
4343 const ArrayRef<MCPhysReg> Order[] = {
4356 static ArrayRef<MCPhysReg> G8RC_and_G8RC_NOX0GetRawAllocationOrder(const MachineFunction &MF) {
4357 static const MCPhysReg AltOrder1[] = { PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::X2 };
4359 const ArrayRef<MCPhysReg> Order[] = {
5644 extern const MCPhysReg PPCRegDiffLists[];
5648 extern const MCPhysReg PPCRegUnitRoots[][2];
5738 static const MCPhysReg CSR_64_AllRegs_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
5740 static const MCPhysReg CSR_64_AllRegs_Altivec_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
5742 static const MCPhysReg CSR_64_AllRegs_VSX_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23, PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27, PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31, 0 };
5744 static const MCPhysReg CSR_AIX32_SaveList[] = { PPC::R13, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, 0 };
5746 static const MCPhysReg CSR_AIX64_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, 0 };
5748 static const MCPhysReg CSR_Altivec_SaveList[] = { PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
5750 static const MCPhysReg CSR_Darwin32_SaveList[] = { PPC::R13, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, 0 };
5752 static const MCPhysReg CSR_Darwin32_Altivec_SaveList[] = { PPC::R13, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
5754 static const MCPhysReg CSR_Darwin64_SaveList[] = { PPC::X13, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, 0 };
5756 static const MCPhysReg CSR_Darwin64_Altivec_SaveList[] = { PPC::X13, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
5758 static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
5760 static const MCPhysReg CSR_SPE_SaveList[] = { PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, PPC::S30, PPC::S31, 0 };
5762 static const MCPhysReg CSR_SRV464_TLS_PE_SaveList[] = { 0 };
5764 static const MCPhysReg CSR_SVR32_ColdCC_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, 0 };
5766 static const MCPhysReg CSR_SVR32_ColdCC_Altivec_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
5768 static const MCPhysReg CSR_SVR32_ColdCC_Common_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
5770 static const MCPhysReg CSR_SVR32_ColdCC_SPE_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::S4, PPC::S5, PPC::S6, PPC::S7, PPC::S8, PPC::S9, PPC::S10, PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, PPC::S30, PPC::S31, 0 };
5772 static const MCPhysReg CSR_SVR432_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, 0 };
5774 static const MCPhysReg CSR_SVR432_Altivec_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
5776 static const MCPhysReg CSR_SVR432_COMM_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, 0 };
5778 static const MCPhysReg CSR_SVR432_SPE_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, PPC::S30, PPC::S31, 0 };
5780 static const MCPhysReg CSR_SVR464_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, 0 };
5782 static const MCPhysReg CSR_SVR464_Altivec_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
5784 static const MCPhysReg CSR_SVR464_Altivec_ViaCopy_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
5786 static const MCPhysReg CSR_SVR464_R2_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::X2, 0 };
5788 static const MCPhysReg CSR_SVR464_R2_Altivec_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::X2, 0 };
5790 static const MCPhysReg CSR_SVR464_R2_Altivec_ViaCopy_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::X2, 0 };
5792 static const MCPhysReg CSR_SVR464_R2_ViaCopy_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::X2, 0 };
5794 static const MCPhysReg CSR_SVR464_ViaCopy_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, 0 };
5796 static const MCPhysReg CSR_SVR64_ColdCC_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
5798 static const MCPhysReg CSR_SVR64_ColdCC_Altivec_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
5800 static const MCPhysReg CSR_SVR64_ColdCC_R2_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::X2, 0 };
5802 static const MCPhysReg CSR_SVR64_ColdCC_R2_Altivec_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::X2, 0 };
gen/lib/Target/RISCV/RISCVGenInstrInfo.inc 549 static const MCPhysReg ImplicitList1[] = { RISCV::X2, 0 };
550 static const MCPhysReg ImplicitList2[] = { RISCV::X1, 0 };
gen/lib/Target/RISCV/RISCVGenRegisterInfo.inc 181 extern const MCPhysReg RISCVRegDiffLists[] = {
401 extern const MCPhysReg RISCVRegUnitRoots[][2] = {
470 const MCPhysReg FPR32[] = {
480 const MCPhysReg GPR[] = {
490 const MCPhysReg GPRNoX0[] = {
500 const MCPhysReg GPRNoX0X2[] = {
510 const MCPhysReg GPRTC[] = {
520 const MCPhysReg FPR32C[] = {
530 const MCPhysReg GPRC[] = {
540 const MCPhysReg GPRC_and_GPRTC[] = {
550 const MCPhysReg GPRX0[] = {
560 const MCPhysReg SP[] = {
570 const MCPhysReg FPR64[] = {
580 const MCPhysReg FPR64C[] = {
1790 extern const MCPhysReg RISCVRegDiffLists[];
1794 extern const MCPhysReg RISCVRegUnitRoots[][2];
1860 static const MCPhysReg CSR_ILP32D_LP64D_SaveList[] = { RISCV::X1, RISCV::X3, RISCV::X4, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::F8_D, RISCV::F9_D, RISCV::F18_D, RISCV::F19_D, RISCV::F20_D, RISCV::F21_D, RISCV::F22_D, RISCV::F23_D, RISCV::F24_D, RISCV::F25_D, RISCV::F26_D, RISCV::F27_D, 0 };
1862 static const MCPhysReg CSR_ILP32F_LP64F_SaveList[] = { RISCV::X1, RISCV::X3, RISCV::X4, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::F8_F, RISCV::F9_F, RISCV::F18_F, RISCV::F19_F, RISCV::F20_F, RISCV::F21_F, RISCV::F22_F, RISCV::F23_F, RISCV::F24_F, RISCV::F25_F, RISCV::F26_F, RISCV::F27_F, 0 };
1864 static const MCPhysReg CSR_ILP32_LP64_SaveList[] = { RISCV::X1, RISCV::X3, RISCV::X4, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, 0 };
1866 static const MCPhysReg CSR_Interrupt_SaveList[] = { RISCV::X1, RISCV::X3, RISCV::X4, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X8, RISCV::X9, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, 0 };
1868 static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
1870 static const MCPhysReg CSR_XLEN_F32_Interrupt_SaveList[] = { RISCV::X1, RISCV::X3, RISCV::X4, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X8, RISCV::X9, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::F0_F, RISCV::F1_F, RISCV::F2_F, RISCV::F3_F, RISCV::F4_F, RISCV::F5_F, RISCV::F6_F, RISCV::F7_F, RISCV::F10_F, RISCV::F11_F, RISCV::F12_F, RISCV::F13_F, RISCV::F14_F, RISCV::F15_F, RISCV::F16_F, RISCV::F17_F, RISCV::F28_F, RISCV::F29_F, RISCV::F30_F, RISCV::F31_F, RISCV::F8_F, RISCV::F9_F, RISCV::F18_F, RISCV::F19_F, RISCV::F20_F, RISCV::F21_F, RISCV::F22_F, RISCV::F23_F, RISCV::F24_F, RISCV::F25_F, RISCV::F26_F, RISCV::F27_F, 0 };
1872 static const MCPhysReg CSR_XLEN_F64_Interrupt_SaveList[] = { RISCV::X1, RISCV::X3, RISCV::X4, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X8, RISCV::X9, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::F0_D, RISCV::F1_D, RISCV::F2_D, RISCV::F3_D, RISCV::F4_D, RISCV::F5_D, RISCV::F6_D, RISCV::F7_D, RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D, RISCV::F14_D, RISCV::F15_D, RISCV::F16_D, RISCV::F17_D, RISCV::F28_D, RISCV::F29_D, RISCV::F30_D, RISCV::F31_D, RISCV::F8_D, RISCV::F9_D, RISCV::F18_D, RISCV::F19_D, RISCV::F20_D, RISCV::F21_D, RISCV::F22_D, RISCV::F23_D, RISCV::F24_D, RISCV::F25_D, RISCV::F26_D, RISCV::F27_D, 0 };
gen/lib/Target/Sparc/SparcGenCallingConv.inc 34 static const MCPhysReg RegList1[] = {
95 static const MCPhysReg RegList1[] = {
105 static const MCPhysReg RegList2[] = {
115 static const MCPhysReg RegList3[] = {
gen/lib/Target/Sparc/SparcGenInstrInfo.inc 766 static const MCPhysReg ImplicitList1[] = { SP::O6, 0 };
767 static const MCPhysReg ImplicitList2[] = { SP::O7, 0 };
768 static const MCPhysReg ImplicitList3[] = { SP::FCC0, 0 };
769 static const MCPhysReg ImplicitList4[] = { SP::ICC, 0 };
770 static const MCPhysReg ImplicitList5[] = { SP::CPSR, 0 };
771 static const MCPhysReg ImplicitList6[] = { SP::FSR, 0 };
772 static const MCPhysReg ImplicitList7[] = { SP::Y, SP::ICC, 0 };
773 static const MCPhysReg ImplicitList8[] = { SP::PSR, 0 };
774 static const MCPhysReg ImplicitList9[] = { SP::TBR, 0 };
775 static const MCPhysReg ImplicitList10[] = { SP::WIM, 0 };
776 static const MCPhysReg ImplicitList11[] = { SP::Y, 0 };
777 static const MCPhysReg ImplicitList12[] = { SP::Y, SP::ASR18, 0 };
778 static const MCPhysReg ImplicitList13[] = { SP::CPQ, 0 };
779 static const MCPhysReg ImplicitList14[] = { SP::FQ, 0 };
gen/lib/Target/Sparc/SparcGenRegisterInfo.inc 315 extern const MCPhysReg SparcRegDiffLists[] = {
914 extern const MCPhysReg SparcRegUnitRoots[][2] = {
1090 const MCPhysReg FCCRegs[] = {
1100 const MCPhysReg ASRRegs[] = {
1110 const MCPhysReg CoprocRegs[] = {
1120 const MCPhysReg FPRegs[] = {
1130 const MCPhysReg IntRegs[] = {
1140 const MCPhysReg DFPRegs[] = {
1150 const MCPhysReg I64Regs[] = {
1160 const MCPhysReg CoprocPair[] = {
1170 const MCPhysReg IntPair[] = {
1180 const MCPhysReg LowDFPRegs[] = {
1190 const MCPhysReg PRRegs[] = {
1200 const MCPhysReg QFPRegs[] = {
1210 const MCPhysReg LowQFPRegs[] = {
2755 extern const MCPhysReg SparcRegDiffLists[];
2759 extern const MCPhysReg SparcRegUnitRoots[][2];
2825 static const MCPhysReg CSR_SaveList[] = { 0 };
2827 static const MCPhysReg RTCSR_SaveList[] = { 0 };
gen/lib/Target/SystemZ/SystemZGenCallingConv.inc 62 static const MCPhysReg RegList1[] = {
72 static const MCPhysReg RegList2[] = {
82 static const MCPhysReg RegList3[] = {
92 static const MCPhysReg RegList4[] = {
109 static const MCPhysReg RegList5[] = {
186 static const MCPhysReg RegList1[] = {
196 static const MCPhysReg RegList2[] = {
206 static const MCPhysReg RegList3[] = {
216 static const MCPhysReg RegList4[] = {
232 static const MCPhysReg RegList5[] = {
gen/lib/Target/SystemZ/SystemZGenInstrInfo.inc 3916 static const MCPhysReg ImplicitList1[] = { SystemZ::CC, 0 };
3917 static const MCPhysReg ImplicitList2[] = { SystemZ::R1D, 0 };
3918 static const MCPhysReg ImplicitList3[] = { SystemZ::FPC, 0 };
3919 static const MCPhysReg ImplicitList4[] = { SystemZ::R14D, SystemZ::CC, 0 };
3920 static const MCPhysReg ImplicitList5[] = { SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, 0 };
3921 static const MCPhysReg ImplicitList6[] = { SystemZ::CC, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, 0 };
3922 static const MCPhysReg ImplicitList7[] = { SystemZ::R0L, 0 };
3923 static const MCPhysReg ImplicitList8[] = { SystemZ::R0L, SystemZ::R1D, 0 };
3924 static const MCPhysReg ImplicitList9[] = { SystemZ::CC, SystemZ::R1D, 0 };
3925 static const MCPhysReg ImplicitList10[] = { SystemZ::R1L, 0 };
3926 static const MCPhysReg ImplicitList11[] = { SystemZ::R0L, SystemZ::R1L, 0 };
3927 static const MCPhysReg ImplicitList12[] = { SystemZ::R0D, SystemZ::R1D, 0 };
3928 static const MCPhysReg ImplicitList13[] = { SystemZ::R2L, 0 };
3929 static const MCPhysReg ImplicitList14[] = { SystemZ::FPC, SystemZ::R0L, SystemZ::F4Q, 0 };
3930 static const MCPhysReg ImplicitList15[] = { SystemZ::CC, SystemZ::R1L, SystemZ::F0Q, 0 };
3931 static const MCPhysReg ImplicitList16[] = { SystemZ::R1L, SystemZ::R2D, 0 };
3932 static const MCPhysReg ImplicitList17[] = { SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, 0 };
3933 static const MCPhysReg ImplicitList18[] = { SystemZ::R0D, 0 };
3934 static const MCPhysReg ImplicitList19[] = { SystemZ::R0D, SystemZ::CC, 0 };
3935 static const MCPhysReg ImplicitList20[] = { SystemZ::R0L, SystemZ::CC, 0 };
3936 static const MCPhysReg ImplicitList21[] = { SystemZ::CC, SystemZ::R0L, SystemZ::R1D, 0 };
3937 static const MCPhysReg ImplicitList22[] = { SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, 0 };
3938 static const MCPhysReg ImplicitList23[] = { SystemZ::CC, SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R5D, 0 };
gen/lib/Target/SystemZ/SystemZGenRegisterInfo.inc 283 extern const MCPhysReg SystemZRegDiffLists[] = {
752 extern const MCPhysReg SystemZRegUnitRoots[][2] = {
855 const MCPhysReg GRX32Bit[] = {
865 const MCPhysReg VR32Bit[] = {
875 const MCPhysReg AR32Bit[] = {
885 const MCPhysReg FP32Bit[] = {
895 const MCPhysReg GR32Bit[] = {
905 const MCPhysReg GRH32Bit[] = {
915 const MCPhysReg ADDR32Bit[] = {
925 const MCPhysReg CCR[] = {
935 const MCPhysReg FPCRegs[] = {
945 const MCPhysReg AnyRegBit[] = {
955 const MCPhysReg AnyRegBit_with_subreg_h32_in_FP32Bit[] = {
965 const MCPhysReg VR64Bit[] = {
975 const MCPhysReg AnyRegBit_with_subreg_h64[] = {
985 const MCPhysReg CR64Bit[] = {
995 const MCPhysReg FP64Bit[] = {
1005 const MCPhysReg GR64Bit[] = {
1015 const MCPhysReg ADDR64Bit[] = {
1025 const MCPhysReg VR128Bit[] = {
1035 const MCPhysReg VF128Bit[] = {
1045 const MCPhysReg FP128Bit[] = {
1055 const MCPhysReg GR128Bit[] = {
1065 const MCPhysReg ADDR128Bit[] = {
2921 extern const MCPhysReg SystemZRegDiffLists[];
2925 extern const MCPhysReg SystemZRegUnitRoots[][2];
2991 static const MCPhysReg CSR_SystemZ_SaveList[] = { SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
2993 static const MCPhysReg CSR_SystemZ_AllRegs_SaveList[] = { SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
2995 static const MCPhysReg CSR_SystemZ_AllRegs_Vector_SaveList[] = { SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31, 0 };
2997 static const MCPhysReg CSR_SystemZ_SwiftError_SaveList[] = { SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
gen/lib/Target/WebAssembly/WebAssemblyGenInstrInfo.inc 1357 static const MCPhysReg ImplicitList1[] = { WebAssembly::ARGUMENTS, 0 };
1358 static const MCPhysReg ImplicitList2[] = { WebAssembly::SP32, WebAssembly::SP64, 0 };
1359 static const MCPhysReg ImplicitList3[] = { WebAssembly::VALUE_STACK, 0 };
gen/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc 69 extern const MCPhysReg WebAssemblyRegDiffLists[] = {
116 extern const MCPhysReg WebAssemblyRegUnitRoots[][2] = {
133 const MCPhysReg EXNREF[] = {
143 const MCPhysReg I32[] = {
153 const MCPhysReg F32[] = {
163 const MCPhysReg I64[] = {
173 const MCPhysReg F64[] = {
183 const MCPhysReg V128[] = {
548 extern const MCPhysReg WebAssemblyRegDiffLists[];
552 extern const MCPhysReg WebAssemblyRegUnitRoots[][2];
gen/lib/Target/X86/X86GenCallingConv.inc 173 static const MCPhysReg RegList1[] = {
185 static const MCPhysReg RegList2[] = {
197 static const MCPhysReg RegList3[] = {
209 static const MCPhysReg RegList4[] = {
231 static const MCPhysReg RegList6[] = {
244 static const MCPhysReg RegList7[] = {
257 static const MCPhysReg RegList8[] = {
405 static const MCPhysReg RegList1[] = {
437 static const MCPhysReg RegList1[] = {
451 static const MCPhysReg RegList2[] = {
589 static const MCPhysReg RegList1[] = {
602 static const MCPhysReg RegList2[] = {
649 static const MCPhysReg RegList1[] = {
661 static const MCPhysReg RegList2[] = {
673 static const MCPhysReg RegList3[] = {
706 static const MCPhysReg RegList1[] = {
735 static const MCPhysReg RegList1[] = {
833 static const MCPhysReg RegList1[] = {
879 static const MCPhysReg RegList2[] = {
903 static const MCPhysReg RegList3[] = {
920 static const MCPhysReg RegList4[] = {
937 static const MCPhysReg RegList5[] = {
1172 static const MCPhysReg RegList1[] = {
1190 static const MCPhysReg RegList2[] = {
1208 static const MCPhysReg RegList3[] = {
1236 static const MCPhysReg RegList1[] = {
1254 static const MCPhysReg RegList2[] = {
1272 static const MCPhysReg RegList3[] = {
1446 static const MCPhysReg RegList1[] = {
1456 static const MCPhysReg RegList2[] = {
1549 static const MCPhysReg RegList3[] = {
1567 static const MCPhysReg RegList4[] = {
1586 static const MCPhysReg RegList5[] = {
1669 static const MCPhysReg RegList1[] = {
1687 static const MCPhysReg RegList2[] = {
1704 static const MCPhysReg RegList3[] = {
1721 static const MCPhysReg RegList4[] = {
1740 static const MCPhysReg RegList1[] = {
1788 static const MCPhysReg RegList1[] = {
1899 static const MCPhysReg RegList1[] = {
1909 static const MCPhysReg RegList2[] = {
1930 static const MCPhysReg RegList3[] = {
1951 static const MCPhysReg RegList4[] = {
1975 static const MCPhysReg RegList5[] = {
1992 static const MCPhysReg RegList6[] = {
2009 static const MCPhysReg RegList7[] = {
2217 static const MCPhysReg RegList1[] = {
2220 static const MCPhysReg RegList2[] = {
2230 static const MCPhysReg RegList3[] = {
2233 static const MCPhysReg RegList4[] = {
2243 static const MCPhysReg RegList5[] = {
2246 static const MCPhysReg RegList6[] = {
2258 static const MCPhysReg RegList7[] = {
2261 static const MCPhysReg RegList8[] = {
2273 static const MCPhysReg RegList9[] = {
2276 static const MCPhysReg RegList10[] = {
2293 static const MCPhysReg RegList11[] = {
2296 static const MCPhysReg RegList12[] = {
2362 static const MCPhysReg RegList1[] = {
2372 static const MCPhysReg RegList2[] = {
2393 static const MCPhysReg RegList3[] = {
2414 static const MCPhysReg RegList4[] = {
2438 static const MCPhysReg RegList5[] = {
2455 static const MCPhysReg RegList6[] = {
2472 static const MCPhysReg RegList7[] = {
2591 static const MCPhysReg RegList1[] = {
2604 static const MCPhysReg RegList2[] = {
2617 static const MCPhysReg RegList3[] = {
2679 static const MCPhysReg RegList1[] = {
2689 static const MCPhysReg RegList2[] = {
2699 static const MCPhysReg RegList3[] = {
2709 static const MCPhysReg RegList4[] = {
2784 static const MCPhysReg RegList5[] = {
2799 static const MCPhysReg RegList6[] = {
2814 static const MCPhysReg RegList7[] = {
2832 static const MCPhysReg RegList8[] = {
2890 static const MCPhysReg RegList1[] = {
2903 static const MCPhysReg RegList2[] = {
2925 static const MCPhysReg RegList1[] = {
2937 static const MCPhysReg RegList2[] = {
2948 static const MCPhysReg RegList3[] = {
2958 static const MCPhysReg RegList4[] = {
2968 static const MCPhysReg RegList5[] = {
3000 static const MCPhysReg RegList1[] = {
3050 static const MCPhysReg RegList1[] = {
3060 static const MCPhysReg RegList2[] = {
3070 static const MCPhysReg RegList3[] = {
3113 static const MCPhysReg RegList4[] = {
3126 static const MCPhysReg RegList5[] = {
3143 static const MCPhysReg RegList6[] = {
3160 static const MCPhysReg RegList7[] = {
3177 static const MCPhysReg RegList8[] = {
3198 static const MCPhysReg RegList1[] = {
3298 static const MCPhysReg RegList1[] = {
3308 static const MCPhysReg RegList2[] = {
3318 static const MCPhysReg RegList3[] = {
3328 static const MCPhysReg RegList4[] = {
3370 static const MCPhysReg RegList1[] = {
3400 static const MCPhysReg RegList1[] = {
3447 static const MCPhysReg RegList1[] = {
3457 static const MCPhysReg RegList2[] = {
3467 static const MCPhysReg RegList3[] = {
3477 static const MCPhysReg RegList4[] = {
3487 static const MCPhysReg RegList5[] = {
3497 static const MCPhysReg RegList6[] = {
3507 static const MCPhysReg RegList7[] = {
3517 static const MCPhysReg RegList8[] = {
3540 static const MCPhysReg RegList1[] = {
3620 static const MCPhysReg RegList1[] = {
3630 static const MCPhysReg RegList2[] = {
3640 static const MCPhysReg RegList3[] = {
3650 static const MCPhysReg RegList4[] = {
3671 static const MCPhysReg RegList5[] = {
3689 static const MCPhysReg RegList6[] = {
3702 static const MCPhysReg RegList7[] = {
3719 static const MCPhysReg RegList8[] = {
3736 static const MCPhysReg RegList9[] = {
3753 static const MCPhysReg RegList10[] = {
3820 static const MCPhysReg RegList1[] = {
3830 static const MCPhysReg RegList2[] = {
3840 static const MCPhysReg RegList3[] = {
3850 static const MCPhysReg RegList4[] = {
3871 static const MCPhysReg RegList5[] = {
3889 static const MCPhysReg RegList6[] = {
3902 static const MCPhysReg RegList7[] = {
3919 static const MCPhysReg RegList8[] = {
3936 static const MCPhysReg RegList9[] = {
3953 static const MCPhysReg RegList10[] = {
gen/lib/Target/X86/X86GenInstrInfo.inc16563 static const MCPhysReg ImplicitList1[] = { X86::EFLAGS, 0 };
16564 static const MCPhysReg ImplicitList2[] = { X86::RAX, X86::RCX, X86::RDX, 0 };
16565 static const MCPhysReg ImplicitList3[] = { X86::RAX, X86::RDX, X86::RBX, X86::EFLAGS, 0 };
16566 static const MCPhysReg ImplicitList4[] = { X86::EAX, X86::ECX, X86::EDX, 0 };
16567 static const MCPhysReg ImplicitList5[] = { X86::EAX, X86::EDX, X86::EBX, X86::EFLAGS, 0 };
16568 static const MCPhysReg ImplicitList6[] = { X86::RSP, X86::SSP, 0 };
16569 static const MCPhysReg ImplicitList7[] = { X86::EAX, 0 };
16570 static const MCPhysReg ImplicitList8[] = { X86::AL, X86::EFLAGS, 0 };
16571 static const MCPhysReg ImplicitList9[] = { X86::AX, X86::EFLAGS, 0 };
16572 static const MCPhysReg ImplicitList10[] = { X86::AX, 0 };
16573 static const MCPhysReg ImplicitList11[] = { X86::AL, 0 };
16574 static const MCPhysReg ImplicitList12[] = { X86::FPCW, 0 };
16575 static const MCPhysReg ImplicitList13[] = { X86::FPSW, 0 };
16576 static const MCPhysReg ImplicitList14[] = { X86::EAX, X86::EFLAGS, 0 };
16577 static const MCPhysReg ImplicitList15[] = { X86::RAX, X86::EFLAGS, 0 };
16578 static const MCPhysReg ImplicitList16[] = { X86::RAX, 0 };
16579 static const MCPhysReg ImplicitList17[] = { X86::ESP, X86::SSP, 0 };
16580 static const MCPhysReg ImplicitList18[] = { X86::ESP, X86::EFLAGS, X86::SSP, 0 };
16581 static const MCPhysReg ImplicitList19[] = { X86::RSP, X86::EFLAGS, X86::SSP, 0 };
16582 static const MCPhysReg ImplicitList20[] = { X86::XMM0, 0 };
16583 static const MCPhysReg ImplicitList21[] = { X86::EAX, X86::EDX, 0 };
16584 static const MCPhysReg ImplicitList22[] = { X86::DF, 0 };
16585 static const MCPhysReg ImplicitList23[] = { X86::SSP, 0 };
16586 static const MCPhysReg ImplicitList24[] = { X86::EDI, X86::ESI, X86::DF, 0 };
16587 static const MCPhysReg ImplicitList25[] = { X86::EDI, X86::ESI, X86::EFLAGS, 0 };
16588 static const MCPhysReg ImplicitList26[] = { X86::RAX, X86::RBX, X86::RCX, X86::RDX, 0 };
16589 static const MCPhysReg ImplicitList27[] = { X86::RAX, X86::RDX, X86::EFLAGS, 0 };
16590 static const MCPhysReg ImplicitList28[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, 0 };
16591 static const MCPhysReg ImplicitList29[] = { X86::EAX, X86::EDX, X86::EFLAGS, 0 };
16592 static const MCPhysReg ImplicitList30[] = { X86::ST0, X86::FPCW, 0 };
16593 static const MCPhysReg ImplicitList31[] = { X86::EFLAGS, X86::FPSW, 0 };
16594 static const MCPhysReg ImplicitList32[] = { X86::EAX, X86::ECX, 0 };
16595 static const MCPhysReg ImplicitList33[] = { X86::RAX, X86::RDX, 0 };
16596 static const MCPhysReg ImplicitList34[] = { X86::AX, X86::DX, 0 };
16597 static const MCPhysReg ImplicitList35[] = { X86::AX, X86::DX, X86::EFLAGS, 0 };
16598 static const MCPhysReg ImplicitList36[] = { X86::AL, X86::AH, X86::EFLAGS, 0 };
16599 static const MCPhysReg ImplicitList37[] = { X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, 0 };
16600 static const MCPhysReg ImplicitList38[] = { X86::FPSW, X86::FPCW, 0 };
16601 static const MCPhysReg ImplicitList39[] = { X86::RAX, X86::RBX, X86::RCX, 0 };
16602 static const MCPhysReg ImplicitList40[] = { X86::AL, X86::EFLAGS, X86::AX, 0 };
16603 static const MCPhysReg ImplicitList41[] = { X86::DX, 0 };
16604 static const MCPhysReg ImplicitList42[] = { X86::DX, X86::EDI, X86::DF, 0 };
16605 static const MCPhysReg ImplicitList43[] = { X86::EDI, 0 };
16606 static const MCPhysReg ImplicitList44[] = { X86::RAX, X86::ECX, 0 };
16607 static const MCPhysReg ImplicitList45[] = { X86::CX, 0 };
16608 static const MCPhysReg ImplicitList46[] = { X86::ECX, 0 };
16609 static const MCPhysReg ImplicitList47[] = { X86::RCX, 0 };
16610 static const MCPhysReg ImplicitList48[] = { X86::AH, 0 };
16611 static const MCPhysReg ImplicitList49[] = { X86::EBP, X86::ESP, 0 };
16612 static const MCPhysReg ImplicitList50[] = { X86::RBP, X86::RSP, 0 };
16613 static const MCPhysReg ImplicitList51[] = { X86::ESI, X86::DF, 0 };
16614 static const MCPhysReg ImplicitList52[] = { X86::AL, X86::ESI, 0 };
16615 static const MCPhysReg ImplicitList53[] = { X86::EAX, X86::ESI, 0 };
16616 static const MCPhysReg ImplicitList54[] = { X86::RAX, X86::ESI, 0 };
16617 static const MCPhysReg ImplicitList55[] = { X86::AX, X86::ESI, 0 };
16618 static const MCPhysReg ImplicitList56[] = { X86::RDI, 0 };
16619 static const MCPhysReg ImplicitList57[] = { X86::RAX, X86::ECX, X86::EDX, 0 };
16620 static const MCPhysReg ImplicitList58[] = { X86::RAX, X86::RSI, 0 };
16621 static const MCPhysReg ImplicitList59[] = { X86::RAX, X86::RDX, X86::RSI, 0 };
16622 static const MCPhysReg ImplicitList60[] = { X86::EDI, X86::ESI, 0 };
16623 static const MCPhysReg ImplicitList61[] = { X86::EDX, 0 };
16624 static const MCPhysReg ImplicitList62[] = { X86::RDX, 0 };
16625 static const MCPhysReg ImplicitList63[] = { X86::ECX, X86::EAX, X86::EBX, 0 };
16626 static const MCPhysReg ImplicitList64[] = { X86::ECX, X86::EAX, 0 };
16627 static const MCPhysReg ImplicitList65[] = { X86::DX, X86::AX, 0 };
16628 static const MCPhysReg ImplicitList66[] = { X86::DX, X86::EAX, 0 };
16629 static const MCPhysReg ImplicitList67[] = { X86::DX, X86::AL, 0 };
16630 static const MCPhysReg ImplicitList68[] = { X86::DX, X86::ESI, X86::DF, 0 };
16631 static const MCPhysReg ImplicitList69[] = { X86::ESI, 0 };
16632 static const MCPhysReg ImplicitList70[] = { X86::ECX, X86::EFLAGS, 0 };
16633 static const MCPhysReg ImplicitList71[] = { X86::XMM0, X86::EFLAGS, 0 };
16634 static const MCPhysReg ImplicitList72[] = { X86::RAX, X86::RBX, X86::RCX, X86::RDX, X86::EFLAGS, 0 };
16635 static const MCPhysReg ImplicitList73[] = { X86::ESP, 0 };
16636 static const MCPhysReg ImplicitList74[] = { X86::RSP, 0 };
16637 static const MCPhysReg ImplicitList75[] = { X86::EDI, X86::ESI, X86::EBP, X86::EBX, X86::EDX, X86::ECX, X86::EAX, X86::ESP, 0 };
16638 static const MCPhysReg ImplicitList76[] = { X86::ESP, X86::EFLAGS, X86::DF, 0 };
16639 static const MCPhysReg ImplicitList77[] = { X86::RSP, X86::EFLAGS, X86::DF, 0 };
16640 static const MCPhysReg ImplicitList78[] = { X86::CL, X86::EFLAGS, 0 };
16641 static const MCPhysReg ImplicitList79[] = { X86::ECX, X86::DF, 0 };
16642 static const MCPhysReg ImplicitList80[] = { X86::ECX, X86::EDI, X86::ESI, 0 };
16643 static const MCPhysReg ImplicitList81[] = { X86::RCX, X86::RDI, X86::RSI, 0 };
16644 static const MCPhysReg ImplicitList82[] = { X86::AL, X86::ECX, X86::EDI, 0 };
16645 static const MCPhysReg ImplicitList83[] = { X86::ECX, X86::EDI, 0 };
16646 static const MCPhysReg ImplicitList84[] = { X86::AL, X86::RCX, X86::RDI, 0 };
16647 static const MCPhysReg ImplicitList85[] = { X86::RCX, X86::RDI, 0 };
16648 static const MCPhysReg ImplicitList86[] = { X86::EAX, X86::ECX, X86::EDI, 0 };
16649 static const MCPhysReg ImplicitList87[] = { X86::RAX, X86::RCX, X86::RDI, 0 };
16650 static const MCPhysReg ImplicitList88[] = { X86::AX, X86::ECX, X86::EDI, 0 };
16651 static const MCPhysReg ImplicitList89[] = { X86::AX, X86::RCX, X86::RDI, 0 };
16652 static const MCPhysReg ImplicitList90[] = { X86::CL, 0 };
16653 static const MCPhysReg ImplicitList91[] = { X86::AL, X86::EDI, X86::DF, 0 };
16654 static const MCPhysReg ImplicitList92[] = { X86::EDI, X86::EFLAGS, 0 };
16655 static const MCPhysReg ImplicitList93[] = { X86::EAX, X86::EDI, X86::DF, 0 };
16656 static const MCPhysReg ImplicitList94[] = { X86::RAX, X86::EDI, X86::DF, 0 };
16657 static const MCPhysReg ImplicitList95[] = { X86::AX, X86::EDI, X86::DF, 0 };
16658 static const MCPhysReg ImplicitList96[] = { X86::EAX, X86::ESP, X86::EFLAGS, 0 };
16659 static const MCPhysReg ImplicitList97[] = { X86::RAX, X86::RSP, X86::EFLAGS, 0 };
16660 static const MCPhysReg ImplicitList98[] = { X86::RAX, X86::RDI, X86::DF, 0 };
16661 static const MCPhysReg ImplicitList99[] = { X86::EAX, X86::ECX, X86::EFLAGS, X86::DF, 0 };
16662 static const MCPhysReg ImplicitList100[] = { X86::RAX, X86::EFLAGS, X86::DF, 0 };
16663 static const MCPhysReg ImplicitList101[] = { X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::FP7, X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::EFLAGS, X86::DF, 0 };
16664 static const MCPhysReg ImplicitList102[] = { X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::FP7, X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::EFLAGS, X86::DF, 0 };
16665 static const MCPhysReg ImplicitList103[] = { X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
16666 static const MCPhysReg ImplicitList104[] = { X86::RBX, X86::RDX, X86::RSI, X86::RDI, 0 };
16667 static const MCPhysReg ImplicitList105[] = { X86::RSI, X86::RDI, 0 };
16668 static const MCPhysReg ImplicitList106[] = { X86::EDX, X86::EAX, 0 };
16669 static const MCPhysReg ImplicitList107[] = { X86::AL, X86::EBX, 0 };
16670 static const MCPhysReg ImplicitList108[] = { X86::EDX, X86::EAX, X86::ECX, 0 };
16671 static const MCPhysReg ImplicitList109[] = { X86::RAX, X86::RSI, X86::RDI, 0 };
16672 static const MCPhysReg ImplicitList110[] = { X86::RDX, X86::RDI, 0 };
16673 static const MCPhysReg ImplicitList111[] = { X86::RAX, X86::RDI, 0 };
gen/lib/Target/X86/X86GenRegisterInfo.inc 470 extern const MCPhysReg X86RegDiffLists[] = {
1144 extern const MCPhysReg X86RegUnitRoots[][2] = {
1312 const MCPhysReg GR8[] = {
1322 const MCPhysReg GRH8[] = {
1332 const MCPhysReg GR8_NOREX[] = {
1342 const MCPhysReg GR8_ABCD_H[] = {
1352 const MCPhysReg GR8_ABCD_L[] = {
1362 const MCPhysReg GRH16[] = {
1372 const MCPhysReg GR16[] = {
1382 const MCPhysReg GR16_NOREX[] = {
1392 const MCPhysReg VK1[] = {
1402 const MCPhysReg VK16[] = {
1412 const MCPhysReg VK2[] = {
1422 const MCPhysReg VK4[] = {
1432 const MCPhysReg VK8[] = {
1442 const MCPhysReg VK16WM[] = {
1452 const MCPhysReg VK1WM[] = {
1462 const MCPhysReg VK2WM[] = {
1472 const MCPhysReg VK4WM[] = {
1482 const MCPhysReg VK8WM[] = {
1492 const MCPhysReg SEGMENT_REG[] = {
1502 const MCPhysReg GR16_ABCD[] = {
1512 const MCPhysReg FPCCR[] = {
1522 const MCPhysReg VK16PAIR[] = {
1532 const MCPhysReg VK1PAIR[] = {
1542 const MCPhysReg VK2PAIR[] = {
1552 const MCPhysReg VK4PAIR[] = {
1562 const MCPhysReg VK8PAIR[] = {
1572 const MCPhysReg VK16PAIR_with_sub_mask_0_in_VK16WM[] = {
1582 const MCPhysReg FR32X[] = {
1592 const MCPhysReg LOW32_ADDR_ACCESS_RBP[] = {
1602 const MCPhysReg LOW32_ADDR_ACCESS[] = {
1612 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit[] = {
1622 const MCPhysReg DEBUG_REG[] = {
1632 const MCPhysReg FR32[] = {
1642 const MCPhysReg GR32[] = {
1652 const MCPhysReg GR32_NOSP[] = {
1662 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX[] = {
1672 const MCPhysReg GR32_NOREX[] = {
1682 const MCPhysReg VK32[] = {
1692 const MCPhysReg GR32_NOREX_NOSP[] = {
1702 const MCPhysReg RFP32[] = {
1712 const MCPhysReg VK32WM[] = {
1722 const MCPhysReg GR32_ABCD[] = {
1732 const MCPhysReg GR32_TC[] = {
1742 const MCPhysReg GR32_ABCD_and_GR32_TC[] = {
1752 const MCPhysReg GR32_AD[] = {
1762 const MCPhysReg GR32_BPSP[] = {
1772 const MCPhysReg GR32_BSI[] = {
1782 const MCPhysReg GR32_CB[] = {
1792 const MCPhysReg GR32_DC[] = {
1802 const MCPhysReg GR32_DIBP[] = {
1812 const MCPhysReg GR32_SIDI[] = {
1822 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_32bit[] = {
1832 const MCPhysReg CCR[] = {
1842 const MCPhysReg DFCCR[] = {
1852 const MCPhysReg GR32_ABCD_and_GR32_BSI[] = {
1862 const MCPhysReg GR32_AD_and_GR32_DC[] = {
1872 const MCPhysReg GR32_BPSP_and_GR32_DIBP[] = {
1882 const MCPhysReg GR32_BPSP_and_GR32_TC[] = {
1892 const MCPhysReg GR32_BSI_and_GR32_SIDI[] = {
1902 const MCPhysReg GR32_CB_and_GR32_DC[] = {
1912 const MCPhysReg GR32_DIBP_and_GR32_SIDI[] = {
1922 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit[] = {
1932 const MCPhysReg LOW32_ADDR_ACCESS_with_sub_32bit[] = {
1942 const MCPhysReg RFP64[] = {
1952 const MCPhysReg FR64X[] = {
1962 const MCPhysReg GR64[] = {
1972 const MCPhysReg CONTROL_REG[] = {
1982 const MCPhysReg FR64[] = {
1992 const MCPhysReg GR64_with_sub_8bit[] = {
2002 const MCPhysReg GR64_NOSP[] = {
2012 const MCPhysReg GR64_TC[] = {
2022 const MCPhysReg GR64_NOREX[] = {
2032 const MCPhysReg GR64_TCW64[] = {
2042 const MCPhysReg GR64_TC_with_sub_8bit[] = {
2052 const MCPhysReg GR64_NOSP_and_GR64_TC[] = {
2062 const MCPhysReg GR64_TCW64_with_sub_8bit[] = {
2072 const MCPhysReg GR64_TC_and_GR64_TCW64[] = {
2082 const MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX[] = {
2092 const MCPhysReg VK64[] = {
2102 const MCPhysReg VR64[] = {
2112 const MCPhysReg GR64_NOREX_NOSP[] = {
2122 const MCPhysReg GR64_NOREX_and_GR64_TC[] = {
2132 const MCPhysReg GR64_NOSP_and_GR64_TCW64[] = {
2142 const MCPhysReg GR64_TCW64_and_GR64_TC_with_sub_8bit[] = {
2152 const MCPhysReg VK64WM[] = {
2162 const MCPhysReg GR64_TC_and_GR64_NOSP_and_GR64_TCW64[] = {
2172 const MCPhysReg GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX[] = {
2182 const MCPhysReg GR64_NOREX_NOSP_and_GR64_TC[] = {
2192 const MCPhysReg GR64_NOREX_and_GR64_TCW64[] = {
2202 const MCPhysReg GR64_ABCD[] = {
2212 const MCPhysReg GR64_with_sub_32bit_in_GR32_TC[] = {
2222 const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC[] = {
2232 const MCPhysReg GR64_AD[] = {
2242 const MCPhysReg GR64_and_LOW32_ADDR_ACCESS_RBP[] = {
2252 const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP[] = {
2262 const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI[] = {
2272 const MCPhysReg GR64_with_sub_32bit_in_GR32_CB[] = {
2282 const MCPhysReg GR64_with_sub_32bit_in_GR32_DC[] = {
2292 const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP[] = {
2302 const MCPhysReg GR64_with_sub_32bit_in_GR32_SIDI[] = {
2312 const MCPhysReg GR64_and_LOW32_ADDR_ACCESS[] = {
2322 const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI[] = {
2332 const MCPhysReg GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC[] = {
2342 const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP[] = {
2352 const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC[] = {
2362 const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI[] = {
2372 const MCPhysReg GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC[] = {
2382 const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI[] = {
2392 const MCPhysReg RST[] = {
2402 const MCPhysReg RFP80[] = {
2412 const MCPhysReg RFP80_7[] = {
2422 const MCPhysReg VR128X[] = {
2432 const MCPhysReg VR128[] = {
2442 const MCPhysReg BNDR[] = {
2452 const MCPhysReg VR256X[] = {
2462 const MCPhysReg VR256[] = {
2472 const MCPhysReg VR512[] = {
2482 const MCPhysReg VR512_0_15[] = {
6254 static ArrayRef<MCPhysReg> GR8GetRawAllocationOrder(const MachineFunction &MF) {
6255 static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B };
6257 const ArrayRef<MCPhysReg> Order[] = {
6270 static ArrayRef<MCPhysReg> GR8_NOREXGetRawAllocationOrder(const MachineFunction &MF) {
6271 static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL };
6273 const ArrayRef<MCPhysReg> Order[] = {
9880 extern const MCPhysReg X86RegDiffLists[];
9884 extern const MCPhysReg X86RegUnitRoots[][2];
9998 static const MCPhysReg CSR_32_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
10000 static const MCPhysReg CSR_32EHRet_SaveList[] = { X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
10002 static const MCPhysReg CSR_32_AllRegs_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, 0 };
10004 static const MCPhysReg CSR_32_AllRegs_AVX_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, 0 };
10006 static const MCPhysReg CSR_32_AllRegs_AVX512_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
10008 static const MCPhysReg CSR_32_AllRegs_SSE_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 };
10010 static const MCPhysReg CSR_32_RegCall_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 };
10012 static const MCPhysReg CSR_32_RegCall_NoSSE_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, 0 };
10014 static const MCPhysReg CSR_64_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
10016 static const MCPhysReg CSR_64EHRet_SaveList[] = { X86::RAX, X86::RDX, X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
10018 static const MCPhysReg CSR_64_AllRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::RAX, 0 };
10020 static const MCPhysReg CSR_64_AllRegs_AVX_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
10022 static const MCPhysReg CSR_64_AllRegs_AVX512_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
10024 static const MCPhysReg CSR_64_AllRegs_NoSSE_SaveList[] = { X86::RAX, X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
10026 static const MCPhysReg CSR_64_CXX_TLS_Darwin_PE_SaveList[] = { X86::RBP, 0 };
10028 static const MCPhysReg CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RCX, X86::RDX, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, 0 };
10030 static const MCPhysReg CSR_64_HHVM_SaveList[] = { X86::R12, 0 };
10032 static const MCPhysReg CSR_64_Intel_OCL_BI_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
10034 static const MCPhysReg CSR_64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
10036 static const MCPhysReg CSR_64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RDI, X86::RSI, X86::R14, X86::R15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
10038 static const MCPhysReg CSR_64_MostRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
10040 static const MCPhysReg CSR_64_RT_AllRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::RSP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
10042 static const MCPhysReg CSR_64_RT_AllRegs_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::RSP, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
10044 static const MCPhysReg CSR_64_RT_MostRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::RSP, 0 };
10046 static const MCPhysReg CSR_64_SwiftError_SaveList[] = { X86::RBX, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
10048 static const MCPhysReg CSR_64_TLS_Darwin_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RCX, X86::RDX, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, 0 };
10050 static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
10052 static const MCPhysReg CSR_SysV64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::RSP, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
10054 static const MCPhysReg CSR_SysV64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::RSP, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
10056 static const MCPhysReg CSR_Win32_CFGuard_Check_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::ECX, 0 };
10058 static const MCPhysReg CSR_Win32_CFGuard_Check_NoSSE_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::ECX, 0 };
10060 static const MCPhysReg CSR_Win64_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
10062 static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
10064 static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
10066 static const MCPhysReg CSR_Win64_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
10068 static const MCPhysReg CSR_Win64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::RSP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
10070 static const MCPhysReg CSR_Win64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::RSP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
10072 static const MCPhysReg CSR_Win64_SwiftError_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
gen/lib/Target/XCore/XCoreGenCallingConv.inc 40 static const MCPhysReg RegList1[] = {
64 static const MCPhysReg RegList1[] = {
gen/lib/Target/XCore/XCoreGenInstrInfo.inc 440 static const MCPhysReg ImplicitList1[] = { XCore::SP, 0 };
441 static const MCPhysReg ImplicitList2[] = { XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R11, XCore::LR, 0 };
442 static const MCPhysReg ImplicitList3[] = { XCore::R11, 0 };
gen/lib/Target/XCore/XCoreGenRegisterInfo.inc 69 extern const MCPhysReg XCoreRegDiffLists[] = {
124 extern const MCPhysReg XCoreRegUnitRoots[][2] = {
145 const MCPhysReg RRegs[] = {
155 const MCPhysReg GRRegs[] = {
533 extern const MCPhysReg XCoreRegDiffLists[];
537 extern const MCPhysReg XCoreRegUnitRoots[][2];
include/llvm/CodeGen/CallingConvLower.h 168 ForwardedRegister(unsigned VReg, MCPhysReg PReg, MVT VT)
171 MCPhysReg PReg;
344 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const {
371 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) {
385 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) {
412 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) {
412 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) {
450 ArrayRef<MCPhysReg> ShadowRegs) {
522 void getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, MVT VT,
include/llvm/CodeGen/LivePhysRegs.h 50 using RegisterSet = SparseSet<MCPhysReg, identity<MCPhysReg>>;
50 using RegisterSet = SparseSet<MCPhysReg, identity<MCPhysReg>>;
79 void addReg(MCPhysReg Reg) {
89 void removeReg(MCPhysReg Reg) {
98 SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> *Clobbers =
106 bool contains(MCPhysReg Reg) const { return LiveRegs.count(Reg); }
109 bool available(const MachineRegisterInfo &MRI, MCPhysReg Reg) const;
129 SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> &Clobbers);
include/llvm/CodeGen/LiveRegUnits.h 87 void addReg(MCPhysReg Reg) {
94 void addRegMasked(MCPhysReg Reg, LaneBitmask Mask) {
103 void removeReg(MCPhysReg Reg) {
117 bool available(MCPhysReg Reg) const {
include/llvm/CodeGen/MachineBasicBlock.h 73 MCPhysReg PhysReg;
76 RegisterMaskPair(MCPhysReg PhysReg, LaneBitmask LaneMask)
337 void removeLiveIn(MCPhysReg Reg,
341 bool isLiveIn(MCPhysReg Reg,
include/llvm/CodeGen/MachineRegisterInfo.h 92 SmallVector<MCPhysReg, 16> UpdatedCSRs;
240 const MCPhysReg *getCalleeSavedRegs() const;
244 void setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs);
include/llvm/CodeGen/ReachingDefAnalysis.h 98 int getClearance(MachineInstr *MI, MCPhysReg PhysReg);
include/llvm/CodeGen/Register.h 134 bool operator==(MCPhysReg Other) const { return Reg == unsigned(Other); }
135 bool operator!=(MCPhysReg Other) const { return Reg != unsigned(Other); }
include/llvm/CodeGen/RegisterClassInfo.h 37 std::unique_ptr<MCPhysReg[]> Order;
41 operator ArrayRef<MCPhysReg>() const {
59 const MCPhysReg *CalleeSavedRegs = nullptr;
62 SmallVector<MCPhysReg, 4> CalleeSavedAliases;
96 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const {
include/llvm/CodeGen/TargetLowering.h 3736 virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
include/llvm/CodeGen/TargetRegisterInfo.h 46 using iterator = const MCPhysReg *;
47 using const_iterator = const MCPhysReg *;
64 ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&);
77 iterator_range<SmallVectorImpl<MCPhysReg>::const_iterator>
196 ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const {
418 virtual const MCPhysReg*
453 virtual ArrayRef<MCPhysReg>
781 ArrayRef<MCPhysReg> Order,
782 SmallVectorImpl<MCPhysReg> &Hints,
968 ArrayRef<MCPhysReg> Exceptions = ArrayRef<MCPhysReg>()) const;
include/llvm/CodeGen/VirtRegMap.h 109 void assignVirt2Phys(Register virtReg, MCPhysReg physReg);
include/llvm/MC/MCInstrDesc.h 188 const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr
189 const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr
548 const MCPhysReg *getImplicitUses() const { return ImplicitUses; }
570 const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; }
585 if (const MCPhysReg *ImpUses = ImplicitUses)
include/llvm/MC/MCRegister.h 88 bool operator==(MCPhysReg Other) const { return Reg == unsigned(Other); }
89 bool operator!=(MCPhysReg Other) const { return Reg != unsigned(Other); }
include/llvm/MC/MCRegisterInfo.h 31 using iterator = const MCPhysReg*;
32 using const_iterator = const MCPhysReg*;
154 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
155 const MCPhysReg *DiffLists; // Pointer to the difflists array
186 const MCPhysReg *List = nullptr;
195 void init(MCPhysReg InitVal, const MCPhysReg *DiffList) {
195 void init(MCPhysReg InitVal, const MCPhysReg *DiffList) {
205 MCPhysReg D = *List++;
239 const MCPhysReg (*RURoots)[2],
241 const MCPhysReg *DL,
include/llvm/MCA/HardwareUnits/RegisterFile.h 120 MCPhysReg RenameAs;
121 MCPhysReg AliasRegID;
223 unsigned isAvailable(ArrayRef<MCPhysReg> Regs) const;
include/llvm/MCA/Instruction.h 46 MCPhysReg RegisterID;
74 MCPhysReg RegisterID;
89 MCPhysReg RegID;
110 MCPhysReg RegisterID;
150 WriteState(const WriteDescriptor &Desc, MCPhysReg RegID,
162 MCPhysReg getRegisterID() const { return RegisterID; }
204 void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
230 MCPhysReg RegisterID;
257 ReadState(const ReadDescriptor &Desc, MCPhysReg RegID)
264 MCPhysReg getRegisterID() const { return RegisterID; }
276 void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
lib/CodeGen/AggressiveAntiDepBreaker.cpp 177 for (const MCPhysReg *I = MF.getRegInfo().getCalleeSavedRegs(); *I;
632 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC);
lib/CodeGen/AllocationOrder.h 30 SmallVector<MCPhysReg, 16> Hints;
31 ArrayRef<MCPhysReg> Order;
49 ArrayRef<MCPhysReg> getOrder() const { return Order; }
lib/CodeGen/BranchFolding.cpp 438 MCPhysReg Reg = P.PhysReg;
lib/CodeGen/BreakFalseDeps.cpp 144 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC);
145 for (MCPhysReg Reg : Order) {
lib/CodeGen/CallingConvLower.cpp 199 void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs,
248 SmallVector<MCPhysReg, 8> RemainingRegs;
252 for (MCPhysReg PReg : RemainingRegs) {
lib/CodeGen/CriticalAntiDepBreaker.cpp 87 for (const MCPhysReg *I = MF.getRegInfo().getCalleeSavedRegs(); *I;
397 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC);
lib/CodeGen/IfConversion.cpp 1480 SparseSet<MCPhysReg, identity<MCPhysReg>> LiveBeforeMI;
1480 SparseSet<MCPhysReg, identity<MCPhysReg>> LiveBeforeMI;
1485 SmallVector<std::pair<MCPhysReg, const MachineOperand*>, 4> Clobbers;
1859 SmallVector<std::pair<MCPhysReg, const MachineOperand*>, 4> Dummy;
1938 SmallSet<MCPhysReg, 4> RedefsByFalse;
1939 SmallSet<MCPhysReg, 4> ExtUses;
1944 SmallVector<MCPhysReg, 4> Defs;
1962 for (MCPhysReg Reg : Defs) {
2108 SmallSet<MCPhysReg, 4> &LaterRedefs) {
lib/CodeGen/LivePhysRegs.cpp 31 SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> *Clobbers) {
85 SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> &Clobbers) {
144 MCPhysReg Reg) const {
159 MCPhysReg Reg = LI.PhysReg;
179 for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR; ++CSR)
207 for (MCPhysReg R : Pristine)
262 for (MCPhysReg Reg : LiveRegs) {
lib/CodeGen/LiveRegUnits.cpp 95 for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR; ++CSR)
lib/CodeGen/MIRParser/MIParser.cpp 1106 for (const MCPhysReg *ImpDefs = MCID.getImplicitDefs(); *ImpDefs; ++ImpDefs)
1110 for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses; ++ImpUses)
lib/CodeGen/MIRParser/MIRParser.cpp 561 SmallVector<MCPhysReg, 16> CalleeSavedRegisters;
lib/CodeGen/MIRPrinter.cpp 316 const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
318 for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
lib/CodeGen/MachineBasicBlock.cpp 448 void MachineBasicBlock::removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) {
466 bool MachineBasicBlock::isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) const {
lib/CodeGen/MachineFrameInfo.cpp 124 for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR;
lib/CodeGen/MachineInstr.cpp 104 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
108 for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
lib/CodeGen/MachineRegisterInfo.cpp 620 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
621 for (const MCPhysReg *I = CSR; *I; ++I)
637 const MCPhysReg *MachineRegisterInfo::getCalleeSavedRegs() const {
644 void MachineRegisterInfo::setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs) {
648 for (MCPhysReg Reg : CSRs)
lib/CodeGen/MachineVerifier.cpp 255 void report_context(MCPhysReg PhysReg) const;
546 void MachineVerifier::report_context(MCPhysReg PReg) const {
lib/CodeGen/PrologEpilogInserter.cpp 388 const MCPhysReg *CSRegs = F.getRegInfo().getCalleeSavedRegs();
508 MCPhysReg Reg = CSI[i].getReg();
523 MCPhysReg DstReg = CSI[i].getDstReg();
lib/CodeGen/ReachingDefAnalysis.cpp 192 int ReachingDefAnalysis::getClearance(MachineInstr *MI, MCPhysReg PhysReg) {
lib/CodeGen/RegAllocFast.cpp 86 MCPhysReg PhysReg = 0; ///< Currently held here.
139 void setPhysRegState(MCPhysReg PhysReg, unsigned NewState);
142 void markRegUsedInInstr(MCPhysReg PhysReg) {
148 bool isRegUsedInInstr(MCPhysReg PhysReg) const {
199 unsigned calcSpillCost(MCPhysReg PhysReg) const;
200 void assignVirtToPhysReg(LiveReg &, MCPhysReg PhysReg);
212 MCPhysReg defineVirtReg(MachineInstr &MI, unsigned OpNum, unsigned VirtReg,
217 bool setPhysReg(MachineInstr &MI, MachineOperand &MO, MCPhysReg PhysReg);
241 void RegAllocFast::setPhysRegState(MCPhysReg PhysReg, unsigned NewState) {
479 MCPhysReg Alias = *AI;
538 MCPhysReg Alias = *AI;
559 unsigned RegAllocFast::calcSpillCost(MCPhysReg PhysReg) const {
586 MCPhysReg Alias = *AI;
610 void RegAllocFast::assignVirtToPhysReg(LiveReg &LR, MCPhysReg PhysReg) {
713 MCPhysReg BestReg = 0;
715 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC);
716 for (MCPhysReg PhysReg : AllocationOrder) {
757 MCPhysReg PhysReg;
762 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC);
777 MCPhysReg RegAllocFast::defineVirtReg(MachineInstr &MI, unsigned OpNum,
856 MCPhysReg PhysReg) {
931 MCPhysReg PhysReg = LR.PhysReg;
954 MCPhysReg PhysReg = defineVirtReg(MI, I, Reg, 0);
1112 MCPhysReg PhysReg = LR.PhysReg;
1187 MCPhysReg PhysReg = defineVirtReg(MI, I, Reg, CopySrcReg);
lib/CodeGen/RegAllocPBQP.cpp 570 const MCPhysReg *CSR = MF.getRegInfo().getCalleeSavedRegs();
612 ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF);
757 const ArrayRef<MCPhysReg> RawPRegOrder = RC.getRawAllocationOrder(MF);
lib/CodeGen/RegUsageInfoCollector.cpp 148 for (const MCPhysReg Reg : TRI->getIntraCallClobberedRegs(&MF))
207 const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
209 MCPhysReg Reg = CSRegs[i];
lib/CodeGen/RegisterClassInfo.cpp 58 const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs();
63 for (const MCPhysReg *I = CSR; *I; ++I)
99 RCI.Order.reset(new MCPhysReg[NumRegs]);
102 SmallVector<MCPhysReg, 16> CSRAlias;
109 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
lib/CodeGen/RegisterScavenging.cpp 377 static std::pair<MCPhysReg, MachineBasicBlock::iterator>
383 MCPhysReg Survivor = 0;
398 for (MCPhysReg Reg : AllocationOrder) {
415 MCPhysReg AvilableReg = 0;
416 for (MCPhysReg Reg : AllocationOrder) {
588 ArrayRef<MCPhysReg> AllocationOrder = RC.getRawAllocationOrder(MF);
589 std::pair<MCPhysReg, MachineBasicBlock::iterator> P =
592 MCPhysReg Reg = P.first;
lib/CodeGen/SelectionDAG/FastISel.cpp 830 const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
1010 const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 813 const MCPhysReg *ScratchRegs = nullptr;
lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp 435 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
514 for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg) {
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp 1286 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
1427 for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg)
2841 const MCPhysReg *ImpDefs
2859 for (const MCPhysReg *ImpDef = ImpDefs; *ImpDef; ++ImpDef)
2878 const MCPhysReg *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs();
2884 const MCPhysReg *SUImpDefs =
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 1242 MCPhysReg EHPhysReg = TLI->getExceptionPointerRegister(PersonalityFn);
lib/CodeGen/TargetFrameLoweringImpl.cpp 94 const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs();
lib/CodeGen/TargetRegisterInfo.cpp 65 ArrayRef<MCPhysReg> Exceptions) const {
212 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF);
384 ArrayRef<MCPhysReg> Order,
385 SmallVectorImpl<MCPhysReg> &Hints,
lib/CodeGen/VirtRegMap.cpp 83 void VirtRegMap::assignVirt2Phys(Register virtReg, MCPhysReg physReg) {
lib/MC/MCInstrDesc.cpp 46 if (const MCPhysReg *ImpDefs = ImplicitDefs)
lib/MC/MCParser/AsmParser.cpp 5855 ArrayRef<MCPhysReg> ImpDefs(Desc.getImplicitDefs(),
lib/MCA/HardwareUnits/RegisterFile.cpp 89 for (const MCPhysReg Reg : RC) {
150 MCPhysReg RegID = WS.getRegisterID();
197 MCPhysReg ZeroRegisterID =
250 MCPhysReg RegID = WS.getRegisterID();
258 MCPhysReg RenameAs = RegisterMappings[RegID].second.RenameAs;
334 MCPhysReg AliasedReg =
336 MCPhysReg AliasReg = RRITo.RenameAs ? RRITo.RenameAs : WS.getRegisterID();
358 MCPhysReg RegID = RS.getRegisterID();
400 MCPhysReg RegID = RS.getRegisterID();
427 unsigned RegisterFile::isAvailable(ArrayRef<MCPhysReg> Regs) const {
431 for (const MCPhysReg RegID : Regs) {
lib/MCA/InstrBuilder.cpp 632 MCPhysReg RegID = 0;
lib/MCA/Instruction.cpp 21 void WriteState::writeStartEvent(unsigned IID, MCPhysReg RegID,
30 void ReadState::writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles) {
lib/MCA/Stages/DispatchStage.cpp 47 SmallVector<MCPhysReg, 4> RegDefs;
lib/Target/AArch64/AArch64CallingConvention.cpp 23 static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
26 static const MCPhysReg HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2,
29 static const MCPhysReg SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2,
32 static const MCPhysReg DRegList[] = {AArch64::D0, AArch64::D1, AArch64::D2,
35 static const MCPhysReg QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
90 ArrayRef<MCPhysReg> RegList;
lib/Target/AArch64/AArch64CollectLOH.cpp 260 static int mapRegToGPRIndex(MCPhysReg Reg) {
454 static void handleRegMaskClobber(const uint32_t *RegMask, MCPhysReg Reg,
468 for (MCPhysReg Reg : AArch64::GPR32RegClass)
470 for (MCPhysReg Reg : AArch64::GPR64RegClass)
lib/Target/AArch64/AArch64FastISel.cpp 3006 static const MCPhysReg Registers[6][8] = {
lib/Target/AArch64/AArch64FrameLowering.cpp 395 const MCPhysReg *CSRegs = MF->getRegInfo().getCalleeSavedRegs();
2189 const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs();
lib/Target/AArch64/AArch64ISelLowering.cpp 3403 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
3441 static const MCPhysReg FPRArgRegs[] = {
4252 const MCPhysReg *I =
9205 const MCPhysReg *
9210 static const MCPhysReg ScratchRegs[] = {
12378 const MCPhysReg *IStart = TRI->getCalleeSavedRegsViaCopy(Entry->getParent());
12385 for (const MCPhysReg *I = IStart; *I; ++I) {
lib/Target/AArch64/AArch64ISelLowering.h 401 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
lib/Target/AArch64/AArch64RedundantCopyElimination.cpp 88 MCPhysReg Reg;
90 RegImm(MCPhysReg Reg, int32_t Imm) : Reg(Reg), Imm(Imm) {}
186 MCPhysReg DstReg = PredI.getOperand(0).getReg();
187 MCPhysReg SrcReg = PredI.getOperand(1).getReg();
252 MCPhysReg DstReg = PredI.getOperand(0).getReg();
324 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg();
325 MCPhysReg CopySrcReg = PredI->getOperand(1).getReg();
405 MCPhysReg CmpReg = KnownReg.Reg;
454 for (MCPhysReg KnownReg : UsedKnownRegs)
lib/Target/AArch64/AArch64RegisterInfo.cpp 43 const MCPhysReg *
74 const MCPhysReg *AArch64RegisterInfo::getCalleeSavedRegsViaCopy(
85 const MCPhysReg *CSRs = getCalleeSavedRegs(&MF);
86 SmallVector<MCPhysReg, 32> UpdatedCSRs;
87 for (const MCPhysReg *I = CSRs; *I; ++I)
lib/Target/AArch64/AArch64RegisterInfo.h 46 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
47 const MCPhysReg *
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp 63 MCPhysReg Reg;
lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp 653 MCPhysReg HighestVGPRReg = AMDGPU::NoRegister;
654 for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
662 MCPhysReg HighestAGPRReg = AMDGPU::NoRegister;
663 for (MCPhysReg Reg : reverse(AMDGPU::AGPR_32RegClass.getRegisters())) {
673 MCPhysReg HighestSGPRReg = AMDGPU::NoRegister;
674 for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {
lib/Target/AMDGPU/AMDGPURegisterInfo.cpp 95 const MCPhysReg *SIRegisterInfo::getCalleeSavedRegs(
105 static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister;
111 const MCPhysReg *
lib/Target/AMDGPU/GCNNSAReassign.cpp 83 const MCPhysReg *CSRegs;
lib/Target/AMDGPU/GCNRegBankReassign.cpp 161 const MCPhysReg *CSRegs;
lib/Target/AMDGPU/R600RegisterInfo.cpp 63 static const MCPhysReg CalleeSavedReg = R600::NoRegister;
65 const MCPhysReg *R600RegisterInfo::getCalleeSavedRegs(
lib/Target/AMDGPU/R600RegisterInfo.h 28 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
lib/Target/AMDGPU/SIFrameLowering.cpp 27 static ArrayRef<MCPhysReg> getAllSGPR128(const GCNSubtarget &ST,
33 static ArrayRef<MCPhysReg> getAllSGPRs(const GCNSubtarget &ST,
55 const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs();
82 static MCPhysReg findUnusedSGPRNonCalleeSaved(MachineRegisterInfo &MRI) {
120 MCPhysReg OffsetReg = findScratchNonCalleeSaveRegister(
167 MCPhysReg OffsetReg = findScratchNonCalleeSaveRegister(
299 ArrayRef<MCPhysReg> AllSGPR128s = getAllSGPR128(ST, MF);
304 for (MCPhysReg Reg : AllSGPR128s) {
338 ArrayRef<MCPhysReg> AllSGPRs = getAllSGPRs(ST, MF);
367 for (MCPhysReg Reg : AllSGPRs.drop_back(ReservedRegCount)) {
lib/Target/AMDGPU/SIISelLowering.cpp 1654 ArrayRef<MCPhysReg> ArgVGPRs
1677 ArrayRef<MCPhysReg> ArgSGPRs = makeArrayRef(RC->begin(), 32);
1987 const MCPhysReg *IStart = TRI->getCalleeSavedRegsViaCopy(Entry->getParent());
1994 for (const MCPhysReg *I = IStart; *I; ++I) {
2343 const MCPhysReg *I =
lib/Target/AMDGPU/SILowerSGPRSpills.cpp 203 const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs();
307 for (MCPhysReg Reg : FuncInfo->getVGPRSpillAGPRs())
310 for (MCPhysReg Reg : FuncInfo->getAGPRSpillVGPRs())
lib/Target/AMDGPU/SIMachineFunctionInfo.cpp 240 static bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) {
240 static bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) {
281 const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs();
363 for (MCPhysReg Reg : SpillAGPR)
365 for (MCPhysReg Reg : SpillVGPR)
368 SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
409 MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
414 MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
lib/Target/AMDGPU/SIMachineFunctionInfo.h 421 MCPhysReg getNextUserSGPR() const;
423 MCPhysReg getNextSystemSGPR() const;
449 SmallVector<MCPhysReg, 32> Lanes;
470 SmallVector<MCPhysReg, 32> SpillAGPR;
473 SmallVector<MCPhysReg, 32> SpillVGPR;
496 ArrayRef<MCPhysReg> getAGPRSpillVGPRs() const {
500 ArrayRef<MCPhysReg> getVGPRSpillAGPRs() const {
504 MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const {
lib/Target/AMDGPU/SIRegisterInfo.cpp 254 for (MCPhysReg Reg : MFI->getAGPRSpillVGPRs())
257 for (MCPhysReg Reg : MFI->getVGPRSpillAGPRs())
554 MCPhysReg Reg = MFI->getVGPRToAGPRSpill(Index, Lane);
lib/Target/AMDGPU/SIRegisterInfo.h 60 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
61 const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
lib/Target/ARC/ARCISelLowering.cpp 521 static const MCPhysReg ArgRegs[] = {ARC::R0, ARC::R1, ARC::R2, ARC::R3,
lib/Target/ARC/ARCRegisterInfo.cpp 134 const MCPhysReg *
lib/Target/ARC/ARCRegisterInfo.h 31 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
lib/Target/ARM/ARMBaseInstrInfo.cpp 2464 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
lib/Target/ARM/ARMBaseRegisterInfo.cpp 64 const MCPhysReg*
68 const MCPhysReg *RegList =
112 const MCPhysReg *ARMBaseRegisterInfo::getCalleeSavedRegsViaCopy(
180 ArrayRef<MCPhysReg> ARMBaseRegisterInfo::getIntraCallClobberedRegs(
182 static const MCPhysReg IntraCallClobberedRegs[] = {ARM::R12};
302 ArrayRef<MCPhysReg> Order,
303 SmallVectorImpl<MCPhysReg> &Hints,
lib/Target/ARM/ARMBaseRegisterInfo.h 90 const MCPhysReg *CSRegs) {
112 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
113 const MCPhysReg *
132 ArrayRef<MCPhysReg>
153 ArrayRef<MCPhysReg> Order,
154 SmallVectorImpl<MCPhysReg> &Hints,
lib/Target/ARM/ARMCallingConv.cpp 24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
67 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
68 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
69 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 };
70 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
119 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
120 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
156 static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
158 static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
162 static const MCPhysReg DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
164 static const MCPhysReg QRegList[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 };
199 ArrayRef<MCPhysReg> RegList;
lib/Target/ARM/ARMConstantIslandPass.cpp 926 for (MCPhysReg L : LRs)
lib/Target/ARM/ARMFastISel.cpp 3051 static const MCPhysReg GPRArgRegs[] = {
lib/Target/ARM/ARMFrameLowering.cpp 146 const MCPhysReg *CSRegs) {
799 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
1704 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
lib/Target/ARM/ARMISelLowering.cpp 146 static const MCPhysReg GPRArgRegs[] = {
2834 const MCPhysReg *I =
9812 const MCPhysReg *SavedRegs = RI.getCalleeSavedRegs(MF);
17099 const MCPhysReg *IStart = TRI->getCalleeSavedRegsViaCopy(Entry->getParent());
17106 for (const MCPhysReg *I = IStart; *I; ++I) {
lib/Target/ARM/Thumb1FrameLowering.cpp 455 static bool isCSRestore(MachineInstr &MI, const MCPhysReg *CSRegs) {
485 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
659 const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
lib/Target/ARM/Thumb2SizeReduction.cpp 255 for (const MCPhysReg *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
lib/Target/AVR/AVRISelLowering.cpp 939 static const MCPhysReg RegList8[] = {AVR::R24, AVR::R22, AVR::R20,
942 static const MCPhysReg RegList16[] = {AVR::R25R24, AVR::R23R22, AVR::R21R20,
979 const MCPhysReg *RegList = (LocVT == MVT::i16) ? RegList16 : RegList8;
lib/Target/BPF/BPFRegisterInfo.cpp 32 const MCPhysReg *
lib/Target/BPF/BPFRegisterInfo.h 27 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp 523 ArrayRef<MCPhysReg> Table) {
541 static const MCPhysReg IntRegDecoderTable[] = {
557 static const MCPhysReg GeneralSubRegDecoderTable[] = {
570 static const MCPhysReg HvxVRDecoderTable[] = {
585 static const MCPhysReg DoubleRegDecoderTable[] = {
596 static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = {
606 static const MCPhysReg HvxWRDecoderTable[] = {
620 static const MCPhysReg HvxVQRDecoderTable[] = {
630 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
639 static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
650 static const MCPhysReg CtrlRegDecoderTable[] = {
678 static const MCPhysReg CtrlReg64DecoderTable[] = {
758 static const MCPhysReg GuestRegDecoderTable[] = {
784 static const MCPhysReg GuestReg64DecoderTable[] = {
lib/Target/Hexagon/HexagonFrameLowering.cpp 436 for (const MCPhysReg *P = HRI.getCalleeSavedRegs(&MF); *P; ++P)
1408 for (const MCPhysReg *P = HRI.getCallerSavedRegs(&MF, RC); *P; ++P)
1741 SmallVector<std::pair<MCPhysReg, const MachineOperand*>,2> Clobbers;
1939 for (const MCPhysReg *R = HRI.getCalleeSavedRegs(&MF); *R; ++R)
lib/Target/Hexagon/HexagonGenMux.cpp 163 if (const MCPhysReg *R = D.ImplicitDefs)
166 if (const MCPhysReg *R = D.ImplicitUses)
lib/Target/Hexagon/HexagonISelLowering.cpp 134 static const MCPhysReg ArgRegs[] = {
lib/Target/Hexagon/HexagonRegisterInfo.cpp 54 const MCPhysReg *
59 static const MCPhysReg Int32[] = {
62 static const MCPhysReg Int64[] = {
65 static const MCPhysReg Pred[] = {
68 static const MCPhysReg VecSgl[] = {
73 static const MCPhysReg VecDbl[] = {
92 static const MCPhysReg Empty[] = { 0 };
101 const MCPhysReg *
103 static const MCPhysReg CalleeSavedRegsV3[] = {
111 static const MCPhysReg CalleeSavedRegsV3EHReturn[] = {
lib/Target/Hexagon/HexagonRegisterInfo.h 34 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF)
76 const MCPhysReg *getCallerSavedRegs(const MachineFunction *MF,
lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp 99 if (const MCPhysReg *ImpDef = MCID.getImplicitDefs())
lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp 655 for (const MCPhysReg *U = D.getImplicitUses(); U && *U; ++U)
lib/Target/Hexagon/RDFGraph.cpp 637 const MCPhysReg *ImpR = Op.isDef() ? D.getImplicitDefs()
lib/Target/Hexagon/RDFRegisters.cpp 34 for (MCPhysReg R : *RC) {
lib/Target/MSP430/MSP430ISelLowering.cpp 443 static const MCPhysReg CRegList[] = {
447 static const MCPhysReg BuiltinRegList[] = {
453 ArrayRef<MCPhysReg> RegList;
lib/Target/MSP430/MSP430RegisterInfo.cpp 37 const MCPhysReg*
41 static const MCPhysReg CalleeSavedRegs[] = {
46 static const MCPhysReg CalleeSavedRegsFP[] = {
51 static const MCPhysReg CalleeSavedRegsIntr[] = {
57 static const MCPhysReg CalleeSavedRegsIntrFP[] = {
lib/Target/MSP430/MSP430RegisterInfo.h 28 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp 25 static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
27 static const MCPhysReg Mips64IntRegs[8] = {
32 ArrayRef<MCPhysReg> MipsABIInfo::GetByValArgRegs() const {
40 ArrayRef<MCPhysReg> MipsABIInfo::GetVarArgRegs() const {
lib/Target/Mips/MCTargetDesc/MipsABIInfo.h 47 ArrayRef<MCPhysReg> GetByValArgRegs() const;
50 ArrayRef<MCPhysReg> GetVarArgRegs() const;
lib/Target/Mips/MipsCallLowering.cpp 501 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
lib/Target/Mips/MipsDelaySlotFiller.cpp 383 for (const MCPhysReg *R = TRI.getCalleeSavedRegs(MI.getParent()->getParent());
lib/Target/Mips/MipsFastISel.cpp 1334 std::array<MCPhysReg, 4> GPR32ArgRegs = {{Mips::A0, Mips::A1, Mips::A2,
1336 std::array<MCPhysReg, 2> FGR32ArgRegs = {{Mips::F12, Mips::F14}};
1337 std::array<MCPhysReg, 2> AFGR64ArgRegs = {{Mips::D6, Mips::D7}};
lib/Target/Mips/MipsFrameLowering.cpp 126 for (const MCPhysReg *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) {
lib/Target/Mips/MipsISelLowering.cpp 92 static const MCPhysReg Mips64DPRegs[8] = {
2739 CCState &State, ArrayRef<MCPhysReg> F64Regs) {
2743 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2747 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2749 static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 };
2851 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2859 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
4186 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs();
4242 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs();
4326 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
4382 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs();
4384 const MCPhysReg *ShadowRegs =
lib/Target/Mips/MipsRegisterInfo.cpp 92 const MCPhysReg *
151 static const MCPhysReg ReservedGPR32[] = {
155 static const MCPhysReg ReservedGPR64[] = {
183 for (MCPhysReg Reg : Mips::AFGR64RegClass)
187 for (MCPhysReg Reg : Mips::FGR64RegClass)
220 for (MCPhysReg Reg : Mips::MSACtrlRegClass)
lib/Target/Mips/MipsRegisterInfo.h 52 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
lib/Target/NVPTX/NVPTXRegisterInfo.cpp 101 const MCPhysReg *
103 static const MCPhysReg CalleeSavedRegs[] = { 0 };
lib/Target/NVPTX/NVPTXRegisterInfo.h 37 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp 77 const MCPhysReg (&Regs)[N]) {
lib/Target/PowerPC/PPCCallingConv.cpp 36 static const MCPhysReg ArgRegs[] = {
61 static const MCPhysReg ArgRegs[] = {
86 static const MCPhysReg ArgRegs[] = {
114 static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 };
115 static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 };
143 static const MCPhysReg HiRegList[] = { PPC::R3 };
144 static const MCPhysReg LoRegList[] = { PPC::R4 };
lib/Target/PowerPC/PPCExpandISEL.cpp 394 SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 2> Clobbers;
lib/Target/PowerPC/PPCFrameLowering.cpp 42 static const MCPhysReg VRRegNo[] = {
660 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(MBB->getParent());
2147 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
lib/Target/PowerPC/PPCISelLowering.cpp 3266 static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
3271 static const MCPhysReg QFPR[] = {
3600 static const MCPhysReg GPArgRegs[] = {
3606 static const MCPhysReg FPArgRegs[] = {
3712 static const MCPhysReg GPR[] = {
3716 static const MCPhysReg VR[] = {
4123 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4127 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4131 static const MCPhysReg VR[] = {
4142 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4550 static const MCPhysReg GPR[] = {
4554 static const MCPhysReg VR[] = {
5707 static const MCPhysReg GPR[] = {
5711 static const MCPhysReg VR[] = {
6435 static const MCPhysReg GPR_32[] = { // 32-bit registers.
6439 static const MCPhysReg GPR_64[] = { // 64-bit registers.
6443 static const MCPhysReg VR[] = {
6451 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
6728 static const MCPhysReg GPR_32[] = {// 32-bit registers.
6731 static const MCPhysReg GPR_64[] = {// 64-bit registers.
6943 const MCPhysReg *I =
14965 const MCPhysReg *
14971 static const MCPhysReg ScratchRegs[] = {
15027 const MCPhysReg *IStart = TRI->getCalleeSavedRegsViaCopy(Entry->getParent());
15034 for (const MCPhysReg *I = IStart; *I; ++I) {
lib/Target/PowerPC/PPCISelLowering.h 908 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
lib/Target/PowerPC/PPCInstrInfo.cpp 1980 for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
1986 for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
lib/Target/PowerPC/PPCRegisterInfo.cpp 141 const MCPhysReg*
197 const MCPhysReg *
lib/Target/PowerPC/PPCRegisterInfo.h 86 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
87 const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
lib/Target/RISCV/RISCVFrameLowering.cpp 389 static const MCPhysReg CSRegs[] = { RISCV::X1, /* ra */
403 const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs();
lib/Target/RISCV/RISCVISelLowering.cpp 1395 static const MCPhysReg ArgGPRs[] = {
1399 static const MCPhysReg ArgFPR32s[] = {
1403 static const MCPhysReg ArgFPR64s[] = {
1815 static const MCPhysReg GPRList[] = {
1826 static const MCPhysReg FPR32List[] = {
1838 static const MCPhysReg FPR64List[] = {
1944 ArrayRef<MCPhysReg> ArgRegs = makeArrayRef(ArgGPRs);
lib/Target/RISCV/RISCVRegisterInfo.cpp 42 const MCPhysReg *
lib/Target/RISCV/RISCVRegisterInfo.h 30 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
lib/Target/Sparc/AsmParser/SparcAsmParser.cpp 128 static const MCPhysReg IntRegs[32] = {
138 static const MCPhysReg FloatRegs[32] = {
148 static const MCPhysReg DoubleRegs[32] = {
158 static const MCPhysReg QuadFPRegs[32] = {
164 static const MCPhysReg ASRRegs[32] = {
174 static const MCPhysReg IntPairRegs[] = {
180 static const MCPhysReg CoprocRegs[32] = {
190 static const MCPhysReg CoprocPairRegs[] = {
lib/Target/Sparc/SparcISelLowering.cpp 58 static const MCPhysReg RegList[] = {
86 static const MCPhysReg RegList[] = {
536 static const MCPhysReg ArgRegs[] = {
540 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
lib/Target/Sparc/SparcRegisterInfo.cpp 38 const MCPhysReg*
lib/Target/Sparc/SparcRegisterInfo.h 26 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
lib/Target/SystemZ/SystemZCallingConv.cpp 14 const MCPhysReg SystemZ::ArgGPRs[SystemZ::NumArgGPRs] = {
18 const MCPhysReg SystemZ::ArgFPRs[SystemZ::NumArgFPRs] = {
lib/Target/SystemZ/SystemZCallingConv.h 19 extern const MCPhysReg ArgGPRs[NumArgGPRs];
22 extern const MCPhysReg ArgFPRs[NumArgFPRs];
lib/Target/SystemZ/SystemZFrameLowering.cpp 103 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
lib/Target/SystemZ/SystemZISelLowering.cpp 1203 const MCPhysReg *SystemZTargetLowering::getScratchRegisters(
1205 static const MCPhysReg ScratchRegs[] = { SystemZ::R0D, SystemZ::R1D,
lib/Target/SystemZ/SystemZISelLowering.h 484 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
lib/Target/SystemZ/SystemZRegisterInfo.cpp 59 static void addHints(ArrayRef<MCPhysReg> Order,
60 SmallVectorImpl<MCPhysReg> &Hints,
66 for (MCPhysReg Reg : Order)
70 for (MCPhysReg Reg : Order)
78 ArrayRef<MCPhysReg> Order,
79 SmallVectorImpl<MCPhysReg> &Hints,
188 for (MCPhysReg OrderReg : Order)
195 const MCPhysReg *
lib/Target/SystemZ/SystemZRegisterInfo.h 62 ArrayRef<MCPhysReg> Order,
63 SmallVectorImpl<MCPhysReg> &Hints,
78 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp 38 const MCPhysReg *
40 static const MCPhysReg CalleeSavedRegs[] = {0};
lib/Target/WebAssembly/WebAssemblyRegisterInfo.h 35 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
lib/Target/X86/AsmParser/X86AsmParser.cpp 3772 for (MCPhysReg Reg : X86MCRegisterClasses[RegClassID]) {
lib/Target/X86/Disassembler/X86Disassembler.cpp 270 static constexpr MCPhysReg llvmRegnums[] = {ALL_REGS};
273 MCPhysReg llvmRegnum = llvmRegnums[reg];
lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp 678 static const MCPhysReg CU32BitRegs[7] = {
681 static const MCPhysReg CU64BitRegs[] = {
684 const MCPhysReg *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp 87 MCPhysReg Reg;
459 const MCPhysReg Reg = Desc.getImplicitDefs()[I];
lib/Target/X86/X86CallLowering.cpp 165 static const MCPhysReg XMMArgRegs[] = {X86::XMM0, X86::XMM1, X86::XMM2,
lib/Target/X86/X86CallingConv.cpp 33 static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI,
67 static ArrayRef<MCPhysReg> CC_X86_VectorCallGetSSEs(const MVT &ValVT) {
69 static const MCPhysReg RegListZMM[] = {X86::ZMM0, X86::ZMM1, X86::ZMM2,
75 static const MCPhysReg RegListYMM[] = {X86::YMM0, X86::YMM1, X86::YMM2,
80 static const MCPhysReg RegListXMM[] = {X86::XMM0, X86::XMM1, X86::XMM2,
85 static ArrayRef<MCPhysReg> CC_X86_64_VectorCallGetGPRs() {
86 static const MCPhysReg RegListGPR[] = {X86::RCX, X86::RDX, X86::R8, X86::R9};
96 ArrayRef<MCPhysReg> RegList = CC_X86_VectorCallGetSSEs(ValVT);
242 static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX};
lib/Target/X86/X86FastISel.cpp 2947 static const MCPhysReg Reg[] = { X86::AL, X86::AX, X86::EAX, X86::RAX };
3117 static const MCPhysReg GPR32ArgRegs[] = {
3120 static const MCPhysReg GPR64ArgRegs[] = {
3123 static const MCPhysReg XMMArgRegs[] = {
3460 static const MCPhysReg XMMArgRegs[] = {
lib/Target/X86/X86FloatingPoint.cpp 129 MCPhysReg Reg = I->PhysReg;
lib/Target/X86/X86ISelLowering.cpp 2401 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2402 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2646 const MCPhysReg *I =
3117 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
3122 static const MCPhysReg GPR64ArgRegsWin64[] = {
3128 static const MCPhysReg GPR64ArgRegs64Bit[] = {
3135 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
3157 static const MCPhysReg XMMArgRegs64Bit[] = {
3361 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
3362 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
3372 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
3380 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
3891 static const MCPhysReg XMMArgRegs[] = {
31110 const MCPhysReg *SavedRegs = MF->getRegInfo().getCalleeSavedRegs();
46178 const MCPhysReg *IStart = TRI->getCalleeSavedRegsViaCopy(Entry->getParent());
46185 for (const MCPhysReg *I = IStart; *I; ++I) {
lib/Target/X86/X86ISelLowering.h 1405 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
lib/Target/X86/X86InstrInfo.cpp 2471 SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
lib/Target/X86/X86MachineFunctionInfo.cpp 23 for (const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs();
lib/Target/X86/X86RegisterInfo.cpp 279 const MCPhysReg *
399 const MCPhysReg *X86RegisterInfo::getCalleeSavedRegsViaCopy(
lib/Target/X86/X86RegisterInfo.h 104 const MCPhysReg *
106 const MCPhysReg *
lib/Target/X86/X86SelectionDAGInfo.cpp 27 SelectionDAG &DAG, ArrayRef<MCPhysReg> ClobberSet) const {
56 const MCPhysReg ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI,
302 const MCPhysReg ClobberSet[] = {X86::RCX, X86::RSI, X86::RDI,
lib/Target/X86/X86SelectionDAGInfo.h 29 ArrayRef<MCPhysReg> ClobberSet) const;
lib/Target/XCore/XCoreISelLowering.cpp 1345 static const MCPhysReg ArgRegs[] = {
lib/Target/XCore/XCoreRegisterInfo.cpp 209 const MCPhysReg *
213 static const MCPhysReg CalleeSavedRegs[] = {
218 static const MCPhysReg CalleeSavedRegsFP[] = {
lib/Target/XCore/XCoreRegisterInfo.h 31 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
tools/llvm-exegesis/lib/MCInstrDescView.cpp 115 for (const MCPhysReg *MCPhysReg = Description->getImplicitDefs();
124 for (const MCPhysReg *MCPhysReg = Description->getImplicitUses();
302 addOperandIfAlias(const MCPhysReg Reg, bool SelectDef,
334 for (const MCPhysReg Reg : CommonRegisters.set_bits()) {
tools/llvm-exegesis/lib/MCInstrDescView.h 89 const MCPhysReg *ImplicitReg = nullptr; // Set for Implicit Op.
164 RegisterOperandAssignment(const Operand *Operand, MCPhysReg Reg)
168 MCPhysReg Reg;
tools/llvm-exegesis/lib/RegisterAliasing.cpp 35 for (MCPhysReg PhysReg : RegClass)
42 const MCPhysReg PhysReg)
66 RegisterAliasingTrackerCache::getRegister(MCPhysReg PhysReg) const {
tools/llvm-exegesis/lib/RegisterAliasing.h 49 const MCPhysReg Register);
57 int getOrigin(MCPhysReg Aliased) const {
91 const RegisterAliasingTracker &getRegister(MCPhysReg Reg) const;
unittests/CodeGen/MachineInstrTest.cpp 61 const MCPhysReg *
unittests/tools/llvm-exegesis/X86/RegisterAliasingTest.cpp 31 std::set<MCPhysReg> ActualAliasedRegisters;
34 const std::set<MCPhysReg> ExpectedAliasedRegisters = {
37 for (MCPhysReg aliased : ExpectedAliasedRegisters) {