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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
include/llvm/CodeGen/MachineInstr.h 1120 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
1130 return isCopy() || isSubregToReg();
1135 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
include/llvm/CodeGen/TargetInstrInfo.h 939 if (MI.isCopy()) {
lib/CodeGen/CalcSpillWeights.cpp 245 if (!mi->isCopy())
lib/CodeGen/GlobalISel/RegisterBankInfo.cpp 151 return MI.isCopy() || MI.isPHI() ||
lib/CodeGen/InlineSpiller.cpp 451 if (!MI.isCopy() && !MI.mayStore())
798 bool WasCopy = MI->isCopy();
lib/CodeGen/LiveDebugVariables.cpp 776 if (MO.getSubReg() || !MI->isCopy())
823 assert(CopyMI && CopyMI->isCopy() && "Bad copy value");
lib/CodeGen/LiveRangeEdit.cpp 326 if ((MI->readsVirtualRegister(Reg) && (MI->isCopy() || MOI->isDef())) ||
lib/CodeGen/LiveRangeShrink.cpp 199 if (!DefInstr.isCopy())
lib/CodeGen/MIRCanonicalizerPass.cpp 312 if (MI.isCopy())
lib/CodeGen/MachineBasicBlock.cpp 507 for (;I != E && I->isCopy(); ++I)
lib/CodeGen/MachineCSE.cpp 175 if (!DefMI->isCopy())
lib/CodeGen/MachineCopyPropagation.cpp 120 assert(MI->isCopy() && "Tracking non-copy?");
302 assert(Copy.isCopy());
330 if (!UseI.isCopy())
469 if (MI->isCopy() && !TRI->regsOverlap(MI->getOperand(0).getReg(),
625 assert(MaybeDead->isCopy());
lib/CodeGen/MachineLICM.cpp 780 if (!MI.isCopy()) {
952 if (!MI.isCopy())
1081 if (UseMI.isCopy() && CurLoop->contains(&UseMI))
lib/CodeGen/MachinePipeliner.cpp 1290 if (!SU.getInstr()->isCopy() && !SU.getInstr()->isRegSequence())
lib/CodeGen/MachineScheduler.cpp 1824 if (!SU.getInstr()->isCopy())
2914 if (MI->isCopy()) {
3269 if (!Copy->isCopy() && !Copy->isMoveImmediate())
lib/CodeGen/MachineSink.cpp 203 if (!MI.isCopy())
428 if (!MI.isCopy() && !TII->isAsCheapAsAMove(MI))
965 if (MI.getMF()->getFunction().getSubprogram() && MI.isCopy())
985 assert(MI.isCopy());
1279 if (!MI->isCopy() || !MI->getOperand(0).isRenamable()) {
lib/CodeGen/OptimizePHIs.cpp 118 if (SrcMI && SrcMI->isCopy() && !SrcMI->getOperand(0).getSubReg() &&
lib/CodeGen/PeepholeOptimizer.cpp 239 return MI.isCopy() || (!DisableAdvCopyOpt &&
831 assert(MI.isCopy() && "Expected copy instruction");
1393 assert(MI.isCopy() && "expected a COPY machine instruction");
1440 assert(MI.isCopy() && "expected a COPY machine instruction");
1659 if (!MI->isCopy()) {
1722 if (MI->isCopy() &&
1808 assert(Def->isCopy() && "Invalid definition");
2056 if (Def->isCopy())
lib/CodeGen/RegAllocFast.cpp 1020 if (MI.isCopy()) {
lib/CodeGen/RegisterCoalescer.cpp 365 if (MI->isCopy()) {
886 if (!UseMI->isCopy())
3191 if (MI->isCopy()) {
3460 if (!Copy->isCopy())
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 617 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
1623 if (!MI.isCopy() && !MI.isImplicitDef())
lib/CodeGen/TailDuplicator.cpp 236 if (!Copy->isCopy())
lib/CodeGen/TargetInstrInfo.cpp 435 assert(MI.isCopy() && "MI must be a COPY instruction");
602 if (!MI.isCopy() || Ops.size() != 1)
lib/CodeGen/TargetRegisterInfo.cpp 503 if (MI->isCopy())
lib/CodeGen/TwoAddressInstructionPass.cpp 369 if (!Def || !Def->isCopy())
412 if (MI.isCopy()) {
886 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
932 if (End->isCopy() && regOverlapsSet(Defs, End->getOperand(1).getReg(), TRI))
1027 if (DefMI.getParent() != MBB || DefMI.isCopy() || DefMI.isCopyLike())
1076 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
lib/CodeGen/VirtRegMap.cpp 403 if (!MI.isCopy())
414 if (!I->isCopy())
lib/Target/AArch64/AArch64InstrInfo.cpp 3231 if (MI.isCopy() && Ops.size() == 1 &&
4793 while (DefMI->isCopy()) {
lib/Target/AArch64/AArch64InstructionSelector.cpp 674 assert((I.isCopy() ||
685 if (I.isCopy()) {
1359 if (I.isCopy())
lib/Target/AArch64/AArch64RedundantCopyElimination.cpp 323 if (PredI->isCopy()) {
379 bool IsCopy = MI->isCopy();
lib/Target/AArch64/AArch64StackTaggingPreRA.cpp 159 } else if (UseI->isCopy() &&
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 1678 if (I.isCopy())
lib/Target/AMDGPU/GCNNSAReassign.cpp 199 if (Def && Def->isCopy() && Def->getOperand(1).getReg() == PhysReg)
206 if (UseInst->isCopy() && UseInst->getOperand(0).getReg() == PhysReg)
lib/Target/AMDGPU/GCNRegBankReassign.cpp 430 if (Def && Def->isCopy() && Def->getOperand(1).getReg() == PhysReg)
437 if (UseInst->isCopy() && UseInst->getOperand(0).getReg() == PhysReg)
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 253 if (!CopyUse.isCopy())
770 AllAGPRUses &= (UseMI->isCopy() &&
773 if (UseMI->isCopy() || UseMI->isRegSequence()) {
774 if (UseMI->isCopy() &&
814 if (Def->isCopy()) {
824 else if (Def->isCopy() &&
lib/Target/AMDGPU/SIFixupVectorISel.cpp 121 if (!MI || !MI->isCopy())
133 if (!MI || !MI->isCopy())
lib/Target/AMDGPU/SIFoldOperands.cpp 612 if (FoldingImmLike && UseMI->isCopy()) {
669 if (UseMI->isCopy() && OpToFold.isReg() &&
lib/Target/AMDGPU/SIISelLowering.cpp10413 if (!Src || !Src->isCopy() ||
lib/Target/AMDGPU/SIInstrInfo.cpp 4304 while (!ImpDef && Def && Def->isCopy()) {
5065 if (Inst.isCopy() &&
lib/Target/AMDGPU/SIInstrInfo.h 671 assert(MI.isCopy());
728 if (MI.isCopy()) {
lib/Target/AMDGPU/SILowerControlFlow.cpp 459 !(I->isCopy() && I->getOperand(0).getReg() != Exec))
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 99 if (MI.isCopy() && MI.getOperand(1).getReg() == Exec) {
lib/Target/ARM/A15SDOptimizer.cpp 164 if (MI->isCopy() && usesRegClass(MI->getOperand(1),
243 if (MI->isCopy()) {
264 if (EC && EC->isCopy() &&
327 if (MI->isCopy() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
lib/Target/ARM/ARMBaseInstrInfo.cpp 1585 if (!MI.isCopy() || Subtarget.dontWidenVMOVS() || !Subtarget.hasFP64())
lib/Target/ARM/ARMInstructionSelector.cpp 845 if (I.isCopy())
lib/Target/ARM/MLxExpansionPass.cpp 126 while (UseMI->isCopy() || UseMI->isInsertSubreg()) {
336 if (MI->isPosition() || MI->isImplicitDef() || MI->isCopy())
lib/Target/Hexagon/HexagonBitSimplify.cpp 1219 if (UseI.isPHI() || UseI.isCopy()) {
lib/Target/Hexagon/HexagonBitTracker.cpp 233 if (MI.isCopy()) {
1218 assert(MI.isCopy());
lib/Target/Hexagon/HexagonConstPropagation.cpp 1932 if (MI.isCopy()) {
2811 if (!MI.isCopy()) {
2826 if (MI.isCopy())
lib/Target/Hexagon/HexagonGenInsert.cpp 948 bool Skip = MI->isCopy() || MI->isRegSequence();
lib/Target/Hexagon/HexagonHardwareLoops.cpp 1446 if (Def->isCopy() && !loopCountMayWrapOrUnderFlow(&(Def->getOperand(1)),
1491 if (!Def->isCopy() && !Def->isPHI())
lib/Target/Hexagon/HexagonPeephole.cpp 202 if (!DisableOptSZExt && MI.isCopy()) {
lib/Target/Hexagon/HexagonSubtarget.cpp 232 if (MI->isCopy() &&
242 if (MO.isUse() && !MI->isCopy() &&
341 if (DstInst->isCopy())
346 if ((DstInst->isRegSequence() || DstInst->isCopy()) && Dst->NumSuccs == 1) {
lib/Target/Mips/MipsInstructionSelector.cpp 236 if (I.isCopy())
lib/Target/PowerPC/PPCReduceCRLogicals.cpp 542 if (!Copy->isCopy())
618 if (CRI.TrueDefs.first->isCopy() || CRI.TrueDefs.second->isCopy() ||
618 if (CRI.TrueDefs.first->isCopy() || CRI.TrueDefs.second->isCopy() ||
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 562 if (MI->isCopy())
609 if (!(MI->isCopy() && isScalarVecReg(Reg)))
lib/Target/SystemZ/SystemZRegisterInfo.cpp 343 assert (MI->isCopy() && "Only expecting COPY instructions");
lib/Target/X86/X86CallFrameOptimization.cpp 394 if (J->isCopy() && J->getOperand(0).isReg() && J->getOperand(1).isReg() &&
lib/Target/X86/X86FloatingPoint.cpp 425 if (MI.isCopy() && isFPCopy(MI))
lib/Target/X86/X86InstrInfo.cpp 4994 if (PrintFailedFusing && !MI.isCopy())
lib/Target/X86/X86InstructionSelector.cpp 241 assert(I.isCopy() && "Generic operators do not allow physical registers");
267 assert((!Register::isPhysicalRegister(SrcReg) || I.isCopy()) &&
322 if (I.isCopy())