|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 6588 { 755, 5, 1, 4, 865, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #755 = MOVr
8584 { 2751, 4, 1, 4, 565, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2751 = VMOVD
8600 { 2767, 4, 1, 4, 574, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::Predicable), 0x18900ULL, nullptr, nullptr, OperandInfo379, -1 ,nullptr }, // Inst #2767 = VMOVRS
8601 { 2768, 4, 1, 4, 566, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #2768 = VMOVS
8602 { 2769, 4, 1, 4, 575, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::Predicable), 0x18a00ULL, nullptr, nullptr, OperandInfo380, -1 ,nullptr }, // Inst #2769 = VMOVSR
10009 { 4176, 2, 1, 2, 1016, 0|(1ULL<<MCID::MoveReg), 0xc80ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr }, // Inst #4176 = tMOVSr
10011 { 4178, 4, 1, 2, 1016, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #4178 = tMOVr
gen/lib/Target/Mips/MipsGenInstrInfo.inc 5760 { 945, 2, 1, 4, 686, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #945 = CFC1
5761 { 946, 2, 1, 4, 1282, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #946 = CFC1_MM
5763 { 948, 2, 1, 4, 524, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #948 = CFCMSA
5915 { 1100, 2, 1, 4, 677, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1100 = CTC1
5916 { 1101, 2, 1, 4, 1283, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1101 = CTC1_MM
5918 { 1103, 2, 0, 4, 524, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1103 = CTCMSA
6096 { 1281, 2, 1, 4, 1328, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1281 = DMFC1
6104 { 1289, 2, 1, 4, 1329, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1289 = DMTC1
6330 { 1515, 2, 1, 4, 530, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr }, // Inst #1515 = FMOV_D32
6332 { 1517, 2, 1, 4, 530, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1517 = FMOV_D64
6335 { 1520, 2, 1, 4, 531, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1520 = FMOV_S
6336 { 1521, 2, 1, 4, 1265, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1521 = FMOV_S_MM
6691 { 1876, 2, 1, 4, 687, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #1876 = MFC1
6692 { 1877, 2, 1, 4, 687, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #1877 = MFC1_D64
6693 { 1878, 2, 1, 4, 1255, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #1878 = MFC1_MM
6700 { 1885, 2, 1, 4, 688, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #1885 = MFHC1_D32
6701 { 1886, 2, 1, 4, 1256, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #1886 = MFHC1_D32_MM
6702 { 1887, 2, 1, 4, 688, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #1887 = MFHC1_D64
6703 { 1888, 2, 1, 4, 1256, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #1888 = MFHC1_D64_MM
6707 { 1892, 1, 1, 4, 473, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList19, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #1892 = MFHI
6708 { 1893, 1, 1, 2, 879, 0|(1ULL<<MCID::MoveReg), 0x0ULL, ImplicitList19, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #1893 = MFHI16_MM
6709 { 1894, 1, 1, 4, 898, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList20, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1894 = MFHI64
6710 { 1895, 2, 1, 4, 1386, 0|(1ULL<<MCID::MoveReg), 0x6ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1895 = MFHI_DSP
6712 { 1897, 1, 1, 4, 879, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList19, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #1897 = MFHI_MM
6713 { 1898, 1, 1, 4, 473, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList19, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #1898 = MFLO
6714 { 1899, 1, 1, 2, 879, 0|(1ULL<<MCID::MoveReg), 0x0ULL, ImplicitList19, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #1899 = MFLO16_MM
6715 { 1900, 1, 1, 4, 898, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList20, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1900 = MFLO64
6716 { 1901, 2, 1, 4, 1387, 0|(1ULL<<MCID::MoveReg), 0x6ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1901 = MFLO_DSP
6718 { 1903, 1, 1, 4, 879, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList19, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #1903 = MFLO_MM
6762 { 1947, 2, 1, 2, 742, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #1947 = MOVE16_MM
6763 { 1948, 2, 1, 2, 784, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #1948 = MOVE16_MMR6
6764 { 1949, 4, 2, 2, 743, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #1949 = MOVEP_MM
6765 { 1950, 4, 2, 2, 1549, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #1950 = MOVEP_MMR6
6766 { 1951, 2, 1, 4, 541, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #1951 = MOVE_V
6834 { 2019, 2, 1, 4, 678, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #2019 = MTC1
6835 { 2020, 2, 1, 4, 678, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #2020 = MTC1_D64
6836 { 2021, 2, 1, 4, 1257, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #2021 = MTC1_D64_MM
6837 { 2022, 2, 1, 4, 1257, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #2022 = MTC1_MM
6851 { 2036, 1, 0, 4, 488, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList21, OperandInfo49, -1 ,nullptr }, // Inst #2036 = MTHI
6852 { 2037, 1, 0, 4, 900, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList22, OperandInfo86, -1 ,nullptr }, // Inst #2037 = MTHI64
6853 { 2038, 2, 1, 4, 1343, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2038 = MTHI_DSP
6854 { 2039, 2, 1, 4, 1554, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2039 = MTHI_DSP_MM
6855 { 2040, 1, 0, 4, 882, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList21, OperandInfo49, -1 ,nullptr }, // Inst #2040 = MTHI_MM
6858 { 2043, 1, 0, 4, 488, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList23, OperandInfo49, -1 ,nullptr }, // Inst #2043 = MTLO
6859 { 2044, 1, 0, 4, 900, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList24, OperandInfo86, -1 ,nullptr }, // Inst #2044 = MTLO64
6860 { 2045, 2, 1, 4, 1344, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2045 = MTLO_DSP
6861 { 2046, 2, 1, 4, 1556, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2046 = MTLO_DSP_MM
6862 { 2047, 1, 0, 4, 882, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList23, OperandInfo49, -1 ,nullptr }, // Inst #2047 = MTLO_MM
6863 { 2048, 1, 0, 4, 1197, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList25, OperandInfo86, -1 ,nullptr }, // Inst #2048 = MTM0
6864 { 2049, 1, 0, 4, 1197, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList26, OperandInfo86, -1 ,nullptr }, // Inst #2049 = MTM1
6865 { 2050, 1, 0, 4, 1197, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList27, OperandInfo86, -1 ,nullptr }, // Inst #2050 = MTM2
6866 { 2051, 1, 0, 4, 1197, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList28, OperandInfo86, -1 ,nullptr }, // Inst #2051 = MTP0
6867 { 2052, 1, 0, 4, 1197, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList29, OperandInfo86, -1 ,nullptr }, // Inst #2052 = MTP1
6868 { 2053, 1, 0, 4, 1197, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList30, OperandInfo86, -1 ,nullptr }, // Inst #2053 = MTP2
6920 { 2105, 1, 1, 2, 727, 0|(1ULL<<MCID::MoveReg), 0x0ULL, ImplicitList21, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2105 = Mfhi16
6923 { 2108, 2, 1, 2, 727, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2108 = MoveR3216
7034 { 2219, 2, 1, 4, 1417, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #2219 = RDDSP
7227 { 2412, 2, 1, 4, 804, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2412 = SLL64_32
7228 { 2413, 2, 1, 4, 804, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #2413 = SLL64_64
7507 { 2692, 2, 0, 4, 1445, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #2692 = WRDSP
7508 { 2693, 2, 0, 4, 1611, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #2693 = WRDSP_MM
gen/lib/Target/X86/X86GenInstrInfo.inc18870 { 1182, 2, 1, 0, 1078, 0|(1ULL<<MCID::MoveReg), 0x2410002831ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1182 = KMOVBkk
18875 { 1187, 2, 1, 0, 1078, 0|(1ULL<<MCID::MoveReg), 0x6410002831ULL, nullptr, nullptr, OperandInfo214, -1 ,nullptr }, // Inst #1187 = KMOVDkk
18880 { 1192, 2, 1, 0, 1078, 0|(1ULL<<MCID::MoveReg), 0x6410002031ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr }, // Inst #1192 = KMOVQkk
18885 { 1197, 2, 1, 0, 1078, 0|(1ULL<<MCID::MoveReg), 0x2410002031ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1197 = KMOVWkk
19168 { 1480, 2, 1, 0, 192, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x1bc0002031ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #1480 = MMX_MOVQ64rr
19169 { 1481, 2, 1, 0, 192, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x1fc0002030ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #1481 = MMX_MOVQ64rr_REV
19343 { 1655, 2, 1, 0, 6, 0|(1ULL<<MCID::MoveReg), 0x22400000b0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1655 = MOV16rr
19344 { 1656, 2, 1, 0, 6, 0|(1ULL<<MCID::MoveReg), 0x22c00000b1ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1656 = MOV16rr_REV
19363 { 1675, 2, 1, 0, 6, 0|(1ULL<<MCID::MoveReg), 0x2240000130ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1675 = MOV32rr
19364 { 1676, 2, 1, 0, 6, 0|(1ULL<<MCID::MoveReg), 0x22c0000131ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1676 = MOV32rr_REV
19380 { 1692, 2, 1, 0, 6, 0|(1ULL<<MCID::MoveReg), 0x2240010030ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #1692 = MOV64rr
19381 { 1693, 2, 1, 0, 6, 0|(1ULL<<MCID::MoveReg), 0x22c0010031ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #1693 = MOV64rr_REV
19400 { 1712, 2, 1, 0, 6, 0|(1ULL<<MCID::MoveReg), 0x2200000030ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1712 = MOV8rr
19401 { 1713, 2, 1, 0, 6, 0|(1ULL<<MCID::MoveReg), 0x2200000030ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #1713 = MOV8rr_NOREX
19402 { 1714, 2, 1, 0, 6, 0|(1ULL<<MCID::MoveReg), 0x2280000031ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1714 = MOV8rr_REV
19405 { 1717, 2, 1, 0, 213, 0|(1ULL<<MCID::MoveReg), 0xa08002831ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1717 = MOVAPDrr
19406 { 1718, 2, 1, 0, 213, 0|(1ULL<<MCID::MoveReg), 0xa48002830ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1718 = MOVAPDrr_REV
19409 { 1721, 2, 1, 0, 213, 0|(1ULL<<MCID::MoveReg), 0xa04002031ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1721 = MOVAPSrr
19410 { 1722, 2, 1, 0, 213, 0|(1ULL<<MCID::MoveReg), 0xa44002030ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1722 = MOVAPSrr_REV
19505 { 1817, 2, 1, 0, 213, 0|(1ULL<<MCID::MoveReg), 0x408002831ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1817 = MOVUPDrr
19506 { 1818, 2, 1, 0, 213, 0|(1ULL<<MCID::MoveReg), 0x448002830ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1818 = MOVUPDrr_REV
19509 { 1821, 2, 1, 0, 213, 0|(1ULL<<MCID::MoveReg), 0x404002031ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1821 = MOVUPSrr
19510 { 1822, 2, 1, 0, 213, 0|(1ULL<<MCID::MoveReg), 0x444002030ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1822 = MOVUPSrr_REV
25265 { 7577, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x10a18002831ULL, nullptr, nullptr, OperandInfo501, -1 ,nullptr }, // Inst #7577 = VMOVAPDYrr
25266 { 7578, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x10a58002830ULL, nullptr, nullptr, OperandInfo501, -1 ,nullptr }, // Inst #7578 = VMOVAPDYrr_REV
25272 { 7584, 2, 1, 0, 213, 0|(1ULL<<MCID::MoveReg), 0x2004a38002831ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr }, // Inst #7584 = VMOVAPDZ128rr
25273 { 7585, 2, 1, 0, 213, 0|(1ULL<<MCID::MoveReg), 0x2004a78002830ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr }, // Inst #7585 = VMOVAPDZ128rr_REV
25283 { 7595, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x4014a38002831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7595 = VMOVAPDZ256rr
25284 { 7596, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x4014a78002830ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7596 = VMOVAPDZ256rr_REV
25294 { 7606, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x8084a38002831ULL, nullptr, nullptr, OperandInfo486, -1 ,nullptr }, // Inst #7606 = VMOVAPDZrr
25295 { 7607, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x8084a78002830ULL, nullptr, nullptr, OperandInfo486, -1 ,nullptr }, // Inst #7607 = VMOVAPDZrr_REV
25302 { 7614, 2, 1, 0, 213, 0|(1ULL<<MCID::MoveReg), 0xa18002831ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #7614 = VMOVAPDrr
25303 { 7615, 2, 1, 0, 213, 0|(1ULL<<MCID::MoveReg), 0xa58002830ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #7615 = VMOVAPDrr_REV
25306 { 7618, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x10a14002031ULL, nullptr, nullptr, OperandInfo501, -1 ,nullptr }, // Inst #7618 = VMOVAPSYrr
25307 { 7619, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x10a54002030ULL, nullptr, nullptr, OperandInfo501, -1 ,nullptr }, // Inst #7619 = VMOVAPSYrr_REV
25313 { 7625, 2, 1, 0, 213, 0|(1ULL<<MCID::MoveReg), 0x2000a34002031ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr }, // Inst #7625 = VMOVAPSZ128rr
25314 { 7626, 2, 1, 0, 213, 0|(1ULL<<MCID::MoveReg), 0x2000a74002030ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr }, // Inst #7626 = VMOVAPSZ128rr_REV
25324 { 7636, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x4010a34002031ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7636 = VMOVAPSZ256rr
25325 { 7637, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x4010a74002030ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7637 = VMOVAPSZ256rr_REV
25335 { 7647, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x8080a34002031ULL, nullptr, nullptr, OperandInfo486, -1 ,nullptr }, // Inst #7647 = VMOVAPSZrr
25336 { 7648, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x8080a74002030ULL, nullptr, nullptr, OperandInfo486, -1 ,nullptr }, // Inst #7648 = VMOVAPSZrr_REV
25343 { 7655, 2, 1, 0, 213, 0|(1ULL<<MCID::MoveReg), 0xa14002031ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #7655 = VMOVAPSrr
25344 { 7656, 2, 1, 0, 213, 0|(1ULL<<MCID::MoveReg), 0xa54002030ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #7656 = VMOVAPSrr_REV
25378 { 7690, 2, 1, 0, 190, 0|(1ULL<<MCID::MoveReg), 0x2001bfc002831ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr }, // Inst #7690 = VMOVDQA32Z128rr
25379 { 7691, 2, 1, 0, 190, 0|(1ULL<<MCID::MoveReg), 0x2001ffc002830ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr }, // Inst #7691 = VMOVDQA32Z128rr_REV
25389 { 7701, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x4011bfc002831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7701 = VMOVDQA32Z256rr
25390 { 7702, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x4011ffc002830ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7702 = VMOVDQA32Z256rr_REV
25400 { 7712, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x8081bfc002831ULL, nullptr, nullptr, OperandInfo486, -1 ,nullptr }, // Inst #7712 = VMOVDQA32Zrr
25401 { 7713, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x8081ffc002830ULL, nullptr, nullptr, OperandInfo486, -1 ,nullptr }, // Inst #7713 = VMOVDQA32Zrr_REV
25411 { 7723, 2, 1, 0, 190, 0|(1ULL<<MCID::MoveReg), 0x2005bfc002831ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr }, // Inst #7723 = VMOVDQA64Z128rr
25412 { 7724, 2, 1, 0, 190, 0|(1ULL<<MCID::MoveReg), 0x2005ffc002830ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr }, // Inst #7724 = VMOVDQA64Z128rr_REV
25422 { 7734, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x4015bfc002831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7734 = VMOVDQA64Z256rr
25423 { 7735, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x4015ffc002830ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7735 = VMOVDQA64Z256rr_REV
25433 { 7745, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x8085bfc002831ULL, nullptr, nullptr, OperandInfo486, -1 ,nullptr }, // Inst #7745 = VMOVDQA64Zrr
25434 { 7746, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x8085ffc002830ULL, nullptr, nullptr, OperandInfo486, -1 ,nullptr }, // Inst #7746 = VMOVDQA64Zrr_REV
25452 { 7764, 2, 1, 0, 190, 0|(1ULL<<MCID::MoveReg), 0x2005bfc003831ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr }, // Inst #7764 = VMOVDQU16Z128rr
25453 { 7765, 2, 1, 0, 190, 0|(1ULL<<MCID::MoveReg), 0x2005ffc003830ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr }, // Inst #7765 = VMOVDQU16Z128rr_REV
25463 { 7775, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x4015bfc003831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7775 = VMOVDQU16Z256rr
25464 { 7776, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x4015ffc003830ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7776 = VMOVDQU16Z256rr_REV
25474 { 7786, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x8085bfc003831ULL, nullptr, nullptr, OperandInfo486, -1 ,nullptr }, // Inst #7786 = VMOVDQU16Zrr
25475 { 7787, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x8085ffc003830ULL, nullptr, nullptr, OperandInfo486, -1 ,nullptr }, // Inst #7787 = VMOVDQU16Zrr_REV
25485 { 7797, 2, 1, 0, 190, 0|(1ULL<<MCID::MoveReg), 0x2001bfc003031ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr }, // Inst #7797 = VMOVDQU32Z128rr
25486 { 7798, 2, 1, 0, 190, 0|(1ULL<<MCID::MoveReg), 0x2001ffc003030ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr }, // Inst #7798 = VMOVDQU32Z128rr_REV
25496 { 7808, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x4011bfc003031ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7808 = VMOVDQU32Z256rr
25497 { 7809, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x4011ffc003030ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7809 = VMOVDQU32Z256rr_REV
25507 { 7819, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x8081bfc003031ULL, nullptr, nullptr, OperandInfo486, -1 ,nullptr }, // Inst #7819 = VMOVDQU32Zrr
25508 { 7820, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x8081ffc003030ULL, nullptr, nullptr, OperandInfo486, -1 ,nullptr }, // Inst #7820 = VMOVDQU32Zrr_REV
25518 { 7830, 2, 1, 0, 190, 0|(1ULL<<MCID::MoveReg), 0x2005bfc003031ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr }, // Inst #7830 = VMOVDQU64Z128rr
25519 { 7831, 2, 1, 0, 190, 0|(1ULL<<MCID::MoveReg), 0x2005ffc003030ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr }, // Inst #7831 = VMOVDQU64Z128rr_REV
25529 { 7841, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x4015bfc003031ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7841 = VMOVDQU64Z256rr
25530 { 7842, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x4015ffc003030ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7842 = VMOVDQU64Z256rr_REV
25540 { 7852, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x8085bfc003031ULL, nullptr, nullptr, OperandInfo486, -1 ,nullptr }, // Inst #7852 = VMOVDQU64Zrr
25541 { 7853, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x8085ffc003030ULL, nullptr, nullptr, OperandInfo486, -1 ,nullptr }, // Inst #7853 = VMOVDQU64Zrr_REV
25551 { 7863, 2, 1, 0, 190, 0|(1ULL<<MCID::MoveReg), 0x2001bfc003831ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr }, // Inst #7863 = VMOVDQU8Z128rr
25552 { 7864, 2, 1, 0, 190, 0|(1ULL<<MCID::MoveReg), 0x2001ffc003830ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr }, // Inst #7864 = VMOVDQU8Z128rr_REV
25562 { 7874, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x4011bfc003831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7874 = VMOVDQU8Z256rr
25563 { 7875, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x4011ffc003830ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7875 = VMOVDQU8Z256rr_REV
25573 { 7885, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x8081bfc003831ULL, nullptr, nullptr, OperandInfo486, -1 ,nullptr }, // Inst #7885 = VMOVDQU8Zrr
25574 { 7886, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x8081ffc003830ULL, nullptr, nullptr, OperandInfo486, -1 ,nullptr }, // Inst #7886 = VMOVDQU8Zrr_REV
25729 { 8041, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x10418002831ULL, nullptr, nullptr, OperandInfo501, -1 ,nullptr }, // Inst #8041 = VMOVUPDYrr
25730 { 8042, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x10458002830ULL, nullptr, nullptr, OperandInfo501, -1 ,nullptr }, // Inst #8042 = VMOVUPDYrr_REV
25736 { 8048, 2, 1, 0, 213, 0|(1ULL<<MCID::MoveReg), 0x2004438002831ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr }, // Inst #8048 = VMOVUPDZ128rr
25737 { 8049, 2, 1, 0, 213, 0|(1ULL<<MCID::MoveReg), 0x2004478002830ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr }, // Inst #8049 = VMOVUPDZ128rr_REV
25747 { 8059, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x4014438002831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #8059 = VMOVUPDZ256rr
25748 { 8060, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x4014478002830ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #8060 = VMOVUPDZ256rr_REV
25758 { 8070, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x8084438002831ULL, nullptr, nullptr, OperandInfo486, -1 ,nullptr }, // Inst #8070 = VMOVUPDZrr
25759 { 8071, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x8084478002830ULL, nullptr, nullptr, OperandInfo486, -1 ,nullptr }, // Inst #8071 = VMOVUPDZrr_REV
25766 { 8078, 2, 1, 0, 213, 0|(1ULL<<MCID::MoveReg), 0x418002831ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #8078 = VMOVUPDrr
25767 { 8079, 2, 1, 0, 213, 0|(1ULL<<MCID::MoveReg), 0x458002830ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #8079 = VMOVUPDrr_REV
25770 { 8082, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x10414002031ULL, nullptr, nullptr, OperandInfo501, -1 ,nullptr }, // Inst #8082 = VMOVUPSYrr
25771 { 8083, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x10454002030ULL, nullptr, nullptr, OperandInfo501, -1 ,nullptr }, // Inst #8083 = VMOVUPSYrr_REV
25777 { 8089, 2, 1, 0, 213, 0|(1ULL<<MCID::MoveReg), 0x2000434002031ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr }, // Inst #8089 = VMOVUPSZ128rr
25778 { 8090, 2, 1, 0, 213, 0|(1ULL<<MCID::MoveReg), 0x2000474002030ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr }, // Inst #8090 = VMOVUPSZ128rr_REV
25788 { 8100, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x4010434002031ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #8100 = VMOVUPSZ256rr
25789 { 8101, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x4010474002030ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #8101 = VMOVUPSZ256rr_REV
25799 { 8111, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x8080434002031ULL, nullptr, nullptr, OperandInfo486, -1 ,nullptr }, // Inst #8111 = VMOVUPSZrr
25800 { 8112, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x8080474002030ULL, nullptr, nullptr, OperandInfo486, -1 ,nullptr }, // Inst #8112 = VMOVUPSZrr_REV
25807 { 8119, 2, 1, 0, 213, 0|(1ULL<<MCID::MoveReg), 0x414002031ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #8119 = VMOVUPSrr
25808 { 8120, 2, 1, 0, 213, 0|(1ULL<<MCID::MoveReg), 0x454002030ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #8120 = VMOVUPSrr_REV
include/llvm/CodeGen/MachineInstr.h 756 return hasProperty(MCID::MoveReg, Type);
include/llvm/MC/MCInstrDesc.h 274 bool isMoveReg() const { return Flags & (1ULL << MCID::MoveReg); }