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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 6008 { 175, 5, 1, 4, 690, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #175 = ADDSri
6009 { 176, 5, 1, 4, 697, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #176 = ADDSrr
6010 { 177, 6, 1, 4, 700, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #177 = ADDSrsi
6011 { 178, 7, 1, 4, 705, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #178 = ADDSrsr
6395 { 562, 3, 1, 2, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo110, -1 ,nullptr }, // Inst #562 = tADCS
6396 { 563, 3, 1, 2, 38, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo111, -1 ,nullptr }, // Inst #563 = tADDSi3
6397 { 564, 3, 1, 2, 38, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo111, -1 ,nullptr }, // Inst #564 = tADDSi8
6398 { 565, 3, 1, 2, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo110, -1 ,nullptr }, // Inst #565 = tADDSrr
6431 { 598, 6, 1, 4, 690, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #598 = ADCri
6432 { 599, 6, 1, 4, 697, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo128, -1 ,nullptr }, // Inst #599 = ADCrr
6433 { 600, 7, 1, 4, 700, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo129, -1 ,nullptr }, // Inst #600 = ADCrsi
6434 { 601, 8, 1, 4, 706, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo130, -1 ,nullptr }, // Inst #601 = ADCrsr
6435 { 602, 6, 1, 4, 690, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #602 = ADDri
6436 { 603, 6, 1, 4, 697, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #603 = ADDrr
6437 { 604, 7, 1, 4, 700, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #604 = ADDrsi
6438 { 605, 8, 1, 4, 706, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #605 = ADDrsr
9575 { 3742, 6, 1, 4, 690, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo450, -1 ,nullptr }, // Inst #3742 = t2ADDri
9576 { 3743, 5, 1, 4, 690, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo451, -1 ,nullptr }, // Inst #3743 = t2ADDri12
9577 { 3744, 6, 1, 4, 697, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo452, -1 ,nullptr }, // Inst #3744 = t2ADDrr
9578 { 3745, 7, 1, 4, 702, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo453, -1 ,nullptr }, // Inst #3745 = t2ADDrs
9958 { 4125, 6, 2, 2, 37, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x80c80ULL, ImplicitList1, nullptr, OperandInfo497, -1 ,nullptr }, // Inst #4125 = tADC
9959 { 4126, 5, 1, 2, 37, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #4126 = tADDhirr
9960 { 4127, 6, 2, 2, 38, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo498, -1 ,nullptr }, // Inst #4127 = tADDi3
9961 { 4128, 6, 2, 2, 38, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo499, -1 ,nullptr }, // Inst #4128 = tADDi8
9964 { 4131, 6, 2, 2, 37, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo502, -1 ,nullptr }, // Inst #4131 = tADDrr
gen/lib/Target/Hexagon/HexagonGenInstrInfo.inc 4383 { 753, 3, 1, 4, 6, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable), 0x214808002ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #753 = A2_addi
4384 { 754, 3, 1, 4, 8, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Commutable), 0x3ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #754 = A2_addp
include/llvm/MC/MCInstrDesc.h 268 bool isAdd() const { return Flags & (1ULL << MCID::Add); }