|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
tools/lldb/source/API/SystemInitializerFull.cpp 240 EmulateInstructionMIPS::Initialize();
337 EmulateInstructionMIPS::Terminate();
tools/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp 211 if (EmulateInstructionMIPS::SupportsEmulatingInstructionsOfTypeStatic(
215 return new EmulateInstructionMIPS(arch);
678 EmulateInstructionMIPS::MipsOpcode *
680 static EmulateInstructionMIPS::MipsOpcode g_opcodes[] = {
682 {"ADDiu", &EmulateInstructionMIPS::Emulate_ADDiu,
684 {"SW", &EmulateInstructionMIPS::Emulate_SW, "SW rt, offset(rs)"},
685 {"LW", &EmulateInstructionMIPS::Emulate_LW, "LW rt, offset(base)"},
686 {"SUBU", &EmulateInstructionMIPS::Emulate_SUBU_ADDU, "SUBU rd, rs, rt"},
687 {"ADDU", &EmulateInstructionMIPS::Emulate_SUBU_ADDU, "ADDU rd, rs, rt"},
688 {"LUI", &EmulateInstructionMIPS::Emulate_LUI, "LUI rt, immediate"},
691 {"ADDIUSP_MM", &EmulateInstructionMIPS::Emulate_ADDIUSP,
693 {"ADDIUS5_MM", &EmulateInstructionMIPS::Emulate_ADDIUS5,
695 {"SWSP_MM", &EmulateInstructionMIPS::Emulate_SWSP, "SWSP rt,offset(sp)"},
696 {"SWM16_MM", &EmulateInstructionMIPS::Emulate_SWM16_32,
698 {"SWM32_MM", &EmulateInstructionMIPS::Emulate_SWM16_32,
700 {"SWP_MM", &EmulateInstructionMIPS::Emulate_SWM16_32,
702 {"LWSP_MM", &EmulateInstructionMIPS::Emulate_LWSP, "LWSP rt,offset(sp)"},
703 {"LWM16_MM", &EmulateInstructionMIPS::Emulate_LWM16_32,
705 {"LWM32_MM", &EmulateInstructionMIPS::Emulate_LWM16_32,
707 {"LWP_MM", &EmulateInstructionMIPS::Emulate_LWM16_32,
709 {"JRADDIUSP", &EmulateInstructionMIPS::Emulate_JRADDIUSP,
720 {"LB", &EmulateInstructionMIPS::Emulate_LDST_Imm,
722 {"LBE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
724 {"LBU", &EmulateInstructionMIPS::Emulate_LDST_Imm,
726 {"LBUE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
728 {"LDC1", &EmulateInstructionMIPS::Emulate_LDST_Imm,
730 {"LD", &EmulateInstructionMIPS::Emulate_LDST_Imm,
732 {"LDL", &EmulateInstructionMIPS::Emulate_LDST_Imm,
734 {"LDR", &EmulateInstructionMIPS::Emulate_LDST_Imm,
736 {"LLD", &EmulateInstructionMIPS::Emulate_LDST_Imm,
738 {"LDC2", &EmulateInstructionMIPS::Emulate_LDST_Imm,
740 {"LDXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg,
742 {"LH", &EmulateInstructionMIPS::Emulate_LDST_Imm,
744 {"LHE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
746 {"LHU", &EmulateInstructionMIPS::Emulate_LDST_Imm,
748 {"LHUE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
750 {"LL", &EmulateInstructionMIPS::Emulate_LDST_Imm,
752 {"LLE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
754 {"LUXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg,
756 {"LW", &EmulateInstructionMIPS::Emulate_LDST_Imm,
758 {"LWC1", &EmulateInstructionMIPS::Emulate_LDST_Imm,
760 {"LWC2", &EmulateInstructionMIPS::Emulate_LDST_Imm,
762 {"LWE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
764 {"LWL", &EmulateInstructionMIPS::Emulate_LDST_Imm,
766 {"LWLE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
768 {"LWR", &EmulateInstructionMIPS::Emulate_LDST_Imm,
770 {"LWRE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
772 {"LWXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg,
774 {"LLX", &EmulateInstructionMIPS::Emulate_LDST_Imm,
776 {"LLXE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
778 {"LLDX", &EmulateInstructionMIPS::Emulate_LDST_Imm,
781 {"SB", &EmulateInstructionMIPS::Emulate_LDST_Imm,
783 {"SBE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
785 {"SC", &EmulateInstructionMIPS::Emulate_LDST_Imm,
787 {"SCE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
789 {"SCD", &EmulateInstructionMIPS::Emulate_LDST_Imm,
791 {"SD", &EmulateInstructionMIPS::Emulate_LDST_Imm,
793 {"SDL", &EmulateInstructionMIPS::Emulate_LDST_Imm,
795 {"SDR", &EmulateInstructionMIPS::Emulate_LDST_Imm,
797 {"SDC1", &EmulateInstructionMIPS::Emulate_LDST_Imm,
799 {"SDC2", &EmulateInstructionMIPS::Emulate_LDST_Imm,
801 {"SDXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg,
803 {"SH", &EmulateInstructionMIPS::Emulate_LDST_Imm,
805 {"SHE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
807 {"SUXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg,
809 {"SWC1", &EmulateInstructionMIPS::Emulate_LDST_Imm,
811 {"SWC2", &EmulateInstructionMIPS::Emulate_LDST_Imm,
813 {"SWE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
815 {"SWL", &EmulateInstructionMIPS::Emulate_LDST_Imm,
817 {"SWLE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
819 {"SWR", &EmulateInstructionMIPS::Emulate_LDST_Imm,
821 {"SWRE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
823 {"SWXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg,
825 {"SCX", &EmulateInstructionMIPS::Emulate_LDST_Imm,
827 {"SCXE", &EmulateInstructionMIPS::Emulate_LDST_Imm,
829 {"SCDX", &EmulateInstructionMIPS::Emulate_LDST_Imm,
833 {"LBU16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,
835 {"LHU16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,
837 {"LW16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,
839 {"LWGP_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,
841 {"SH16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,
843 {"SW16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,
845 {"SW_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,
847 {"SB16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,
851 {"BEQ", &EmulateInstructionMIPS::Emulate_BXX_3ops, "BEQ rs,rt,offset"},
852 {"BNE", &EmulateInstructionMIPS::Emulate_BXX_3ops, "BNE rs,rt,offset"},
853 {"BEQL", &EmulateInstructionMIPS::Emulate_BXX_3ops, "BEQL rs,rt,offset"},
854 {"BNEL", &EmulateInstructionMIPS::Emulate_BXX_3ops, "BNEL rs,rt,offset"},
855 {"BGEZALL", &EmulateInstructionMIPS::Emulate_Bcond_Link,
857 {"BAL", &EmulateInstructionMIPS::Emulate_BAL, "BAL offset"},
858 {"BGEZAL", &EmulateInstructionMIPS::Emulate_Bcond_Link,
860 {"BALC", &EmulateInstructionMIPS::Emulate_BALC, "BALC offset"},
861 {"BC", &EmulateInstructionMIPS::Emulate_BC, "BC offset"},
862 {"BGEZ", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BGEZ rs,offset"},
863 {"BLEZALC", &EmulateInstructionMIPS::Emulate_Bcond_Link_C,
865 {"BGEZALC", &EmulateInstructionMIPS::Emulate_Bcond_Link_C,
867 {"BLTZALC", &EmulateInstructionMIPS::Emulate_Bcond_Link_C,
869 {"BGTZALC", &EmulateInstructionMIPS::Emulate_Bcond_Link_C,
871 {"BEQZALC", &EmulateInstructionMIPS::Emulate_Bcond_Link_C,
873 {"BNEZALC", &EmulateInstructionMIPS::Emulate_Bcond_Link_C,
875 {"BEQC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,
877 {"BNEC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,
879 {"BLTC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,
881 {"BGEC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,
883 {"BLTUC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,
885 {"BGEUC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,
887 {"BLTZC", &EmulateInstructionMIPS::Emulate_BXX_2ops_C, "BLTZC rt,offset"},
888 {"BLEZC", &EmulateInstructionMIPS::Emulate_BXX_2ops_C, "BLEZC rt,offset"},
889 {"BGEZC", &EmulateInstructionMIPS::Emulate_BXX_2ops_C, "BGEZC rt,offset"},
890 {"BGTZC", &EmulateInstructionMIPS::Emulate_BXX_2ops_C, "BGTZC rt,offset"},
891 {"BEQZC", &EmulateInstructionMIPS::Emulate_BXX_2ops_C, "BEQZC rt,offset"},
892 {"BNEZC", &EmulateInstructionMIPS::Emulate_BXX_2ops_C, "BNEZC rt,offset"},
893 {"BGEZL", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BGEZL rt,offset"},
894 {"BGTZ", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BGTZ rt,offset"},
895 {"BGTZL", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BGTZL rt,offset"},
896 {"BLEZ", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BLEZ rt,offset"},
897 {"BLEZL", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BLEZL rt,offset"},
898 {"BLTZ", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BLTZ rt,offset"},
899 {"BLTZAL", &EmulateInstructionMIPS::Emulate_Bcond_Link,
901 {"BLTZALL", &EmulateInstructionMIPS::Emulate_Bcond_Link,
903 {"BLTZL", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BLTZL rt,offset"},
904 {"BOVC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,
906 {"BNVC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,
908 {"J", &EmulateInstructionMIPS::Emulate_J, "J target"},
909 {"JAL", &EmulateInstructionMIPS::Emulate_JAL, "JAL target"},
910 {"JALX", &EmulateInstructionMIPS::Emulate_JAL, "JALX target"},
911 {"JALR", &EmulateInstructionMIPS::Emulate_JALR, "JALR target"},
912 {"JALR_HB", &EmulateInstructionMIPS::Emulate_JALR, "JALR.HB target"},
913 {"JIALC", &EmulateInstructionMIPS::Emulate_JIALC, "JIALC rt,offset"},
914 {"JIC", &EmulateInstructionMIPS::Emulate_JIC, "JIC rt,offset"},
915 {"JR", &EmulateInstructionMIPS::Emulate_JR, "JR target"},
916 {"JR_HB", &EmulateInstructionMIPS::Emulate_JR, "JR.HB target"},
917 {"BC1F", &EmulateInstructionMIPS::Emulate_FP_branch, "BC1F cc, offset"},
918 {"BC1T", &EmulateInstructionMIPS::Emulate_FP_branch, "BC1T cc, offset"},
919 {"BC1FL", &EmulateInstructionMIPS::Emulate_FP_branch, "BC1FL cc, offset"},
920 {"BC1TL", &EmulateInstructionMIPS::Emulate_FP_branch, "BC1TL cc, offset"},
921 {"BC1EQZ", &EmulateInstructionMIPS::Emulate_BC1EQZ, "BC1EQZ ft, offset"},
922 {"BC1NEZ", &EmulateInstructionMIPS::Emulate_BC1NEZ, "BC1NEZ ft, offset"},
923 {"BC1ANY2F", &EmulateInstructionMIPS::Emulate_3D_branch,
925 {"BC1ANY2T", &EmulateInstructionMIPS::Emulate_3D_branch,
927 {"BC1ANY4F", &EmulateInstructionMIPS::Emulate_3D_branch,
929 {"BC1ANY4T", &EmulateInstructionMIPS::Emulate_3D_branch,
931 {"BNZ_B", &EmulateInstructionMIPS::Emulate_BNZB, "BNZ.b wt,s16"},
932 {"BNZ_H", &EmulateInstructionMIPS::Emulate_BNZH, "BNZ.h wt,s16"},
933 {"BNZ_W", &EmulateInstructionMIPS::Emulate_BNZW, "BNZ.w wt,s16"},
934 {"BNZ_D", &EmulateInstructionMIPS::Emulate_BNZD, "BNZ.d wt,s16"},
935 {"BZ_B", &EmulateInstructionMIPS::Emulate_BZB, "BZ.b wt,s16"},
936 {"BZ_H", &EmulateInstructionMIPS::Emulate_BZH, "BZ.h wt,s16"},
937 {"BZ_W", &EmulateInstructionMIPS::Emulate_BZW, "BZ.w wt,s16"},
938 {"BZ_D", &EmulateInstructionMIPS::Emulate_BZD, "BZ.d wt,s16"},
939 {"BNZ_V", &EmulateInstructionMIPS::Emulate_BNZV, "BNZ.V wt,s16"},
940 {"BZ_V", &EmulateInstructionMIPS::Emulate_BZV, "BZ.V wt,s16"},
943 {"B16_MM", &EmulateInstructionMIPS::Emulate_B16_MM, "B16 offset"},
944 {"BEQZ16_MM", &EmulateInstructionMIPS::Emulate_Branch_MM,
946 {"BNEZ16_MM", &EmulateInstructionMIPS::Emulate_Branch_MM,
948 {"BEQZC_MM", &EmulateInstructionMIPS::Emulate_Branch_MM,
950 {"BNEZC_MM", &EmulateInstructionMIPS::Emulate_Branch_MM,
952 {"BGEZALS_MM", &EmulateInstructionMIPS::Emulate_Branch_MM,
954 {"BLTZALS_MM", &EmulateInstructionMIPS::Emulate_Branch_MM,
956 {"JALR16_MM", &EmulateInstructionMIPS::Emulate_JALRx16_MM, "JALR16 rs"},
957 {"JALRS16_MM", &EmulateInstructionMIPS::Emulate_JALRx16_MM, "JALRS16 rs"},
958 {"JR16_MM", &EmulateInstructionMIPS::Emulate_JR, "JR16 rs rs"},
959 {"JRC16_MM", &EmulateInstructionMIPS::Emulate_JR, "JRC16 rs rs"},
960 {"JALS_MM", &EmulateInstructionMIPS::Emulate_JALx, "JALS target"},
961 {"JALX_MM", &EmulateInstructionMIPS::Emulate_JALx, "JALX target"},
962 {"JALRS_MM", &EmulateInstructionMIPS::Emulate_JALRS, "JALRS rt, rs"},