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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
lib/Target/ARM/ARMBaseInstrInfo.cpp 591 return ARM_AM::getAM2ShiftOpc(OffImm) != ARM_AM::no_shift;
603 if (ShiftOpc == ARM_AM::no_shift) return false; // not scaled
619 return ARM_AM::getAM2ShiftOpc(OffImm) != ARM_AM::no_shift;
lib/Target/ARM/ARMFastISel.cpp 2644 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 },
2645 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } },
2646 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 },
2647 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } },
2648 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 },
2649 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } }
2654 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2655 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } },
2656 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 },
2657 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } },
2658 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 },
2659 /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } }
2662 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2663 /* 1 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 1 } },
2664 /* 8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift, 0 },
2665 /* 8 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },
2666 /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift, 0 },
2667 /* 16 bit zext */ { ARM::t2UXTH , 0, ARM_AM::no_shift, 0 } }
2692 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2703 bool ImmIsSO = (Shift != ARM_AM::no_shift);
lib/Target/ARM/ARMFrameLowering.cpp 1145 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
lib/Target/ARM/ARMISelDAGToDAG.cpp 552 if (ShOpcVal == ARM_AM::no_shift) return false;
576 if (ShOpcVal == ARM_AM::no_shift) return false;
701 if (ShOpcVal != ARM_AM::no_shift) {
711 ShOpcVal = ARM_AM::no_shift;
714 ShOpcVal = ARM_AM::no_shift;
719 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
723 if (ShOpcVal != ARM_AM::no_shift) {
734 ShOpcVal = ARM_AM::no_shift;
737 ShOpcVal = ARM_AM::no_shift;
776 if (ShOpcVal != ARM_AM::no_shift) {
785 ShOpcVal = ARM_AM::no_shift;
788 ShOpcVal = ARM_AM::no_shift;
829 ARM_AM::no_shift),
lib/Target/ARM/ARMISelLowering.cpp 4220 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
4221 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
15162 if (ShOpcVal != ARM_AM::no_shift) {
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 1457 int Imm = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift);
1481 int Imm = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift);
lib/Target/ARM/ARMSelectionDAGInfo.h 25 default: return ARM_AM::no_shift;
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 1380 return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift;
1540 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1600 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1624 if (Memory.ShiftType == ARM_AM::no_shift)
1635 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1772 if (shift == 0 && Memory.ShiftType != ARM_AM::no_shift)
2815 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2836 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
3776 if (Memory.ShiftType != ARM_AM::no_shift) {
3787 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
3963 .Default(ARM_AM::no_shift);
3965 if (ShiftTy == ARM_AM::no_shift)
5460 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
5542 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
5666 ARM_AM::no_shift, 0, 0, false,
5723 ARM_AM::no_shift, 0, Align,
5776 ARM_AM::no_shift, 0, 0,
5805 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp 54 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp 248 case ARM_AM::no_shift: