reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
600 bool isAdd = ARM_AM::getAM2Op(OffImm) == ARM_AM::add;
lib/Target/ARM/ARMFrameLowering.cpp 1145 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
lib/Target/ARM/ARMISelDAGToDAG.cpp662 ARM_AM::AddrOpc AddSub = ARM_AM::add; 693 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add; 768 ? ARM_AM::add : ARM_AM::sub; 804 ? ARM_AM::add : ARM_AM::sub; 824 ? ARM_AM::add : ARM_AM::sub; 862 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), SDLoc(N), 879 ARM_AM::AddrOpc AddSub = ARM_AM::add; 891 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), SDLoc(N), 903 ? ARM_AM::add : ARM_AM::sub; 932 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0), 949 ARM_AM::AddrOpc AddSub = ARM_AM::add; 968 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5FP16Opc(ARM_AM::add, 0), 971 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),lib/Target/ARM/ARMLoadStoreOptimizer.cpp
1341 return Mode == ARM_AM::add ? ARM::VLDMSIA_UPD : ARM::VLDMSDB_UPD; 1343 return Mode == ARM_AM::add ? ARM::VLDMDIA_UPD : ARM::VLDMDDB_UPD; 1345 return Mode == ARM_AM::add ? ARM::VSTMSIA_UPD : ARM::VSTMSDB_UPD; 1347 return Mode == ARM_AM::add ? ARM::VSTMDIA_UPD : ARM::VSTMDDB_UPD; 1366 return Mode == ARM_AM::add ? ARM::VLDMSIA_UPD : ARM::VLDMSDB_UPD; 1368 return Mode == ARM_AM::add ? ARM::VLDMDIA_UPD : ARM::VLDMDDB_UPD; 1370 return Mode == ARM_AM::add ? ARM::VSTMSIA_UPD : ARM::VSTMSDB_UPD; 1372 return Mode == ARM_AM::add ? ARM::VSTMDIA_UPD : ARM::VSTMDDB_UPD; 1418 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::add); 1424 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::add); 1432 ARM_AM::AddrOpc AddSub = Offset < 0 ? ARM_AM::sub : ARM_AM::add; 2195 ARM_AM::AddrOpc AddSub = ARM_AM::add;lib/Target/ARM/AsmParser/ARMAsmParser.cpp
2811 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2819 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 2832 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2855 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2863 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 2874 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 2883 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2905 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2927 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 3042 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 3124 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;lib/Target/ARM/Disassembler/ARMDisassembler.cpp
1756 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1865 ARM_AM::AddrOpc Op = ARM_AM::add; 1952 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 2568 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2588 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
409 return ((AM2Opc >> 12) & 1) ? sub : add; 438 return ((AM3Opc >> 8) & 1) ? sub : add; 481 return ((AM5Opc >> 8) & 1) ? sub : add; 504 return ((AM5Opc >> 8) & 1) ? sub : add;lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
1259 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; 1293 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add; 1329 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 1365 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 1445 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add; 1485 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;