reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 3721     OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
 3724     OS << "<ARMVCC::" << ARMVPTPredToString(getVPTPred()) << ">";
 3727     OS << "<ccout " << RegName(getReg()) << ">";
 3737     OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
 3741     OS << "<coprocessor number: " << getCoproc() << ">";
 3744     OS << "<coprocessor register: " << getCoproc() << ">";
 3747     OS << "<coprocessor option: " << CoprocOption.Val << ">";
 3750     OS << "<mask: " << getMSRMask() << ">";
 3753     OS << "<banked reg: " << getBankedReg() << ">";
 3756     OS << *getImm();
 3759     OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
 3762     OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
 3765     OS << "<ARM_TSB::" << TraceSyncBOptToString(getTraceSyncBarrierOpt()) << ">";
 3768     OS << "<memory";
 3770       OS << " base:" << RegName(Memory.BaseRegNum);
 3772       OS << " offset-imm:" << *Memory.OffsetImm;
 3774       OS << " offset-reg:" << (Memory.isNegative ? "-" : "")
 3777       OS << " shift-type:" << ARM_AM::getShiftOpcStr(Memory.ShiftType);
 3778       OS << " shift-imm:" << Memory.ShiftImm;
 3781       OS << " alignment:" << Memory.Alignment;
 3782     OS << ">";
 3785     OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
 3788       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
 3790     OS << ">";
 3793     OS << "<ARM_PROC::";
 3797         OS << ARM_PROC::IFlagsToString(1 << i);
 3798     OS << ">";
 3802     OS << "<register " << RegName(getReg()) << ">";
 3805     OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
 3809     OS << "<so_reg_reg " << RegName(RegShiftedReg.SrcReg) << " "
 3814     OS << "<so_reg_imm " << RegName(RegShiftedImm.SrcReg) << " "
 3819     OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
 3822     OS << "<mod_imm #" << ModImm.Bits << ", #"
 3826     OS << "<constant_pool_imm #" << *getConstantPoolImm();
 3829     OS << "<bitfield " << "lsb: " << Bitfield.LSB
 3838     OS << "<register_list ";
 3843       OS << RegName(*I);
 3844       if (++I < E) OS << ", ";
 3847     OS << ">";
 3851     OS << "<vector_list " << VectorList.Count << " * "
 3855     OS << "<vector_list(all lanes) " << VectorList.Count << " * "
 3859     OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
 3863     OS << "'" << getToken() << "'";
 3866     OS << "<vectorindex " << getVectorIndex() << ">";