reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
837 assert(I.getParent() && "Instruction should be in a basic block!"); 838 assert(I.getParent()->getParent() && "Instruction should be in a function!"); 840 auto &MBB = *I.getParent(); 844 if (!isPreISelGenericOpcode(I.getOpcode())) { 845 if (I.isCopy()) 846 return selectCopy(I, TII, MRI, TRI, RBI); 853 if (selectImpl(I, *CoverageInfo)) 856 MachineInstrBuilder MIB{MF, I}; 859 switch (I.getOpcode()) { 864 assert(MRI.getType(I.getOperand(0).getReg()).getSizeInBits() <= 32 && 867 LLT SrcTy = MRI.getType(I.getOperand(1).getReg()); 872 I.setDesc(TII.get(Opcodes.AND)); 876 Register SExtResult = I.getOperand(0).getReg(); 880 I.getOperand(0).setReg(AndResult); 882 auto InsertBefore = std::next(I.getIterator()); 884 BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(Opcodes.RSB)) 897 unsigned NewOpc = selectSimpleExtOpc(I.getOpcode(), SrcSize); 898 if (NewOpc == I.getOpcode()) 900 I.setDesc(TII.get(NewOpc)); 914 auto SrcReg = I.getOperand(1).getReg(); 915 auto DstReg = I.getOperand(0).getReg(); 924 assert(I.getOpcode() == G_TRUNC && "Unsupported operand for G_ANYEXT"); 931 auto InsertBefore = std::next(I.getIterator()); 933 BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(ARM::VMOVRRD)) 956 I.setDesc(TII.get(COPY)); 957 return selectCopy(I, TII, MRI, TRI, RBI); 960 if (!MRI.getType(I.getOperand(0).getReg()).isPointer()) { 966 auto &Val = I.getOperand(1); 982 I.setDesc(TII.get(ARM::MOVi)); 988 unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits() / 8; 996 ConstPool->getConstantPoolIndex(I.getOperand(1).getFPImm(), Alignment); 1009 auto SrcReg = I.getOperand(1).getReg(); 1010 auto DstReg = I.getOperand(0).getReg(); 1028 I.setDesc(TII.get(COPY)); 1029 return selectCopy(I, TII, MRI, TRI, RBI); 1041 Register OpReg = I.getOperand(2).getReg(); 1065 I.setDesc(TII.get(Opcodes.ADDrr)); 1071 I.setDesc(TII.get(Opcodes.ADDri)); 1078 const auto &MemOp = **I.memoperands_begin(); 1084 Register Reg = I.getOperand(0).getReg(); 1093 const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize); 1099 Register OriginalValue = I.getOperand(0).getReg(); 1102 I.getOperand(0).setReg(ValueToStore); 1104 auto InsertBefore = I.getIterator(); 1105 auto AndI = BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(Opcodes.AND)) 1115 I.setDesc(TII.get(NewOpc)); 1134 if (!validReg(MRI, I.getOperand(0).getReg(), 1, ARM::GPRRegBankID)) { 1141 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.TSTri)) 1141 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.TSTri)) 1141 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.TSTri)) 1142 .addReg(I.getOperand(0).getReg()) 1150 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.Bcc)) 1150 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.Bcc)) 1150 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.Bcc)) 1151 .add(I.getOperand(1)) 1155 I.eraseFromParent(); 1159 I.setDesc(TII.get(PHI)); 1161 Register DstReg = I.getOperand(0).getReg(); 1173 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);