reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/Target/ARM/ARMBaseInstrInfo.cpp
 4932   MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
 4932   MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
 4934   switch (MI.getOpcode()) {
 4943     assert(!isPredicated(MI) && "Cannot predicate a VORRd");
 4949     DstReg = MI.getOperand(0).getReg();
 4950     SrcReg = MI.getOperand(1).getReg();
 4952     for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
 4953       MI.RemoveOperand(i - 1);
 4956     MI.setDesc(get(ARM::VORRd));
 4965     assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
 4968     DstReg = MI.getOperand(0).getReg();
 4969     SrcReg = MI.getOperand(1).getReg();
 4971     for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
 4972       MI.RemoveOperand(i - 1);
 4979     MI.setDesc(get(ARM::VGETLNi32));
 4992     assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
 4995     DstReg = MI.getOperand(0).getReg();
 4996     SrcReg = MI.getOperand(1).getReg();
 5001     if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
 5004     for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
 5005       MI.RemoveOperand(i - 1);
 5009     MI.setDesc(get(ARM::VSETLNi32));
 5011         .addReg(DReg, getUndefRegState(!MI.readsRegister(DReg, TRI)))
 5028       DstReg = MI.getOperand(0).getReg();
 5029       SrcReg = MI.getOperand(1).getReg();
 5036       if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
 5039       for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
 5040         MI.RemoveOperand(i - 1);
 5045         MI.setDesc(get(ARM::VDUPLN32d));
 5047             .addReg(DDst, getUndefRegState(!MI.readsRegister(DDst, TRI)))
 5073       NewMIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::VEXTd32),
 5073       NewMIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::VEXTd32),
 5073       NewMIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::VEXTd32),
 5080       bool CurUndef = !MI.readsRegister(CurReg, TRI);
 5084       CurUndef = !MI.readsRegister(CurReg, TRI);
 5092       MI.setDesc(get(ARM::VEXTd32));
 5098       CurUndef = CurReg == DSrc && !MI.readsRegister(CurReg, TRI);
 5102       CurUndef = CurReg == DSrc && !MI.readsRegister(CurReg, TRI);