reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
950 &MI, TII, MRI, TRI, CallAddrOpIdx, false); 961 &MI, TII, MRI, TRI, RtnAddrOpIdx, false); 991 ScoreBrackets.getRegInterval(&MI, TII, MRI, TRI, I, false); 1027 ScoreBrackets.getRegInterval(&MI, TII, MRI, TRI, I, true); 1153 MI.getDebugLoc(), TII->get(AMDGPU::S_WAITCNT)) 1168 TII->get(AMDGPU::S_WAITCNT_VSCNT)) 1203 if (TII->isDS(Inst) && TII->usesLGKM_CNT(Inst)) { 1203 if (TII->isDS(Inst) && TII->usesLGKM_CNT(Inst)) { 1204 if (TII->isAlwaysGDS(Inst.getOpcode()) || 1205 TII->hasModifiersSet(Inst, AMDGPU::OpName::gds)) { 1206 ScoreBrackets->updateByEvent(TII, TRI, MRI, GDS_ACCESS, Inst); 1207 ScoreBrackets->updateByEvent(TII, TRI, MRI, GDS_GPR_LOCK, Inst); 1209 ScoreBrackets->updateByEvent(TII, TRI, MRI, LDS_ACCESS, Inst); 1211 } else if (TII->isFLAT(Inst)) { 1214 if (TII->usesVM_CNT(Inst)) { 1216 ScoreBrackets->updateByEvent(TII, TRI, MRI, VMEM_ACCESS, Inst); 1219 ScoreBrackets->updateByEvent(TII, TRI, MRI, VMEM_READ_ACCESS, Inst); 1221 ScoreBrackets->updateByEvent(TII, TRI, MRI, VMEM_WRITE_ACCESS, Inst); 1224 if (TII->usesLGKM_CNT(Inst)) { 1225 ScoreBrackets->updateByEvent(TII, TRI, MRI, LDS_ACCESS, Inst); 1241 ScoreBrackets->updateByEvent(TII, TRI, MRI, VMEM_ACCESS, Inst); 1245 (TII->isMIMG(Inst) && !Inst.mayLoad() && !Inst.mayStore())) 1246 ScoreBrackets->updateByEvent(TII, TRI, MRI, VMEM_READ_ACCESS, Inst); 1248 ScoreBrackets->updateByEvent(TII, TRI, MRI, VMEM_WRITE_ACCESS, Inst); 1252 ScoreBrackets->updateByEvent(TII, TRI, MRI, VMW_GPR_LOCK, Inst); 1254 } else if (TII->isSMRD(Inst)) { 1255 ScoreBrackets->updateByEvent(TII, TRI, MRI, SMEM_ACCESS, Inst); 1268 ScoreBrackets->updateByEvent(TII, TRI, MRI, SQ_MESSAGE, Inst); 1272 int Imm = TII->getNamedOperand(Inst, AMDGPU::OpName::tgt)->getImm(); 1274 ScoreBrackets->updateByEvent(TII, TRI, MRI, EXP_PARAM_ACCESS, Inst); 1276 ScoreBrackets->updateByEvent(TII, TRI, MRI, EXP_POS_ACCESS, Inst); 1278 ScoreBrackets->updateByEvent(TII, TRI, MRI, EXP_GPR_LOCK, Inst); 1283 ScoreBrackets->updateByEvent(TII, TRI, MRI, SMEM_ACCESS, Inst); 1431 TII->get(ST->isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64), 1446 TII = ST->getInstrInfo(); 1447 TRI = &TII->getRegisterInfo(); 1549 if (!HaveScalarStores && TII->isScalarStore(*I)) 1573 else if (TII->isScalarStore(*I)) 1581 BuildMI(*MBB, I, I->getDebugLoc(), TII->get(AMDGPU::S_DCACHE_WB)); 1597 TII->get(AMDGPU::S_WAITCNT_VSCNT)) 1600 BuildMI(EntryBB, EntryBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_WAITCNT))