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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenCallingConv.inc 114 if (LocVT == MVT::v3i32 ||
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc30926 /* 65306*/ /*SwitchType*/ 41, MVT::v3i32,// ->65349
30931 MVT::v3i32, 9/*#Ops*/, 3, 2, 4, 5, 6, 7, 8, 9, 10,
30938 MVT::v3i32, 8/*#Ops*/, 2, 3, 4, 5, 6, 7, 8, 9,
30987 /* 65471*/ /*SwitchType*/ 71, MVT::v3i32,// ->65544
30997 MVT::v3i32, 8/*#Ops*/, 2, 3, 4, 5, 6, 7, 8, 9,
31009 MVT::v3i32, 9/*#Ops*/, 3, 2, 4, 5, 6, 7, 8, 9, 10,
31130 /* 65814*/ /*SwitchType*/ 23, MVT::v3i32,// ->65839
31137 MVT::v3i32, 5/*#Ops*/, 2, 3, 5, 6, 4,
31153 /* 65869*/ OPC_SwitchType /*5 cases */, 23, MVT::v3i32,// ->65895
31160 MVT::v3i32, 5/*#Ops*/, 2, 3, 5, 6, 4,
32015 /* 67730*/ OPC_CheckChild1Type, MVT::v3i32,
32265 /* 68354*/ OPC_CheckChild1Type, MVT::v3i32,
32477 /* 68883*/ OPC_CheckChild1Type, MVT::v3i32,
33204 /* 70382*/ OPC_CheckChild1Type, MVT::v3i32,
33438 /* 70895*/ OPC_CheckChild1Type, MVT::v3i32,
35972 /* 76282*/ /*SwitchType*/ 37, MVT::v3i32,// ->76321
35982 MVT::v3i32, 9/*#Ops*/, 1, 2, 6, 7, 8, 9, 10, 11, 12,
36030 /* 76429*/ /*SwitchType*/ 38, MVT::v3i32,// ->76469
36040 MVT::v3i32, 10/*#Ops*/, 2, 1, 3, 7, 8, 9, 10, 11, 12, 13,
36091 /* 76585*/ /*SwitchType*/ 38, MVT::v3i32,// ->76625
36101 MVT::v3i32, 10/*#Ops*/, 2, 1, 3, 7, 8, 9, 10, 11, 12, 13,
36154 /* 76755*/ /*SwitchType*/ 58, MVT::v3i32,// ->76815
36169 MVT::v3i32, 10/*#Ops*/, 11, 1, 4, 12, 13, 14, 15, 16, 17, 18,
36721 /* 78158*/ OPC_CheckChild1Type, MVT::v3i32,
38562 /* 82288*/ /*SwitchType*/ 33, MVT::v3i32,// ->82323
38571 MVT::v3i32, 8/*#Ops*/, 1, 2, 5, 6, 7, 8, 9, 10,
38613 /* 82416*/ /*SwitchType*/ 34, MVT::v3i32,// ->82452
38622 MVT::v3i32, 9/*#Ops*/, 2, 1, 3, 6, 7, 8, 9, 10, 11,
38667 /* 82553*/ /*SwitchType*/ 34, MVT::v3i32,// ->82589
38676 MVT::v3i32, 9/*#Ops*/, 2, 1, 3, 6, 7, 8, 9, 10, 11,
38723 /* 82704*/ /*SwitchType*/ 54, MVT::v3i32,// ->82760
38737 MVT::v3i32, 9/*#Ops*/, 10, 1, 4, 11, 12, 13, 14, 15, 16,
40118 /* 86178*/ /*SwitchType*/ 33, MVT::v3i32,// ->86213
40127 MVT::v3i32, 8/*#Ops*/, 1, 2, 5, 6, 7, 8, 9, 10,
40193 /* 86378*/ /*SwitchType*/ 34, MVT::v3i32,// ->86414
40202 MVT::v3i32, 9/*#Ops*/, 2, 1, 3, 6, 7, 8, 9, 10, 11,
40271 /* 86587*/ /*SwitchType*/ 34, MVT::v3i32,// ->86623
40280 MVT::v3i32, 9/*#Ops*/, 2, 1, 3, 6, 7, 8, 9, 10, 11,
40361 /* 86850*/ /*SwitchType*/ 54, MVT::v3i32,// ->86906
40375 MVT::v3i32, 9/*#Ops*/, 10, 1, 4, 11, 12, 13, 14, 15, 16,
41789 /* 90221*/ OPC_CheckChild1Type, MVT::v3i32,
44261 /* 95785*/ OPC_CheckChild1Type, MVT::v3i32,
58594 /*128377*/ OPC_CheckChild0Type, MVT::v3i32,
62736 /*136970*/ OPC_CheckType, MVT::v3i32,
62812 /*137070*/ OPC_CheckChild0Type, MVT::v3i32,
77357 /*171992*/ /*SwitchType*/ 12, MVT::v3i32,// ->172006
77360 MVT::v3i32, 3/*#Ops*/, 0, 1, 2,
77402 /*172095*/ /*SwitchType*/ 12, MVT::v3i32,// ->172109
77405 MVT::v3i32, 3/*#Ops*/, 0, 1, 2,
77447 /*172198*/ /*SwitchType*/ 12, MVT::v3i32,// ->172212
77450 MVT::v3i32, 3/*#Ops*/, 0, 1, 2,
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc17472 /* 82 */ MVT::v3i32, MVT::v3f32, MVT::Other,
include/llvm/Support/MachineValueType.h 477 case v3i32:
633 case v3i32:
748 case v3i32:
940 if (NumElements == 3) return MVT::v3i32;
lib/CodeGen/ValueTypes.cpp 170 case MVT::v3i32: return "v3i32";
314 case MVT::v3i32: return VectorType::get(Type::getInt32Ty(Context), 3);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 77 AddPromotedToType(ISD::LOAD, MVT::v3f32, MVT::v3i32);
177 AddPromotedToType(ISD::STORE, MVT::v3f32, MVT::v3i32);
278 setOperationAction(ISD::CONCAT_VECTORS, MVT::v3i32, Custom);
289 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3i32, Custom);
357 MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32
442 AddPromotedToType(ISD::SELECT, MVT::v3f32, MVT::v3i32);
lib/Target/AMDGPU/SIISelLowering.cpp 127 addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass);
165 setOperationAction(ISD::LOAD, MVT::v3i32, Custom);
174 setOperationAction(ISD::STORE, MVT::v3i32, Custom);
183 setTruncStoreAction(MVT::v3i32, MVT::v3i16, Expand);
326 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3i32, Custom);
6718 (WidenedVT == MVT::v3i32 || WidenedVT == MVT::v3f32)) {
utils/TableGen/CodeGenTarget.cpp 110 case MVT::v3i32: return "MVT::v3i32";