|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenCallingConv.inc 283 if (LocVT == MVT::f32) {
355 LocVT == MVT::f32) {
527 if (LocVT == MVT::f32) {
601 LocVT == MVT::f32) {
680 LocVT = MVT::f32;
692 LocVT == MVT::f32) {
775 LocVT == MVT::f32) {
856 if (LocVT == MVT::f32) {
933 LocVT == MVT::f32) {
970 LocVT == MVT::f32) {
1096 if (LocVT == MVT::f32) {
1226 if (LocVT == MVT::f32) {
gen/lib/Target/AArch64/AArch64GenDAGISel.inc 2836 /* 5656*/ OPC_CheckType, MVT::f32,
2839 MVT::f32, 2/*#Ops*/, 0, 1,
2849 /* 5680*/ OPC_CheckType, MVT::f32,
2852 MVT::f32, 2/*#Ops*/, 0, 2,
69899 /*167780*/ OPC_CheckType, MVT::f32,
69952 /*167901*/ OPC_CheckType, MVT::f32,
70208 /*168425*/ OPC_CheckType, MVT::f32,
70550 /*169166*/ OPC_CheckChild1Type, MVT::f32,
71382 /*170898*/ OPC_CheckType, MVT::f32,
71550 /*171234*/ OPC_CheckType, MVT::f32,
71753 /*171655*/ OPC_CheckChild1Type, MVT::f32,
71888 /*171897*/ OPC_CheckType, MVT::f32,
72056 /*172219*/ OPC_CheckType, MVT::f32,
72386 /*172880*/ OPC_CheckChild1Type, MVT::f32,
74326 /*176478*/ /*SwitchType*/ 59, MVT::f32,// ->176539
74405 /*176629*/ OPC_CheckChild1Type, MVT::f32,
74505 /*176812*/ /*SwitchType*/ 59, MVT::f32,// ->176873
74584 /*176963*/ OPC_CheckChild1Type, MVT::f32,
75006 /*177713*/ OPC_CheckChild1Type, MVT::f32,
75148 /*177983*/ OPC_CheckChild1Type, MVT::f32,
75820 /*179204*/ OPC_CheckChild1Type, MVT::f32,
75916 /*179375*/ OPC_CheckChild1Type, MVT::f32,
76012 /*179546*/ OPC_CheckChild1Type, MVT::f32,
76108 /*179717*/ OPC_CheckChild1Type, MVT::f32,
76204 /*179888*/ OPC_CheckChild1Type, MVT::f32,
76300 /*180059*/ OPC_CheckChild1Type, MVT::f32,
76396 /*180230*/ OPC_CheckChild1Type, MVT::f32,
76492 /*180401*/ OPC_CheckChild1Type, MVT::f32,
76583 /*180565*/ OPC_CheckChild1Type, MVT::f32,
76585 /*180568*/ OPC_CheckChild2Type, MVT::f32,
76674 /*180744*/ OPC_CheckChild1Type, MVT::f32,
76676 /*180747*/ OPC_CheckChild2Type, MVT::f32,
78251 /*183888*/ OPC_CheckType, MVT::f32,
78254 MVT::f32, 2/*#Ops*/, 0, 2,
78403 /*184169*/ OPC_CheckChild1Type, MVT::f32,
78414 /*184188*/ OPC_CheckType, MVT::f32,
78416 /*184191*/ OPC_CheckType, MVT::f32,
78420 MVT::f32, 3/*#Ops*/, 0, 1, 3,
78476 /*184299*/ OPC_CheckType, MVT::f32,
78479 /*184303*/ OPC_CheckChild2Type, MVT::f32,
78480 /*184305*/ OPC_CheckType, MVT::f32,
78484 MVT::f32, 3/*#Ops*/, 2, 0, 3,
78520 /*184378*/ OPC_CheckChild1Type, MVT::f32,
78522 /*184381*/ OPC_CheckChild2Type, MVT::f32,
78523 /*184383*/ OPC_CheckType, MVT::f32,
78526 MVT::f32, 2/*#Ops*/, 0, 1,
78852 /*184993*/ OPC_CheckType, MVT::f32,
78855 MVT::f32, 2/*#Ops*/, 0, 2,
78961 /*185192*/ /*SwitchType*/ 11, MVT::f32,// ->185205
78962 /*185194*/ OPC_CheckChild1Type, MVT::f32,
78965 MVT::f32, 1/*#Ops*/, 0,
79029 /*185318*/ /*SwitchType*/ 15, MVT::f32,// ->185335
79030 /*185320*/ OPC_CheckChild1Type, MVT::f32,
79032 /*185323*/ OPC_CheckChild2Type, MVT::f32,
79035 MVT::f32, 2/*#Ops*/, 0, 1,
79069 /*185394*/ /*SwitchType*/ 15, MVT::f32,// ->185411
79070 /*185396*/ OPC_CheckChild1Type, MVT::f32,
79072 /*185399*/ OPC_CheckChild2Type, MVT::f32,
79075 MVT::f32, 2/*#Ops*/, 0, 1,
79154 /*185555*/ /*SwitchType*/ 15, MVT::f32,// ->185572
79155 /*185557*/ OPC_CheckChild1Type, MVT::f32,
79157 /*185560*/ OPC_CheckChild2Type, MVT::f32,
79160 MVT::f32, 2/*#Ops*/, 0, 1,
79232 MVT::f32, 1/*#Ops*/, 0,
79244 /*185723*/ /*SwitchType*/ 9, MVT::f32,// ->185734
79245 /*185725*/ OPC_CheckChild1Type, MVT::f32,
79247 MVT::f32, 1/*#Ops*/, 0,
79307 /*185839*/ /*SwitchType*/ 9, MVT::f32,// ->185850
79308 /*185841*/ OPC_CheckChild1Type, MVT::f32,
79310 MVT::f32, 1/*#Ops*/, 0,
79329 /*185879*/ /*SwitchType*/ 9, MVT::f32,// ->185890
79330 /*185881*/ OPC_CheckChild1Type, MVT::f32,
79332 MVT::f32, 1/*#Ops*/, 0,
79386 /*185983*/ OPC_SwitchType /*2 cases */, 41, MVT::f32,// ->186027
79390 MVT::f32, 1/*#Ops*/, 0,
79401 MVT::f32, 1/*#Ops*/, 3,
79415 /*186044*/ OPC_SwitchType /*3 cases */, 24, MVT::f32,// ->186071
79419 MVT::f32, 1/*#Ops*/, 0,
79426 MVT::f32, 1/*#Ops*/, 0,
79456 /*186116*/ OPC_SwitchType /*3 cases */, 24, MVT::f32,// ->186143
79460 MVT::f32, 1/*#Ops*/, 0,
79467 MVT::f32, 1/*#Ops*/, 0,
79497 /*186188*/ OPC_SwitchType /*3 cases */, 24, MVT::f32,// ->186215
79501 MVT::f32, 1/*#Ops*/, 0,
79508 MVT::f32, 1/*#Ops*/, 0,
79538 /*186260*/ OPC_SwitchType /*3 cases */, 24, MVT::f32,// ->186287
79542 MVT::f32, 1/*#Ops*/, 0,
79549 MVT::f32, 1/*#Ops*/, 0,
84436 /*195680*/ /*SwitchType*/ 32, MVT::f32,// ->195714
84441 MVT::f32, 4/*#Ops*/, 2, 3, 4, 5,
84448 MVT::f32, 4/*#Ops*/, 2, 3, 4, 5,
84496 /*195799*/ OPC_SwitchType /*3 cases */, 8, MVT::f32,// ->195810
84499 MVT::f32, 1/*#Ops*/, 1,
84535 /*195869*/ /*SwitchType*/ 28, MVT::f32,// ->195899
84540 MVT::f32, 2/*#Ops*/, 2, 3,
84547 MVT::f32, 2/*#Ops*/, 2, 3,
93256 /*212162*/ /*SwitchType*/ 16, MVT::f32,// ->212180
93261 MVT::f32, 3/*#Ops*/, 0, 1, 4,
93953 /*213595*/ /*SwitchType*/ 63, MVT::f32,// ->213660
94022 /*213730*/ OPC_SwitchType /*2 cases */, 21, MVT::f32,// ->213754
94051 /*213782*/ OPC_SwitchType /*2 cases */, 21, MVT::f32,// ->213806
94080 /*213834*/ OPC_SwitchType /*2 cases */, 21, MVT::f32,// ->213858
94109 /*213886*/ OPC_SwitchType /*2 cases */, 21, MVT::f32,// ->213910
94155 /*213967*/ OPC_CheckChild0Type, MVT::f32,
94265 /*214173*/ /*SwitchType*/ 63, MVT::f32,// ->214238
94334 /*214308*/ OPC_SwitchType /*2 cases */, 21, MVT::f32,// ->214332
94363 /*214360*/ OPC_SwitchType /*2 cases */, 21, MVT::f32,// ->214384
94392 /*214412*/ OPC_SwitchType /*2 cases */, 21, MVT::f32,// ->214436
94421 /*214464*/ OPC_SwitchType /*2 cases */, 21, MVT::f32,// ->214488
94467 /*214545*/ OPC_CheckChild0Type, MVT::f32,
95039 /*215671*/ OPC_CheckChild0Type, MVT::f32,
95402 /*216341*/ OPC_CheckChild0Type, MVT::f32,
99261 /*223674*/ OPC_CheckChild0Type, MVT::f32,
99298 /*223740*/ OPC_CheckChild0Type, MVT::f32,
99328 /*223792*/ OPC_CheckChild0Type, MVT::f32,
99395 /*223918*/ OPC_CheckChild0Type, MVT::f32,
99462 /*224044*/ OPC_CheckChild0Type, MVT::f32,
100604 /*225979*/ OPC_CheckChild0Type, MVT::f32,
101326 /*227162*/ OPC_CheckType, MVT::f32,
101329 MVT::f32, 2/*#Ops*/, 0, 1,
101837 /*228085*/ OPC_CheckChild0Type, MVT::f32,
101884 /*228186*/ OPC_CheckChild0Type, MVT::f32,
102019 /*228444*/ OPC_CheckType, MVT::f32,
102026 MVT::f32, 4/*#Ops*/, 3, 2, 6, 7,
102054 /*228515*/ OPC_CheckType, MVT::f32,
102061 MVT::f32, 4/*#Ops*/, 3, 0, 6, 7,
102079 /*228569*/ OPC_CheckType, MVT::f32,
102083 MVT::f32, 4/*#Ops*/, 3, 0, 1, 4,
102125 /*228652*/ OPC_CheckType, MVT::f32,
102129 MVT::f32, 4/*#Ops*/, 3, 2, 0, 4,
102169 /*228729*/ OPC_CheckType, MVT::f32,
102172 MVT::f32, 4/*#Ops*/, 3, 2, 0, 4,
102211 /*228804*/ OPC_CheckType, MVT::f32,
102215 MVT::f32, 4/*#Ops*/, 3, 2, 0, 4,
102254 /*228878*/ OPC_CheckType, MVT::f32,
102258 MVT::f32, 4/*#Ops*/, 3, 0, 1, 4,
102298 /*228956*/ OPC_CheckType, MVT::f32,
102301 MVT::f32, 4/*#Ops*/, 3, 0, 1, 4,
102335 /*229023*/ OPC_CheckType, MVT::f32,
102343 MVT::f32, 4/*#Ops*/, 3, 0, 6, 7,
102365 /*229085*/ OPC_CheckType, MVT::f32,
102373 MVT::f32, 4/*#Ops*/, 3, 2, 6, 7,
102387 /*229132*/ OPC_CheckType, MVT::f32,
102391 MVT::f32, 4/*#Ops*/, 3, 2, 0, 4,
102429 /*229207*/ OPC_CheckType, MVT::f32,
102437 MVT::f32, 4/*#Ops*/, 3, 2, 6, 7,
102455 /*229260*/ OPC_CheckType, MVT::f32,
102463 MVT::f32, 4/*#Ops*/, 3, 0, 6, 7,
102483 /*229316*/ OPC_CheckType, MVT::f32,
102487 MVT::f32, 4/*#Ops*/, 3, 0, 1, 4,
102522 /*229385*/ OPC_CheckType, MVT::f32,
102530 MVT::f32, 4/*#Ops*/, 3, 2, 6, 7,
102547 /*229437*/ OPC_CheckType, MVT::f32,
102555 MVT::f32, 4/*#Ops*/, 3, 0, 6, 7,
102574 /*229496*/ /*SwitchType*/ 9, MVT::f32,// ->229507
102576 MVT::f32, 3/*#Ops*/, 0, 1, 2,
102603 /*229552*/ /*SwitchType*/ 9, MVT::f32,// ->229563
102605 MVT::f32, 3/*#Ops*/, 0, 1, 2,
102622 /*229591*/ /*SwitchType*/ 11, MVT::f32,// ->229604
102625 MVT::f32, 3/*#Ops*/, 0, 1, 2,
102648 /*229641*/ /*SwitchType*/ 11, MVT::f32,// ->229654
102651 MVT::f32, 3/*#Ops*/, 0, 1, 2,
102675 /*229692*/ /*SwitchType*/ 9, MVT::f32,// ->229703
102677 MVT::f32, 3/*#Ops*/, 0, 1, 2,
102696 /*229733*/ /*SwitchType*/ 11, MVT::f32,// ->229746
102699 MVT::f32, 3/*#Ops*/, 0, 1, 2,
103213 /*230734*/ OPC_CheckChild0Type, MVT::f32,
103264 /*230858*/ OPC_CheckChild0Type, MVT::f32,
103318 /*230984*/ OPC_SwitchType /*2 cases */, 66, MVT::f32,// ->231053
103367 /*231104*/ OPC_CheckChild0Type, MVT::f32,
103420 /*231226*/ OPC_CheckChild0Type, MVT::f32,
103471 /*231349*/ OPC_SwitchType /*2 cases */, 65, MVT::f32,// ->231417
103573 /*231579*/ OPC_CheckChild0Type, MVT::f32,
103625 /*231702*/ OPC_CheckChild0Type, MVT::f32,
103717 /*231910*/ OPC_CheckType, MVT::f32,
103722 MVT::f32, 0/*#Ops*/, // Results = #6
103727 MVT::f32, 3/*#Ops*/, 6, 7, 8, // Results = #9
103729 MVT::f32, 1/*#Ops*/, 9,
103736 MVT::f32, 0/*#Ops*/, // Results = #6
103741 MVT::f32, 3/*#Ops*/, 6, 7, 8, // Results = #9
103743 MVT::f32, 1/*#Ops*/, 9,
103750 /*231998*/ OPC_CheckType, MVT::f32,
103755 MVT::f32, 0/*#Ops*/, // Results = #6
103760 MVT::f32, 3/*#Ops*/, 6, 7, 8, // Results = #9
103762 MVT::f32, 1/*#Ops*/, 9,
103769 MVT::f32, 0/*#Ops*/, // Results = #6
103774 MVT::f32, 3/*#Ops*/, 6, 7, 8, // Results = #9
103776 MVT::f32, 1/*#Ops*/, 9,
103885 /*232356*/ OPC_CheckType, MVT::f32,
103890 MVT::f32, 0/*#Ops*/, // Results = #4
103895 MVT::f32, 3/*#Ops*/, 4, 5, 6, // Results = #7
103897 MVT::f32, 1/*#Ops*/, 7,
103904 MVT::f32, 0/*#Ops*/, // Results = #4
103909 MVT::f32, 3/*#Ops*/, 4, 5, 6, // Results = #7
103911 MVT::f32, 1/*#Ops*/, 7,
103918 /*232440*/ OPC_CheckType, MVT::f32,
103923 MVT::f32, 0/*#Ops*/, // Results = #4
103928 MVT::f32, 3/*#Ops*/, 4, 5, 6, // Results = #7
103930 MVT::f32, 1/*#Ops*/, 7,
103937 MVT::f32, 0/*#Ops*/, // Results = #4
103942 MVT::f32, 3/*#Ops*/, 4, 5, 6, // Results = #7
103944 MVT::f32, 1/*#Ops*/, 7,
104059 /*232793*/ /*SwitchType*/ 9, MVT::f32,// ->232804
104062 MVT::f32, 1/*#Ops*/, 0,
104080 /*232831*/ /*SwitchType*/ 9, MVT::f32,// ->232842
104083 MVT::f32, 1/*#Ops*/, 0,
104148 /*232952*/ OPC_CheckType, MVT::f32,
104165 MVT::f32, 2/*#Ops*/, 11, 12, // Results = #13
104167 MVT::f32, 1/*#Ops*/, 13,
104185 MVT::f32, 2/*#Ops*/, 11, 12, // Results = #13
104187 MVT::f32, 1/*#Ops*/, 13,
104242 /*233227*/ OPC_CheckType, MVT::f32,
104265 MVT::f32, 2/*#Ops*/, 15, 16, // Results = #17
104267 MVT::f32, 1/*#Ops*/, 17,
104291 MVT::f32, 2/*#Ops*/, 15, 16, // Results = #17
104293 MVT::f32, 1/*#Ops*/, 17,
104355 /*233582*/ /*SwitchType*/ 124, MVT::f32,// ->233708
104372 MVT::f32, 2/*#Ops*/, 9, 10, // Results = #11
104374 MVT::f32, 1/*#Ops*/, 11,
104392 MVT::f32, 2/*#Ops*/, 9, 10, // Results = #11
104394 MVT::f32, 1/*#Ops*/, 11,
104451 /*233851*/ OPC_CheckType, MVT::f32,
104474 MVT::f32, 2/*#Ops*/, 13, 14, // Results = #15
104476 MVT::f32, 1/*#Ops*/, 15,
104500 MVT::f32, 2/*#Ops*/, 13, 14, // Results = #15
104502 MVT::f32, 1/*#Ops*/, 15,
104576 /*234217*/ /*SwitchType*/ 9, MVT::f32,// ->234228
104579 MVT::f32, 1/*#Ops*/, 0,
104597 /*234255*/ /*SwitchType*/ 9, MVT::f32,// ->234266
104600 MVT::f32, 1/*#Ops*/, 0,
104702 /*234441*/ OPC_CheckType, MVT::f32,
104707 MVT::f32, 1/*#Ops*/, 2,
104720 /*234478*/ OPC_CheckType, MVT::f32,
104725 MVT::f32, 1/*#Ops*/, 2,
104739 /*234517*/ /*SwitchType*/ 10, MVT::f32,// ->234529
104742 MVT::f32, 2/*#Ops*/, 0, 1,
104817 /*234674*/ /*SwitchType*/ 13, MVT::f32,// ->234689
104821 MVT::f32, 2/*#Ops*/, 0, 2,
104843 /*234726*/ /*SwitchType*/ 13, MVT::f32,// ->234741
104847 MVT::f32, 2/*#Ops*/, 0, 2,
104872 /*234784*/ /*SwitchType*/ 13, MVT::f32,// ->234799
104876 MVT::f32, 2/*#Ops*/, 0, 2,
104898 /*234836*/ /*SwitchType*/ 13, MVT::f32,// ->234851
104902 MVT::f32, 2/*#Ops*/, 0, 2,
104924 /*234885*/ /*SwitchType*/ 10, MVT::f32,// ->234897
104927 MVT::f32, 2/*#Ops*/, 0, 1,
104999 /*235027*/ OPC_CheckType, MVT::f32,
105003 MVT::f32, 3/*#Ops*/, 0, 1, 3,
105054 /*235124*/ OPC_CheckType, MVT::f32,
105058 MVT::f32, 3/*#Ops*/, 2, 0, 3,
105089 /*235189*/ /*SwitchType*/ 10, MVT::f32,// ->235201
105092 MVT::f32, 2/*#Ops*/, 0, 1,
105252 /*235497*/ OPC_CheckChild0Type, MVT::f32,
105297 /*235611*/ OPC_CheckChild0Type, MVT::f32,
105408 /*235851*/ /*SwitchType*/ 10, MVT::f32,// ->235863
105411 MVT::f32, 2/*#Ops*/, 0, 1,
105432 /*235897*/ /*SwitchType*/ 11, MVT::f32,// ->235910
105435 MVT::f32, 3/*#Ops*/, 0, 1, 2,
105454 /*235939*/ /*SwitchType*/ 9, MVT::f32,// ->235950
105457 MVT::f32, 1/*#Ops*/, 0,
105511 /*236044*/ /*SwitchType*/ 8, MVT::f32,// ->236054
105513 MVT::f32, 2/*#Ops*/, 0, 1,
105530 /*236079*/ /*SwitchType*/ 9, MVT::f32,// ->236090
105533 MVT::f32, 1/*#Ops*/, 0,
105623 /*236251*/ /*SwitchType*/ 6, MVT::f32,// ->236259
105625 MVT::f32, 0/*#Ops*/,
105645 /*236289*/ /*SwitchType*/ 41, MVT::f32,// ->236332
105652 MVT::f32, 1/*#Ops*/, 2,
105661 MVT::f32, 2/*#Ops*/, 2, 3,
105706 /*236414*/ /*SwitchType*/ 9, MVT::f32,// ->236425
105709 MVT::f32, 1/*#Ops*/, 0,
105714 /*236427*/ OPC_CheckChild0Type, MVT::f32,
105748 /*236488*/ OPC_CheckChild0Type, MVT::f32,
105755 /*236500*/ /*SwitchType*/ 9, MVT::f32,// ->236511
105758 MVT::f32, 1/*#Ops*/, 0,
105809 /*236595*/ /*SwitchType*/ 9, MVT::f32,// ->236606
105812 MVT::f32, 1/*#Ops*/, 0,
105860 /*236689*/ /*SwitchType*/ 9, MVT::f32,// ->236700
105863 MVT::f32, 1/*#Ops*/, 0,
105911 /*236783*/ /*SwitchType*/ 9, MVT::f32,// ->236794
105914 MVT::f32, 1/*#Ops*/, 0,
105962 /*236877*/ /*SwitchType*/ 9, MVT::f32,// ->236888
105965 MVT::f32, 1/*#Ops*/, 0,
106013 /*236971*/ /*SwitchType*/ 9, MVT::f32,// ->236982
106016 MVT::f32, 1/*#Ops*/, 0,
106064 /*237065*/ /*SwitchType*/ 9, MVT::f32,// ->237076
106067 MVT::f32, 1/*#Ops*/, 0,
106115 /*237159*/ /*SwitchType*/ 9, MVT::f32,// ->237170
106118 MVT::f32, 1/*#Ops*/, 0,
106167 /*237255*/ /*SwitchType*/ 10, MVT::f32,// ->237267
106170 MVT::f32, 2/*#Ops*/, 0, 1,
106224 /*237368*/ /*SwitchType*/ 10, MVT::f32,// ->237380
106227 MVT::f32, 2/*#Ops*/, 0, 1,
106281 /*237481*/ /*SwitchType*/ 10, MVT::f32,// ->237493
106284 MVT::f32, 2/*#Ops*/, 0, 1,
106338 /*237594*/ /*SwitchType*/ 10, MVT::f32,// ->237606
106341 MVT::f32, 2/*#Ops*/, 0, 1,
106395 /*237707*/ /*SwitchType*/ 10, MVT::f32,// ->237719
106398 MVT::f32, 2/*#Ops*/, 0, 1,
106446 /*237808*/ /*SwitchType*/ 9, MVT::f32,// ->237819
106449 MVT::f32, 1/*#Ops*/, 0,
106467 /*237847*/ /*SwitchType*/ 9, MVT::f32,// ->237858
106470 MVT::f32, 1/*#Ops*/, 0,
106482 /*237874*/ OPC_SwitchType /*6 cases */, 7, MVT::f32,// ->237884
106484 MVT::f32, 1/*#Ops*/, 0,
106516 /*237935*/ OPC_SwitchType /*5 cases */, 8, MVT::f32,// ->237946
106518 MVT::f32, 2/*#Ops*/, 0, 1,
106544 /*237991*/ OPC_SwitchType /*6 cases */, 7, MVT::f32,// ->238001
106546 MVT::f32, 1/*#Ops*/, 0,
106578 /*238052*/ OPC_SwitchType /*5 cases */, 8, MVT::f32,// ->238063
106580 MVT::f32, 2/*#Ops*/, 0, 1,
106991 MVT::f32, 2/*#Ops*/, 0, 2, // Results = #3
107001 MVT::f32, 2/*#Ops*/, 0, 2, // Results = #3
107011 MVT::f32, 2/*#Ops*/, 0, 2, // Results = #3
107021 MVT::f32, 2/*#Ops*/, 0, 2, // Results = #3
107108 /*239359*/ /*SwitchType*/ 15|128,1/*143*/, MVT::f32,// ->239505
107237 /*239675*/ OPC_CheckChild0Type, MVT::f32,
109854 /*245352*/ OPC_CheckType, MVT::f32,
109964 /*245616*/ OPC_CheckType, MVT::f32,
110051 /*245838*/ OPC_SwitchType /*3 cases */, 67, MVT::f32,// ->245908
110176 /*246130*/ OPC_CheckChild1Type, MVT::f32,
110686 /*247234*/ OPC_SwitchType /*3 cases */, 23, MVT::f32,// ->247260
110755 /*247365*/ OPC_CheckChild0Type, MVT::f32,
gen/lib/Target/AArch64/AArch64GenFastISel.inc 1027 if (RetVT.SimpleTy != MVT::f32)
1064 case MVT::f32: return fastEmit_AArch64ISD_FRECPE_MVT_f32_r(RetVT, Op0, Op0IsKill);
1077 if (RetVT.SimpleTy != MVT::f32)
1114 case MVT::f32: return fastEmit_AArch64ISD_FRSQRTE_MVT_f32_r(RetVT, Op0, Op0IsKill);
1450 if (RetVT.SimpleTy != MVT::f32)
1470 case MVT::f32: return fastEmit_AArch64ISD_SITOF_MVT_f32_r(RetVT, Op0, Op0IsKill);
1564 if (RetVT.SimpleTy != MVT::f32)
1584 case MVT::f32: return fastEmit_AArch64ISD_UITOF_MVT_f32_r(RetVT, Op0, Op0IsKill);
2714 if (RetVT.SimpleTy != MVT::f32)
2779 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
2802 if (RetVT.SimpleTy != MVT::f32)
2867 case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0, Op0IsKill);
2890 if (RetVT.SimpleTy != MVT::f32)
2955 case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
2978 if (RetVT.SimpleTy != MVT::f32)
3043 case MVT::f32: return fastEmit_ISD_FNEARBYINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
3066 if (RetVT.SimpleTy != MVT::f32)
3131 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
3160 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(Op0, Op0IsKill);
3190 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill);
3225 case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(Op0, Op0IsKill);
3244 case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
3368 case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
3495 case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
3518 if (RetVT.SimpleTy != MVT::f32)
3583 case MVT::f32: return fastEmit_ISD_FRINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
3606 if (RetVT.SimpleTy != MVT::f32)
3671 case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
3694 if (RetVT.SimpleTy != MVT::f32)
3759 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
3782 if (RetVT.SimpleTy != MVT::f32)
3847 case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0, Op0IsKill);
3884 case MVT::f32: return fastEmit_ISD_LLROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
3949 case MVT::f32: return fastEmit_ISD_LROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
3981 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill);
4011 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(Op0, Op0IsKill);
4146 case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill);
4176 case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f32_r(Op0, Op0IsKill);
4814 case MVT::f32: return fastEmit_AArch64ISD_FCMEQ_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4902 case MVT::f32: return fastEmit_AArch64ISD_FCMGE_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4990 case MVT::f32: return fastEmit_AArch64ISD_FCMGT_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
5034 case MVT::f32: return fastEmit_AArch64ISD_FCMP_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
5043 if (RetVT.SimpleTy != MVT::f32)
5074 case MVT::f32: return fastEmit_AArch64ISD_FRECPS_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
5086 if (RetVT.SimpleTy != MVT::f32)
5117 case MVT::f32: return fastEmit_AArch64ISD_FRSQRTS_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
6168 if (RetVT.SimpleTy != MVT::f32)
6260 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
6286 if (RetVT.SimpleTy != MVT::f32)
6351 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
6374 if (RetVT.SimpleTy != MVT::f32)
6445 case MVT::f32: return fastEmit_ISD_FMAXIMUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
6469 if (RetVT.SimpleTy != MVT::f32)
6540 case MVT::f32: return fastEmit_ISD_FMAXNUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
6564 if (RetVT.SimpleTy != MVT::f32)
6635 case MVT::f32: return fastEmit_ISD_FMINIMUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
6659 if (RetVT.SimpleTy != MVT::f32)
6730 case MVT::f32: return fastEmit_ISD_FMINNUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
6754 if (RetVT.SimpleTy != MVT::f32)
6819 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
6842 if (RetVT.SimpleTy != MVT::f32)
6907 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
7871 if (RetVT.SimpleTy != MVT::f32)
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 5180 /* 0 */ MVT::f32, MVT::i32, MVT::Other,
gen/lib/Target/AMDGPU/AMDGPUGenCallingConv.inc 78 LocVT == MVT::f32 ||
94 LocVT == MVT::f32 ||
160 if (LocVT == MVT::f32 ||
176 if (LocVT == MVT::f32 ||
223 LocVT == MVT::f32 ||
255 if (LocVT == MVT::f32 ||
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc30342 /* 63998*/ OPC_SwitchType /*2 cases */, 67, MVT::f32,// ->64068
30349 MVT::f32, 4/*#Ops*/, 2, 3, 4, 5,
30359 MVT::f32, 4/*#Ops*/, 2, 3, 4, 5,
30368 MVT::f32, 4/*#Ops*/, 2, 3, 4, 5,
30439 /* 64207*/ OPC_SwitchType /*2 cases */, 20, MVT::f32,// ->64230
30445 MVT::f32, 4/*#Ops*/, 1, 2, 3, 4,
30465 /* 64263*/ OPC_CheckType, MVT::f32,
30471 MVT::f32, 3/*#Ops*/, 2, 3, 4,
30479 /* 64292*/ OPC_CheckType, MVT::f32,
30485 MVT::f32, 3/*#Ops*/, 2, 3, 4,
30490 /* 64315*/ OPC_SwitchType /*2 cases */, 23, MVT::f32,// ->64341
30497 MVT::f32, 5/*#Ops*/, 2, 3, 5, 6, 4,
30513 /* 64370*/ OPC_SwitchType /*2 cases */, 23, MVT::f32,// ->64396
30520 MVT::f32, 5/*#Ops*/, 2, 3, 5, 6, 4,
32201 /* 68190*/ OPC_CheckChild1Type, MVT::f32,
32413 /* 68715*/ OPC_CheckChild1Type, MVT::f32,
32740 /* 69436*/ OPC_CheckChild1Type, MVT::f32,
32755 /* 69465*/ OPC_CheckChild1Type, MVT::f32,
33050 /* 70041*/ OPC_CheckChild1Type, MVT::f32,
33312 /* 70616*/ OPC_CheckChild1Type, MVT::f32,
33527 /* 71093*/ /*SwitchType*/ 61, MVT::f32,// ->71156
33533 MVT::f32, 4/*#Ops*/, 0, 4, 5, 6,
33542 MVT::f32, 4/*#Ops*/, 0, 4, 5, 6,
33549 MVT::f32, 4/*#Ops*/, 0, 1, 4, 5,
34319 /* 72825*/ OPC_CheckChild1Type, MVT::f32,
34377 /* 72940*/ OPC_CheckChild1Type, MVT::f32,
34454 MVT::f32, 3/*#Ops*/, 4, 2, 1,
34473 MVT::f32, 3/*#Ops*/, 0, 2, 1,
34480 MVT::f32, 3/*#Ops*/, 0, 2, 1,
34499 MVT::f32, 4/*#Ops*/, 0, 1, 3, 2,
34508 /* 73186*/ OPC_SwitchType /*2 cases */, 12, MVT::f32,// ->73201
34510 /* 73190*/ OPC_CheckType, MVT::f32,
34513 MVT::f32, 1/*#Ops*/, 0,
34527 /* 73218*/ OPC_SwitchType /*3 cases */, 15, MVT::f32,// ->73236
34528 /* 73221*/ OPC_CheckChild1Type, MVT::f32,
34531 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
34560 MVT::f32, 8/*#Ops*/, 4, 3, 8, 7, 10, 9, 5, 6,
34572 MVT::f32, 8/*#Ops*/, 4, 3, 8, 7, 10, 9, 5, 6,
34584 MVT::f32, 8/*#Ops*/, 4, 3, 8, 7, 10, 9, 5, 6,
34596 MVT::f32, 8/*#Ops*/, 4, 3, 8, 7, 10, 9, 5, 6,
34602 /* 73399*/ OPC_SwitchType /*2 cases */, 31, MVT::f32,// ->73433
34603 /* 73402*/ OPC_CheckChild1Type, MVT::f32,
34605 /* 73405*/ OPC_CheckChild2Type, MVT::f32,
34607 /* 73408*/ OPC_CheckChild3Type, MVT::f32,
34612 MVT::f32, 8/*#Ops*/, 4, 3, 8, 7, 10, 9, 5, 6,
34634 /* 73477*/ OPC_SwitchType /*3 cases */, 21, MVT::f32,// ->73501
34635 /* 73480*/ OPC_CheckChild1Type, MVT::f32,
34640 MVT::f32, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
34666 /* 73555*/ OPC_SwitchType /*3 cases */, 15, MVT::f32,// ->73573
34667 /* 73558*/ OPC_CheckChild1Type, MVT::f32,
34670 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
34692 /* 73615*/ OPC_SwitchType /*3 cases */, 15, MVT::f32,// ->73633
34693 /* 73618*/ OPC_CheckChild1Type, MVT::f32,
34696 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
34718 /* 73675*/ OPC_SwitchType /*2 cases */, 15, MVT::f32,// ->73693
34719 /* 73678*/ OPC_CheckChild1Type, MVT::f32,
34722 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
34737 /* 73718*/ OPC_SwitchType /*2 cases */, 15, MVT::f32,// ->73736
34738 /* 73721*/ OPC_CheckChild1Type, MVT::f32,
34741 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
34763 /* 73779*/ /*SwitchType*/ 15, MVT::f32,// ->73796
34764 /* 73781*/ OPC_CheckChild1Type, MVT::f32,
34767 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
34782 /* 73821*/ OPC_CheckChild1Type, MVT::f32,
34783 /* 73823*/ OPC_CheckType, MVT::f32,
34787 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
34796 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
34802 /* 73865*/ OPC_SwitchType /*2 cases */, 17, MVT::f32,// ->73885
34803 /* 73868*/ OPC_CheckChild1Type, MVT::f32,
34807 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
34825 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
35824 /* 75943*/ OPC_CheckType, MVT::f32,
35834 MVT::f32, 9/*#Ops*/, 1, 2, 6, 7, 8, 9, 10, 11, 12,
35855 /* 76008*/ OPC_CheckType, MVT::f32,
35865 MVT::f32, 10/*#Ops*/, 2, 1, 3, 7, 8, 9, 10, 11, 12, 13,
35889 /* 76081*/ OPC_CheckType, MVT::f32,
35899 MVT::f32, 10/*#Ops*/, 2, 1, 3, 7, 8, 9, 10, 11, 12, 13,
35920 /* 76148*/ OPC_CheckType, MVT::f32,
35935 MVT::f32, 10/*#Ops*/, 11, 1, 4, 12, 13, 14, 15, 16, 17, 18,
36991 /* 78760*/ OPC_CheckChild1Type, MVT::f32,
38435 /* 81998*/ OPC_CheckType, MVT::f32,
38444 MVT::f32, 8/*#Ops*/, 1, 2, 5, 6, 7, 8, 9, 10,
38461 /* 82052*/ OPC_CheckType, MVT::f32,
38470 MVT::f32, 9/*#Ops*/, 2, 1, 3, 6, 7, 8, 9, 10, 11,
38490 /* 82114*/ OPC_CheckType, MVT::f32,
38499 MVT::f32, 9/*#Ops*/, 2, 1, 3, 6, 7, 8, 9, 10, 11,
38516 /* 82170*/ OPC_CheckType, MVT::f32,
38530 MVT::f32, 9/*#Ops*/, 10, 1, 4, 11, 12, 13, 14, 15, 16,
39967 /* 85817*/ OPC_CheckType, MVT::f32,
39976 MVT::f32, 8/*#Ops*/, 1, 2, 5, 6, 7, 8, 9, 10,
39993 /* 85871*/ OPC_CheckType, MVT::f32,
40002 MVT::f32, 9/*#Ops*/, 2, 1, 3, 6, 7, 8, 9, 10, 11,
40022 /* 85933*/ OPC_CheckType, MVT::f32,
40031 MVT::f32, 9/*#Ops*/, 2, 1, 3, 6, 7, 8, 9, 10, 11,
40048 /* 85989*/ OPC_CheckType, MVT::f32,
40062 MVT::f32, 9/*#Ops*/, 10, 1, 4, 11, 12, 13, 14, 15, 16,
41214 /* 88941*/ OPC_CheckChild1Type, MVT::f32,
43226 /* 93481*/ OPC_CheckChild1Type, MVT::f32,
50350 /*108201*/ /*SwitchType*/ 17, MVT::f32,// ->108220
50354 MVT::f32, 5/*#Ops*/, 6, 5, 4, 3, 0,
50361 /*108229*/ OPC_CheckChild0Type, MVT::f32,
54679 /*119876*/ OPC_CheckChild0Type, MVT::f32,
54902 /*120225*/ OPC_CheckChild3Type, MVT::f32,
54956 /*120322*/ OPC_CheckChild3Type, MVT::f32,
58148 /*127419*/ OPC_CheckChild0Type, MVT::f32,
58167 /*127462*/ OPC_CheckChild0Type, MVT::f32,
58225 /*127614*/ OPC_CheckChild0Type, MVT::f32,
58267 /*127720*/ OPC_CheckType, MVT::f32,
58283 /*127750*/ OPC_CheckType, MVT::f32,
58295 /*127773*/ OPC_CheckType, MVT::f32,
58316 /*127817*/ OPC_CheckChild0Type, MVT::f32,
58883 /*128953*/ /*SwitchType*/ 66|128,8/*1090*/, MVT::f32,// ->130046
58890 MVT::f32, 3/*#Ops*/, 0, 2, 3,
58897 MVT::f32, 2/*#Ops*/, 0, 1,
58904 MVT::f32, 2/*#Ops*/, 0, 1,
58911 MVT::f32, 2/*#Ops*/, 0, 1,
58921 MVT::f32, 3/*#Ops*/, 0, 2, 3,
58928 MVT::f32, 2/*#Ops*/, 0, 1,
58935 MVT::f32, 2/*#Ops*/, 0, 1,
58942 MVT::f32, 2/*#Ops*/, 0, 1,
58949 MVT::f32, 2/*#Ops*/, 0, 1,
58959 MVT::f32, 3/*#Ops*/, 0, 2, 3,
58966 MVT::f32, 2/*#Ops*/, 0, 1,
58973 MVT::f32, 2/*#Ops*/, 0, 1,
58980 MVT::f32, 2/*#Ops*/, 0, 1,
58987 MVT::f32, 2/*#Ops*/, 0, 1,
58994 MVT::f32, 2/*#Ops*/, 0, 1,
59001 MVT::f32, 2/*#Ops*/, 0, 1,
59008 MVT::f32, 2/*#Ops*/, 0, 1,
59015 MVT::f32, 2/*#Ops*/, 0, 1,
59025 MVT::f32, 3/*#Ops*/, 0, 2, 3,
59032 MVT::f32, 2/*#Ops*/, 0, 1,
59039 MVT::f32, 2/*#Ops*/, 0, 1,
59046 MVT::f32, 2/*#Ops*/, 0, 1,
59053 MVT::f32, 2/*#Ops*/, 0, 1,
59060 MVT::f32, 2/*#Ops*/, 0, 1,
59067 MVT::f32, 2/*#Ops*/, 0, 1,
59074 MVT::f32, 2/*#Ops*/, 0, 1,
59081 MVT::f32, 2/*#Ops*/, 0, 1,
59088 MVT::f32, 2/*#Ops*/, 0, 1,
59095 MVT::f32, 2/*#Ops*/, 0, 1,
59102 MVT::f32, 2/*#Ops*/, 0, 1,
59109 MVT::f32, 2/*#Ops*/, 0, 1,
59116 MVT::f32, 2/*#Ops*/, 0, 1,
59123 MVT::f32, 2/*#Ops*/, 0, 1,
59130 MVT::f32, 2/*#Ops*/, 0, 1,
59137 MVT::f32, 2/*#Ops*/, 0, 1,
59147 MVT::f32, 2/*#Ops*/, 0, 1,
59154 MVT::f32, 2/*#Ops*/, 0, 1,
59161 MVT::f32, 2/*#Ops*/, 0, 1,
59171 MVT::f32, 2/*#Ops*/, 0, 1,
59178 MVT::f32, 2/*#Ops*/, 0, 1,
59185 MVT::f32, 2/*#Ops*/, 0, 1,
59192 MVT::f32, 2/*#Ops*/, 0, 1,
59199 MVT::f32, 2/*#Ops*/, 0, 1,
59209 MVT::f32, 2/*#Ops*/, 0, 1,
59216 MVT::f32, 2/*#Ops*/, 0, 1,
59223 MVT::f32, 2/*#Ops*/, 0, 1,
59230 MVT::f32, 2/*#Ops*/, 0, 1,
59237 MVT::f32, 2/*#Ops*/, 0, 1,
59244 MVT::f32, 2/*#Ops*/, 0, 1,
59251 MVT::f32, 2/*#Ops*/, 0, 1,
59258 MVT::f32, 2/*#Ops*/, 0, 1,
59265 MVT::f32, 2/*#Ops*/, 0, 1,
59272 MVT::f32, 2/*#Ops*/, 0, 1,
59279 MVT::f32, 2/*#Ops*/, 0, 1,
59286 MVT::f32, 2/*#Ops*/, 0, 1,
59293 MVT::f32, 2/*#Ops*/, 0, 1,
59300 MVT::f32, 2/*#Ops*/, 0, 1,
59307 MVT::f32, 2/*#Ops*/, 0, 1,
59314 MVT::f32, 2/*#Ops*/, 0, 1,
59321 MVT::f32, 2/*#Ops*/, 0, 1,
59328 MVT::f32, 2/*#Ops*/, 0, 1,
59335 MVT::f32, 2/*#Ops*/, 0, 1,
59342 MVT::f32, 2/*#Ops*/, 0, 1,
59349 MVT::f32, 2/*#Ops*/, 0, 1,
59356 MVT::f32, 2/*#Ops*/, 0, 1,
59363 MVT::f32, 2/*#Ops*/, 0, 1,
59370 MVT::f32, 2/*#Ops*/, 0, 1,
59377 MVT::f32, 2/*#Ops*/, 0, 1,
59384 MVT::f32, 2/*#Ops*/, 0, 1,
59391 MVT::f32, 2/*#Ops*/, 0, 1,
59398 MVT::f32, 2/*#Ops*/, 0, 1,
59405 MVT::f32, 2/*#Ops*/, 0, 1,
59412 MVT::f32, 2/*#Ops*/, 0, 1,
59419 MVT::f32, 2/*#Ops*/, 0, 1,
59426 MVT::f32, 2/*#Ops*/, 0, 1,
60900 /*133052*/ OPC_CheckChild0Type, MVT::f32,
62496 /*136657*/ OPC_CheckChild0Type, MVT::f32,
62522 /*136692*/ /*SwitchType*/ 3, MVT::f32,// ->136697
62537 /*136712*/ /*SwitchType*/ 3, MVT::f32,// ->136717
62681 /*136898*/ OPC_SwitchType /*3 cases */, 10, MVT::f32,// ->136911
63514 /*138685*/ OPC_CheckChild0Type, MVT::f32,
63642 /*138936*/ OPC_SwitchType /*2 cases */, 29, MVT::f32,// ->138968
63649 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
63672 /*139014*/ OPC_CheckType, MVT::f32,
63679 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
63691 /*139060*/ OPC_SwitchType /*2 cases */, 29, MVT::f32,// ->139092
63698 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
63725 /*139145*/ OPC_CheckType, MVT::f32,
63732 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
63742 /*139187*/ OPC_CheckType, MVT::f32,
63749 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
63764 /*139237*/ OPC_CheckType, MVT::f32,
63771 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
63782 /*139280*/ OPC_CheckType, MVT::f32,
63789 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
63804 /*139330*/ OPC_CheckType, MVT::f32,
63811 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
63821 /*139372*/ OPC_CheckType, MVT::f32,
63828 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
63843 /*139425*/ OPC_SwitchType /*2 cases */, 29, MVT::f32,// ->139457
63850 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
63873 /*139505*/ OPC_SwitchType /*2 cases */, 29, MVT::f32,// ->139537
63880 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
63914 /*139601*/ OPC_CheckType, MVT::f32,
63921 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
63929 /*139640*/ OPC_CheckType, MVT::f32,
63937 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
63942 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
63951 /*139697*/ OPC_CheckType, MVT::f32,
63958 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
63980 /*139760*/ OPC_CheckType, MVT::f32,
63987 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
63995 /*139799*/ OPC_CheckType, MVT::f32,
64003 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
64008 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
64017 /*139856*/ OPC_CheckType, MVT::f32,
64024 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
64044 /*139915*/ OPC_CheckType, MVT::f32,
64051 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
64065 /*139964*/ OPC_CheckType, MVT::f32,
64072 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
64082 /*140006*/ OPC_CheckType, MVT::f32,
64089 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
64104 /*140056*/ OPC_CheckType, MVT::f32,
64111 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
64122 /*140099*/ OPC_CheckType, MVT::f32,
64129 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
64144 /*140149*/ OPC_CheckType, MVT::f32,
64151 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
64161 /*140191*/ OPC_CheckType, MVT::f32,
64168 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
64191 /*140253*/ OPC_CheckType, MVT::f32,
64198 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
64206 /*140292*/ OPC_CheckType, MVT::f32,
64214 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
64219 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
64228 /*140349*/ OPC_CheckType, MVT::f32,
64235 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
64257 /*140412*/ OPC_CheckType, MVT::f32,
64264 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
64272 /*140451*/ OPC_CheckType, MVT::f32,
64280 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
64285 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
64294 /*140508*/ OPC_CheckType, MVT::f32,
64301 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
64321 /*140567*/ OPC_CheckType, MVT::f32,
64328 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
64342 /*140616*/ OPC_CheckType, MVT::f32,
64349 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
64359 /*140658*/ OPC_CheckType, MVT::f32,
64366 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
64381 /*140708*/ OPC_CheckType, MVT::f32,
64388 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
64399 /*140751*/ OPC_CheckType, MVT::f32,
64406 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
64421 /*140801*/ OPC_CheckType, MVT::f32,
64428 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
64438 /*140843*/ OPC_CheckType, MVT::f32,
64445 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
64459 /*140891*/ OPC_CheckType, MVT::f32,
64466 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
64480 /*140940*/ OPC_CheckType, MVT::f32,
64487 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
64497 /*140982*/ OPC_CheckType, MVT::f32,
64504 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
64519 /*141032*/ OPC_CheckType, MVT::f32,
64526 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
64537 /*141075*/ OPC_CheckType, MVT::f32,
64544 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
64559 /*141125*/ OPC_CheckType, MVT::f32,
64566 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
64576 /*141167*/ OPC_CheckType, MVT::f32,
64583 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
64606 /*141229*/ OPC_CheckType, MVT::f32,
64613 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
64621 /*141268*/ OPC_CheckType, MVT::f32,
64629 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
64634 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
64643 /*141325*/ OPC_CheckType, MVT::f32,
64650 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
64671 /*141385*/ OPC_CheckType, MVT::f32,
64678 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
64686 /*141424*/ OPC_CheckType, MVT::f32,
64694 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
64699 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
64708 /*141481*/ OPC_CheckType, MVT::f32,
64715 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
64736 /*141541*/ OPC_CheckType, MVT::f32,
64743 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
64751 /*141580*/ OPC_CheckType, MVT::f32,
64759 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
64764 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
64773 /*141637*/ OPC_CheckType, MVT::f32,
64780 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
64802 /*141700*/ OPC_CheckType, MVT::f32,
64809 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
64817 /*141739*/ OPC_CheckType, MVT::f32,
64825 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
64830 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
64839 /*141796*/ OPC_CheckType, MVT::f32,
64846 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
66018 /*144556*/ OPC_SwitchType /*2 cases */, 29, MVT::f32,// ->144588
66025 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
66048 /*144636*/ OPC_SwitchType /*2 cases */, 29, MVT::f32,// ->144668
66055 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
66081 /*144723*/ OPC_SwitchType /*2 cases */, 29, MVT::f32,// ->144755
66088 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
66111 /*144803*/ OPC_SwitchType /*2 cases */, 29, MVT::f32,// ->144835
66118 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
66152 /*144899*/ OPC_CheckType, MVT::f32,
66159 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
66167 /*144938*/ OPC_CheckType, MVT::f32,
66175 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
66180 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
66189 /*144995*/ OPC_CheckType, MVT::f32,
66196 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
66217 /*145055*/ OPC_CheckType, MVT::f32,
66224 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
66232 /*145094*/ OPC_CheckType, MVT::f32,
66240 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
66245 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
66254 /*145151*/ OPC_CheckType, MVT::f32,
66261 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
66282 /*145211*/ OPC_CheckType, MVT::f32,
66289 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
66297 /*145250*/ OPC_CheckType, MVT::f32,
66305 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
66310 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
66319 /*145307*/ OPC_CheckType, MVT::f32,
66326 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
66348 /*145370*/ OPC_CheckType, MVT::f32,
66355 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
66363 /*145409*/ OPC_CheckType, MVT::f32,
66371 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
66376 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
66385 /*145466*/ OPC_CheckType, MVT::f32,
66392 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
66412 /*145527*/ OPC_CheckType, MVT::f32,
66419 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
66433 /*145576*/ OPC_CheckType, MVT::f32,
66440 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
66450 /*145618*/ OPC_CheckType, MVT::f32,
66457 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
66472 /*145668*/ OPC_CheckType, MVT::f32,
66479 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
66490 /*145711*/ OPC_CheckType, MVT::f32,
66497 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
66512 /*145761*/ OPC_CheckType, MVT::f32,
66519 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
66529 /*145803*/ OPC_CheckType, MVT::f32,
66536 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
66550 /*145851*/ OPC_CheckType, MVT::f32,
66557 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
66571 /*145900*/ OPC_CheckType, MVT::f32,
66578 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
66588 /*145942*/ OPC_CheckType, MVT::f32,
66595 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
66610 /*145992*/ OPC_CheckType, MVT::f32,
66617 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
66628 /*146035*/ OPC_CheckType, MVT::f32,
66635 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
66650 /*146085*/ OPC_CheckType, MVT::f32,
66657 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
66667 /*146127*/ OPC_CheckType, MVT::f32,
66674 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
66690 /*146181*/ OPC_CheckType, MVT::f32,
66697 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
66711 /*146230*/ OPC_CheckType, MVT::f32,
66718 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
66728 /*146272*/ OPC_CheckType, MVT::f32,
66735 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
66750 /*146322*/ OPC_CheckType, MVT::f32,
66757 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
66768 /*146365*/ OPC_CheckType, MVT::f32,
66775 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
66790 /*146415*/ OPC_CheckType, MVT::f32,
66797 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
66807 /*146457*/ OPC_CheckType, MVT::f32,
66814 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
66838 /*146520*/ OPC_CheckType, MVT::f32,
66845 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
66853 /*146559*/ OPC_CheckType, MVT::f32,
66861 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
66866 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
66875 /*146616*/ OPC_CheckType, MVT::f32,
66882 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
66904 /*146679*/ OPC_CheckType, MVT::f32,
66911 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
66919 /*146718*/ OPC_CheckType, MVT::f32,
66927 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
66932 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
66941 /*146775*/ OPC_CheckType, MVT::f32,
66948 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
66968 /*146834*/ OPC_CheckType, MVT::f32,
66975 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
66989 /*146883*/ OPC_CheckType, MVT::f32,
66996 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
67006 /*146925*/ OPC_CheckType, MVT::f32,
67013 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
67028 /*146975*/ OPC_CheckType, MVT::f32,
67035 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
67046 /*147018*/ OPC_CheckType, MVT::f32,
67053 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
67068 /*147068*/ OPC_CheckType, MVT::f32,
67075 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
67085 /*147110*/ OPC_CheckType, MVT::f32,
67092 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
67115 /*147172*/ OPC_CheckType, MVT::f32,
67122 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
67130 /*147211*/ OPC_CheckType, MVT::f32,
67138 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
67143 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
67152 /*147268*/ OPC_CheckType, MVT::f32,
67159 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
67180 /*147328*/ OPC_CheckType, MVT::f32,
67187 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
67195 /*147367*/ OPC_CheckType, MVT::f32,
67203 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
67208 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
67217 /*147424*/ OPC_CheckType, MVT::f32,
67224 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
68378 /*150151*/ OPC_SwitchType /*4 cases */, 40, MVT::f32,// ->150194
68383 MVT::f32, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
68390 MVT::f32, 6/*#Ops*/, 5, 4, 3, 2, 6, 7,
68475 /*150402*/ OPC_SwitchType /*2 cases */, 29, MVT::f32,// ->150434
68482 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
68505 /*150480*/ OPC_CheckType, MVT::f32,
68512 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
68524 /*150526*/ OPC_SwitchType /*2 cases */, 29, MVT::f32,// ->150558
68531 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
68558 /*150611*/ OPC_CheckType, MVT::f32,
68565 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
68575 /*150653*/ OPC_CheckType, MVT::f32,
68582 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
68597 /*150703*/ OPC_CheckType, MVT::f32,
68604 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
68615 /*150746*/ OPC_CheckType, MVT::f32,
68622 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
68637 /*150796*/ OPC_CheckType, MVT::f32,
68644 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
68654 /*150838*/ OPC_CheckType, MVT::f32,
68661 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
68676 /*150891*/ OPC_SwitchType /*2 cases */, 29, MVT::f32,// ->150923
68683 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
68706 /*150971*/ OPC_SwitchType /*2 cases */, 29, MVT::f32,// ->151003
68713 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
68747 /*151067*/ OPC_CheckType, MVT::f32,
68754 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
68762 /*151106*/ OPC_CheckType, MVT::f32,
68770 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
68775 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
68784 /*151163*/ OPC_CheckType, MVT::f32,
68791 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
68813 /*151226*/ OPC_CheckType, MVT::f32,
68820 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
68828 /*151265*/ OPC_CheckType, MVT::f32,
68836 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
68841 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
68850 /*151322*/ OPC_CheckType, MVT::f32,
68857 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
68877 /*151381*/ OPC_CheckType, MVT::f32,
68884 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
68898 /*151430*/ OPC_CheckType, MVT::f32,
68905 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
68915 /*151472*/ OPC_CheckType, MVT::f32,
68922 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
68937 /*151522*/ OPC_CheckType, MVT::f32,
68944 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
68955 /*151565*/ OPC_CheckType, MVT::f32,
68962 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
68977 /*151615*/ OPC_CheckType, MVT::f32,
68984 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
68994 /*151657*/ OPC_CheckType, MVT::f32,
69001 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
69024 /*151719*/ OPC_CheckType, MVT::f32,
69031 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
69039 /*151758*/ OPC_CheckType, MVT::f32,
69047 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
69052 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
69061 /*151815*/ OPC_CheckType, MVT::f32,
69068 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
69090 /*151878*/ OPC_CheckType, MVT::f32,
69097 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
69105 /*151917*/ OPC_CheckType, MVT::f32,
69113 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
69118 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
69127 /*151974*/ OPC_CheckType, MVT::f32,
69134 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
69154 /*152033*/ OPC_CheckType, MVT::f32,
69161 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
69175 /*152082*/ OPC_CheckType, MVT::f32,
69182 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
69192 /*152124*/ OPC_CheckType, MVT::f32,
69199 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
69214 /*152174*/ OPC_CheckType, MVT::f32,
69221 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
69232 /*152217*/ OPC_CheckType, MVT::f32,
69239 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
69254 /*152267*/ OPC_CheckType, MVT::f32,
69261 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
69271 /*152309*/ OPC_CheckType, MVT::f32,
69278 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
69292 /*152357*/ OPC_CheckType, MVT::f32,
69299 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
69313 /*152406*/ OPC_CheckType, MVT::f32,
69320 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
69330 /*152448*/ OPC_CheckType, MVT::f32,
69337 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
69352 /*152498*/ OPC_CheckType, MVT::f32,
69359 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
69370 /*152541*/ OPC_CheckType, MVT::f32,
69377 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
69392 /*152591*/ OPC_CheckType, MVT::f32,
69399 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
69409 /*152633*/ OPC_CheckType, MVT::f32,
69416 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
69439 /*152695*/ OPC_CheckType, MVT::f32,
69446 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
69454 /*152734*/ OPC_CheckType, MVT::f32,
69462 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
69467 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
69476 /*152791*/ OPC_CheckType, MVT::f32,
69483 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
69504 /*152851*/ OPC_CheckType, MVT::f32,
69511 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
69519 /*152890*/ OPC_CheckType, MVT::f32,
69527 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
69532 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
69541 /*152947*/ OPC_CheckType, MVT::f32,
69548 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
69569 /*153007*/ OPC_CheckType, MVT::f32,
69576 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
69584 /*153046*/ OPC_CheckType, MVT::f32,
69592 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
69597 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
69606 /*153103*/ OPC_CheckType, MVT::f32,
69613 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
69635 /*153166*/ OPC_CheckType, MVT::f32,
69642 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
69650 /*153205*/ OPC_CheckType, MVT::f32,
69658 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
69663 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
69672 /*153262*/ OPC_CheckType, MVT::f32,
69679 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
70851 /*156022*/ OPC_SwitchType /*2 cases */, 29, MVT::f32,// ->156054
70858 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
70881 /*156102*/ OPC_SwitchType /*2 cases */, 29, MVT::f32,// ->156134
70888 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
70914 /*156189*/ OPC_SwitchType /*2 cases */, 29, MVT::f32,// ->156221
70921 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
70944 /*156269*/ OPC_SwitchType /*2 cases */, 29, MVT::f32,// ->156301
70951 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
70985 /*156365*/ OPC_CheckType, MVT::f32,
70992 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
71000 /*156404*/ OPC_CheckType, MVT::f32,
71008 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
71013 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
71022 /*156461*/ OPC_CheckType, MVT::f32,
71029 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
71050 /*156521*/ OPC_CheckType, MVT::f32,
71057 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
71065 /*156560*/ OPC_CheckType, MVT::f32,
71073 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
71078 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
71087 /*156617*/ OPC_CheckType, MVT::f32,
71094 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
71115 /*156677*/ OPC_CheckType, MVT::f32,
71122 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
71130 /*156716*/ OPC_CheckType, MVT::f32,
71138 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
71143 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
71152 /*156773*/ OPC_CheckType, MVT::f32,
71159 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
71181 /*156836*/ OPC_CheckType, MVT::f32,
71188 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
71196 /*156875*/ OPC_CheckType, MVT::f32,
71204 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
71209 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
71218 /*156932*/ OPC_CheckType, MVT::f32,
71225 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
71245 /*156993*/ OPC_CheckType, MVT::f32,
71252 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
71266 /*157042*/ OPC_CheckType, MVT::f32,
71273 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
71283 /*157084*/ OPC_CheckType, MVT::f32,
71290 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
71305 /*157134*/ OPC_CheckType, MVT::f32,
71312 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
71323 /*157177*/ OPC_CheckType, MVT::f32,
71330 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
71345 /*157227*/ OPC_CheckType, MVT::f32,
71352 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
71362 /*157269*/ OPC_CheckType, MVT::f32,
71369 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
71383 /*157317*/ OPC_CheckType, MVT::f32,
71390 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
71404 /*157366*/ OPC_CheckType, MVT::f32,
71411 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
71421 /*157408*/ OPC_CheckType, MVT::f32,
71428 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
71443 /*157458*/ OPC_CheckType, MVT::f32,
71450 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
71461 /*157501*/ OPC_CheckType, MVT::f32,
71468 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
71483 /*157551*/ OPC_CheckType, MVT::f32,
71490 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
71500 /*157593*/ OPC_CheckType, MVT::f32,
71507 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
71523 /*157647*/ OPC_CheckType, MVT::f32,
71530 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
71544 /*157696*/ OPC_CheckType, MVT::f32,
71551 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
71561 /*157738*/ OPC_CheckType, MVT::f32,
71568 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
71583 /*157788*/ OPC_CheckType, MVT::f32,
71590 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
71601 /*157831*/ OPC_CheckType, MVT::f32,
71608 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
71623 /*157881*/ OPC_CheckType, MVT::f32,
71630 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
71640 /*157923*/ OPC_CheckType, MVT::f32,
71647 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
71671 /*157986*/ OPC_CheckType, MVT::f32,
71678 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
71686 /*158025*/ OPC_CheckType, MVT::f32,
71694 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
71699 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
71708 /*158082*/ OPC_CheckType, MVT::f32,
71715 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
71737 /*158145*/ OPC_CheckType, MVT::f32,
71744 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
71752 /*158184*/ OPC_CheckType, MVT::f32,
71760 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
71765 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
71774 /*158241*/ OPC_CheckType, MVT::f32,
71781 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
71801 /*158300*/ OPC_CheckType, MVT::f32,
71808 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
71822 /*158349*/ OPC_CheckType, MVT::f32,
71829 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
71839 /*158391*/ OPC_CheckType, MVT::f32,
71846 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
71861 /*158441*/ OPC_CheckType, MVT::f32,
71868 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
71879 /*158484*/ OPC_CheckType, MVT::f32,
71886 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
71901 /*158534*/ OPC_CheckType, MVT::f32,
71908 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
71918 /*158576*/ OPC_CheckType, MVT::f32,
71925 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
71948 /*158638*/ OPC_CheckType, MVT::f32,
71955 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
71963 /*158677*/ OPC_CheckType, MVT::f32,
71971 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
71976 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
71985 /*158734*/ OPC_CheckType, MVT::f32,
71992 MVT::f32, 8/*#Ops*/, 6, 5, 4, 3, 8, 7, 9, 10,
72013 /*158794*/ OPC_CheckType, MVT::f32,
72020 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
72028 /*158833*/ OPC_CheckType, MVT::f32,
72036 MVT::f32, 8/*#Ops*/, 6, 5, 8, 7, 4, 3, 9, 10,
72041 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
72050 /*158890*/ OPC_CheckType, MVT::f32,
72057 MVT::f32, 8/*#Ops*/, 8, 7, 6, 5, 4, 3, 9, 10,
73211 /*161617*/ OPC_SwitchType /*4 cases */, 40, MVT::f32,// ->161660
73216 MVT::f32, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
73223 MVT::f32, 6/*#Ops*/, 5, 4, 3, 2, 6, 7,
73291 /*161828*/ OPC_CheckType, MVT::f32,
73297 MVT::f32, 3/*#Ops*/, 0, 1, 2,
73313 MVT::f32, 11/*#Ops*/, 5, 4, 8, 7, 10, 9, 11, 12, 13, 14, 15,
73321 /*161902*/ OPC_SwitchType /*4 cases */, 55, MVT::f32,// ->161960
73329 MVT::f32, 8/*#Ops*/, 4, 3, 8, 7, 10, 9, 5, 6,
73337 MVT::f32, 8/*#Ops*/, 4, 3, 8, 7, 10, 9, 5, 6,
73400 /*162128*/ OPC_CheckType, MVT::f32,
73420 /*162181*/ OPC_CheckType, MVT::f32,
73439 /*162231*/ OPC_SwitchType /*2 cases */, 13, MVT::f32,// ->162247
73442 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
73446 /*162249*/ OPC_CheckChild0Type, MVT::f32,
73458 /*162272*/ OPC_SwitchType /*2 cases */, 29, MVT::f32,// ->162304
73465 MVT::f32, 8/*#Ops*/, 4, 3, 6, 5, 8, 7, 9, 10,
74141 /*163936*/ OPC_SwitchType /*4 cases */, 40, MVT::f32,// ->163979
74146 MVT::f32, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
74153 MVT::f32, 6/*#Ops*/, 5, 4, 3, 2, 6, 7,
74223 /*164152*/ OPC_CheckType, MVT::f32,
74229 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
74234 /*164177*/ OPC_SwitchType /*2 cases */, 18, MVT::f32,// ->164198
74238 MVT::f32, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
74279 /*164299*/ /*SwitchType*/ 65, MVT::f32,// ->164366
74290 MVT::f32, 8/*#Ops*/, 6, 3, 7, 4, 8, 5, 9, 10,
74298 MVT::f32, 8/*#Ops*/, 4, 3, 8, 7, 10, 9, 5, 6,
74318 /*164402*/ OPC_CheckType, MVT::f32,
74326 MVT::f32, 4/*#Ops*/, 1, 3, 4, 5,
74335 /*164447*/ OPC_CheckType, MVT::f32,
74340 MVT::f32, 4/*#Ops*/, 1, 0, 2, 3,
74349 /*164481*/ OPC_CheckType, MVT::f32,
74354 MVT::f32, 4/*#Ops*/, 1, 0, 2, 3,
74363 /*164515*/ OPC_CheckType, MVT::f32,
74368 MVT::f32, 4/*#Ops*/, 1, 0, 2, 3,
74374 /*164539*/ OPC_CheckType, MVT::f32,
74379 MVT::f32, 1/*#Ops*/, 0,
74388 MVT::f32, 4/*#Ops*/, 1, 0, 2, 3,
74410 /*164624*/ /*SwitchType*/ 33, MVT::f32,// ->164659
74418 MVT::f32, 6/*#Ops*/, 3, 4, 2, 1, 5, 6,
74446 /*164723*/ /*SwitchType*/ 60, MVT::f32,// ->164785
74455 MVT::f32, 6/*#Ops*/, 3, 4, 2, 1, 5, 6,
74464 MVT::f32, 6/*#Ops*/, 2, 1, 2, 1, 3, 4,
74528 /*164948*/ OPC_CheckType, MVT::f32,
74534 MVT::f32, 4/*#Ops*/, 3, 2, 4, 5,
74541 /*164974*/ OPC_CheckType, MVT::f32,
74547 MVT::f32, 4/*#Ops*/, 3, 2, 4, 5,
74555 /*165001*/ OPC_CheckType, MVT::f32,
74560 MVT::f32, 4/*#Ops*/, 3, 2, 4, 5,
74572 /*165033*/ OPC_CheckType, MVT::f32,
74578 MVT::f32, 4/*#Ops*/, 3, 2, 4, 5,
74585 /*165059*/ OPC_CheckType, MVT::f32,
74591 MVT::f32, 4/*#Ops*/, 3, 2, 4, 5,
74599 /*165086*/ OPC_CheckType, MVT::f32,
74604 MVT::f32, 4/*#Ops*/, 3, 2, 4, 5,
74616 /*165118*/ OPC_CheckType, MVT::f32,
74622 MVT::f32, 4/*#Ops*/, 3, 2, 4, 5,
74629 /*165144*/ OPC_CheckType, MVT::f32,
74635 MVT::f32, 4/*#Ops*/, 3, 2, 4, 5,
74643 /*165171*/ OPC_CheckType, MVT::f32,
74648 MVT::f32, 4/*#Ops*/, 3, 2, 4, 5,
74655 /*165198*/ OPC_SwitchType /*3 cases */, 21, MVT::f32,// ->165222
74660 MVT::f32, 6/*#Ops*/, 2, 1, 2, 1, 3, 4,
74690 /*165287*/ OPC_CheckType, MVT::f32,
74701 /*165304*/ OPC_CheckType, MVT::f32,
74732 /*165395*/ OPC_CheckType, MVT::f32,
74743 /*165412*/ OPC_CheckType, MVT::f32,
74826 /*165673*/ /*SwitchType*/ 13, MVT::f32,// ->165688
74829 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
74846 /*165719*/ OPC_SwitchType /*3 cases */, 23, MVT::f32,// ->165745
74851 MVT::f32, MVT::i1, 2/*#Ops*/, 0, 2,
74893 /*165857*/ OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->165902
74899 MVT::f32, MVT::i1, 2/*#Ops*/, 0, 2,
74906 MVT::f32, 2/*#Ops*/, 2, 0,
75013 /*166167*/ OPC_SwitchType /*2 cases */, 9, MVT::f32,// ->166179
75016 MVT::f32, 1/*#Ops*/, 0,
75028 /*166193*/ OPC_SwitchType /*3 cases */, 13, MVT::f32,// ->166209
75031 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
75051 /*166247*/ OPC_SwitchType /*3 cases */, 26, MVT::f32,// ->166276
75056 MVT::f32, 1/*#Ops*/, 1,
75062 MVT::f32, 1/*#Ops*/, 1,
75092 /*166326*/ OPC_SwitchType /*4 cases */, 42, MVT::f32,// ->166371
75098 MVT::f32, MVT::i1, 2/*#Ops*/, 0, 2,
75105 MVT::f32, 2/*#Ops*/, 2, 0,
75167 /*166533*/ OPC_SwitchType /*3 cases */, 27, MVT::f32,// ->166563
75173 MVT::f32, 5/*#Ops*/, 1, 2, 3, 4, 0,
75214 /*166675*/ /*SwitchType*/ 12, MVT::f32,// ->166689
75217 MVT::f32, 3/*#Ops*/, 1, 2, 3,
75235 /*166719*/ OPC_SwitchType /*3 cases */, 27, MVT::f32,// ->166749
75241 MVT::f32, 5/*#Ops*/, 1, 2, 3, 4, 0,
75282 /*166852*/ /*SwitchType*/ 12, MVT::f32,// ->166866
75285 MVT::f32, 3/*#Ops*/, 1, 2, 3,
75311 /*166913*/ OPC_CheckChild0Type, MVT::f32,
75318 /*166929*/ /*SwitchType*/ 13, MVT::f32,// ->166944
75321 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
75338 /*166980*/ /*SwitchType*/ 34, MVT::f32,// ->167016
75346 MVT::f32, 3/*#Ops*/, 3, 0, 5,
75373 /*167097*/ OPC_CheckChild1Type, MVT::f32,
75374 /*167099*/ OPC_SwitchType /*3 cases */, 23, MVT::f32,// ->167125
75379 MVT::f32, 3/*#Ops*/, 3, 0, 1,
75415 /*167231*/ OPC_SwitchType /*3 cases */, 34, MVT::f32,// ->167268
75423 MVT::f32, 3/*#Ops*/, 3, 0, 5,
75467 /*167398*/ OPC_CheckType, MVT::f32,
75473 MVT::f32, 1/*#Ops*/, 3,
75480 /*167428*/ OPC_SwitchType /*2 cases */, 23, MVT::f32,// ->167454
75485 MVT::f32, 8/*#Ops*/, 4, 3, 8, 7, 10, 9, 5, 6,
75503 /*167491*/ OPC_SwitchType /*2 cases */, 23, MVT::f32,// ->167517
75508 MVT::f32, 8/*#Ops*/, 4, 3, 8, 7, 10, 9, 5, 6,
75526 /*167554*/ OPC_SwitchType /*2 cases */, 23, MVT::f32,// ->167580
75531 MVT::f32, 8/*#Ops*/, 4, 3, 8, 7, 10, 9, 5, 6,
75549 /*167617*/ OPC_SwitchType /*3 cases */, 23, MVT::f32,// ->167643
75554 MVT::f32, 8/*#Ops*/, 4, 3, 8, 7, 10, 9, 5, 6,
75590 /*167733*/ OPC_CheckType, MVT::f32,
75595 MVT::f32, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
75602 MVT::f32, 6/*#Ops*/, 5, 4, 3, 2, 6, 7,
75609 /*167781*/ OPC_SwitchType /*4 cases */, 40, MVT::f32,// ->167824
75614 MVT::f32, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
75621 MVT::f32, 6/*#Ops*/, 5, 4, 3, 2, 6, 7,
75686 /*167989*/ OPC_SwitchType /*4 cases */, 40, MVT::f32,// ->168032
75691 MVT::f32, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
75698 MVT::f32, 6/*#Ops*/, 5, 4, 3, 2, 6, 7,
75763 /*168197*/ OPC_SwitchType /*4 cases */, 40, MVT::f32,// ->168240
75768 MVT::f32, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
75775 MVT::f32, 6/*#Ops*/, 5, 4, 3, 2, 6, 7,
75841 /*168406*/ OPC_SwitchType /*3 cases */, 18, MVT::f32,// ->168427
75845 MVT::f32, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
75867 /*168475*/ OPC_CheckType, MVT::f32,
75872 MVT::f32, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
75878 /*168502*/ OPC_CheckType, MVT::f32,
75883 MVT::f32, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
75900 /*168556*/ OPC_CheckChild0Type, MVT::f32,
75917 /*168583*/ OPC_CheckChild4Type, MVT::f32,
75938 /*168618*/ OPC_CheckType, MVT::f32,
75941 MVT::f32, 9/*#Ops*/, 3, 0, 2, 1, 5, 4, 6, 7, 8,
75947 /*168642*/ OPC_CheckChild0Type, MVT::f32,
75964 /*168669*/ OPC_CheckChild4Type, MVT::f32,
75989 /*168718*/ OPC_CheckChild0Type, MVT::f32,
76020 /*168768*/ OPC_CheckType, MVT::f32,
76023 MVT::f32, 7/*#Ops*/, 3, 0, 2, 1, 4, 5, 6,
76028 /*168789*/ OPC_SwitchType /*3 cases */, 13, MVT::f32,// ->168805
76031 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
76050 /*168842*/ OPC_SwitchType /*3 cases */, 13, MVT::f32,// ->168858
76053 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
76073 /*168897*/ OPC_SwitchType /*3 cases */, 13, MVT::f32,// ->168913
76076 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
76096 /*168952*/ OPC_SwitchType /*3 cases */, 13, MVT::f32,// ->168968
76099 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
76119 /*169007*/ OPC_SwitchType /*2 cases */, 13, MVT::f32,// ->169023
76122 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
76135 /*169045*/ OPC_SwitchType /*2 cases */, 13, MVT::f32,// ->169061
76138 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
76151 /*169083*/ OPC_CheckType, MVT::f32,
76154 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
76159 /*169102*/ OPC_SwitchType /*3 cases */, 13, MVT::f32,// ->169118
76162 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
76181 /*169155*/ OPC_SwitchType /*3 cases */, 13, MVT::f32,// ->169171
76184 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
76203 /*169208*/ OPC_SwitchType /*2 cases */, 13, MVT::f32,// ->169224
76206 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
76219 /*169246*/ OPC_SwitchType /*2 cases */, 13, MVT::f32,// ->169262
76222 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
76235 /*169284*/ OPC_CheckType, MVT::f32,
76239 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
76244 /*169305*/ OPC_SwitchType /*2 cases */, 15, MVT::f32,// ->169323
76248 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
76261 /*169345*/ OPC_CheckType, MVT::f32,
76265 MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
76271 /*169368*/ OPC_CheckType, MVT::f32,
76274 MVT::f32, 3/*#Ops*/, 1, 2, 3,
76280 /*169388*/ OPC_CheckType, MVT::f32,
76283 MVT::f32, 3/*#Ops*/, 1, 2, 3,
76289 /*169408*/ OPC_CheckType, MVT::f32,
76292 MVT::f32, 3/*#Ops*/, 1, 2, 3,
76298 /*169428*/ OPC_CheckType, MVT::f32,
76301 MVT::f32, 3/*#Ops*/, 1, 2, 3,
77200 /*171631*/ OPC_CheckType, MVT::f32,
77221 /*171682*/ OPC_CheckType, MVT::f32,
77245 /*171739*/ OPC_CheckType, MVT::f32,
77265 /*171789*/ OPC_CheckType, MVT::f32,
78461 /*174433*/ OPC_CheckChild0Type, MVT::f32,
78472 /*174459*/ OPC_CheckChild0Type, MVT::f32,
78501 /*174519*/ OPC_CheckChild0Type, MVT::f32,
79472 if (cast<MemSDNode>(N)->getMemoryVT() != MVT::f32) return false;
79545 if (cast<MemSDNode>(N)->getMemoryVT() != MVT::f32) return false;
79558 if (cast<MemSDNode>(N)->getMemoryVT() != MVT::f32) return false;
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc17459 /* 0 */ MVT::i32, MVT::f32, MVT::i16, MVT::f16, MVT::v2i16, MVT::v2f16, MVT::i1, MVT::Other,
17462 /* 20 */ MVT::i32, MVT::f32, MVT::v2i16, MVT::v2f16, MVT::i32, MVT::i32, MVT::i32, MVT::i32, MVT::i16, MVT::f16, MVT::Other,
17466 /* 45 */ MVT::i32, MVT::f32, MVT::i16, MVT::f16, MVT::v2i16, MVT::v2f16, MVT::Other,
17467 /* 52 */ MVT::i32, MVT::f32, MVT::v2i16, MVT::v2f16, MVT::Other,
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 794 /* 2376*/ OPC_EmitRegister, MVT::f32, R600::ZERO,
4237 /* 17398*/ OPC_CheckChild0Type, MVT::f32,
4474 /* 18293*/ OPC_CheckType, MVT::f32,
4495 MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
4501 /* 18399*/ OPC_CheckType, MVT::f32,
4522 MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
4528 /* 18505*/ OPC_CheckType, MVT::f32,
4549 MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
4555 /* 18611*/ OPC_CheckType, MVT::f32,
4576 MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
4582 /* 18717*/ OPC_CheckType, MVT::f32,
4603 MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
4609 /* 18823*/ OPC_CheckType, MVT::f32,
4630 MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
4636 /* 18929*/ OPC_CheckType, MVT::f32,
4657 MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
4663 /* 19035*/ OPC_CheckType, MVT::f32,
4684 MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
4700 /* 19156*/ OPC_CheckType, MVT::f32,
4718 MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
4724 /* 19260*/ OPC_CheckType, MVT::f32,
4742 MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
4748 /* 19364*/ OPC_CheckType, MVT::f32,
4766 MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
4772 /* 19468*/ OPC_CheckType, MVT::f32,
4790 MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
4796 /* 19572*/ OPC_CheckType, MVT::f32,
4814 MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
4820 /* 19676*/ OPC_CheckType, MVT::f32,
4838 MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
4844 /* 19780*/ OPC_CheckType, MVT::f32,
4862 MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
4868 /* 19884*/ OPC_CheckType, MVT::f32,
4886 MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
4892 /* 19988*/ OPC_CheckType, MVT::f32,
4910 MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
4916 /* 20092*/ OPC_CheckType, MVT::f32,
4934 MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
4940 /* 20196*/ OPC_CheckType, MVT::f32,
4958 MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
4964 /* 20300*/ OPC_CheckType, MVT::f32,
4982 MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
5261 /* 21490*/ OPC_CheckType, MVT::f32,
5279 MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
5285 /* 21594*/ OPC_CheckType, MVT::f32,
5303 MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
5309 /* 21698*/ OPC_CheckType, MVT::f32,
5327 MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
7034 /* 27405*/ /*SwitchType*/ 8|128,1/*136*/, MVT::f32,// ->27544
7042 MVT::f32, 2/*#Ops*/, 0, 1,
7050 MVT::f32, 2/*#Ops*/, 0, 1,
7058 MVT::f32, 2/*#Ops*/, 0, 1,
7066 MVT::f32, 2/*#Ops*/, 0, 1,
7074 MVT::f32, 2/*#Ops*/, 0, 1,
7085 MVT::f32, 2/*#Ops*/, 0, 1,
7093 MVT::f32, 2/*#Ops*/, 0, 1,
7101 MVT::f32, 2/*#Ops*/, 0, 1,
7630 /* 29220*/ OPC_CheckChild0Type, MVT::f32,
7635 /* 29227*/ /*SwitchType*/ 7, MVT::f32,// ->29236
7818 /* 29836*/ OPC_CheckChild0Type, MVT::f32,
7873 /* 30046*/ OPC_CheckChild0Type, MVT::f32,
8698 /* 33390*/ OPC_CheckChild0Type, MVT::f32,
8901 /* 34069*/ OPC_CheckChild2Type, MVT::f32,
8915 /* 34098*/ OPC_CheckType, MVT::f32,
8917 /* 34101*/ OPC_CheckType, MVT::f32,
8933 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
8951 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
8969 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
8975 /* 34309*/ OPC_CheckChild1Type, MVT::f32,
8976 /* 34311*/ OPC_CheckType, MVT::f32,
8992 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9010 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9028 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9036 /* 34522*/ OPC_CheckChild1Type, MVT::f32,
9037 /* 34524*/ OPC_CheckType, MVT::f32,
9052 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9058 /* 34598*/ OPC_CheckChild1Type, MVT::f32,
9059 /* 34600*/ OPC_CheckType, MVT::f32,
9075 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9093 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9111 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9118 /* 34811*/ OPC_CheckChild1Type, MVT::f32,
9119 /* 34813*/ OPC_CheckType, MVT::f32,
9135 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9153 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9171 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9199 /* 35061*/ OPC_CheckType, MVT::f32,
9215 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9233 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9251 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9258 /* 35270*/ OPC_CheckType, MVT::f32,
9294 MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 24, 25, 26, 27, 28, 29, 30, 31, 32,
9332 MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 24, 25, 26, 27, 28, 29, 30, 31, 32,
9370 MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 24, 25, 26, 27, 28, 29, 30, 31, 32,
9381 /* 35786*/ OPC_CheckType, MVT::f32,
9397 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9415 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9433 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9439 /* 35994*/ OPC_CheckType, MVT::f32,
9455 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9473 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9491 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9499 /* 36205*/ OPC_CheckType, MVT::f32,
9520 MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
9526 /* 36312*/ OPC_CheckType, MVT::f32,
9547 MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
9553 /* 36419*/ OPC_CheckType, MVT::f32,
9574 MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
9580 /* 36526*/ OPC_CheckType, MVT::f32,
9601 MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
9607 /* 36633*/ OPC_CheckType, MVT::f32,
9628 MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
9634 /* 36740*/ OPC_CheckType, MVT::f32,
9655 MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
9660 /* 36846*/ OPC_CheckType, MVT::f32,
9675 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9680 /* 36918*/ OPC_CheckType, MVT::f32,
9695 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9700 /* 36990*/ OPC_CheckType, MVT::f32,
9715 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9720 /* 37062*/ OPC_CheckType, MVT::f32,
9735 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9740 /* 37134*/ OPC_CheckType, MVT::f32,
9755 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9767 /* 37214*/ OPC_CheckType, MVT::f32,
9832 MVT::f32, 70/*#Ops*/, 8, 9, 10, 11, 12, 13, 0, 14, 15, 16, 17, 1, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 2, 29, 30, 31, 32, 3, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 4, 44, 45, 46, 47, 5, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 6, 59, 60, 61, 62, 7, 63, 64, 65, 66, 67, 68, 69,
9839 /* 37559*/ OPC_CheckType, MVT::f32,
9858 MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
9879 MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
9885 /* 37766*/ OPC_CheckType, MVT::f32,
9901 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9919 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9937 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9943 /* 37976*/ OPC_CheckType, MVT::f32,
9959 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9977 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
9995 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
10001 /* 38186*/ OPC_CheckType, MVT::f32,
10017 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
10035 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
10053 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
10059 /* 38396*/ OPC_CheckType, MVT::f32,
10075 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
10093 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
10111 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
10118 /* 38608*/ OPC_CheckType, MVT::f32,
10134 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
10152 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
10159 /* 38753*/ OPC_CheckType, MVT::f32,
10175 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
10193 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
10199 /* 38896*/ OPC_CheckChild0Type, MVT::f32,
10200 /* 38898*/ OPC_CheckType, MVT::f32,
10216 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
10234 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
10252 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
10270 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
10276 /* 39175*/ OPC_CheckChild0Type, MVT::f32,
10277 /* 39177*/ OPC_CheckType, MVT::f32,
10293 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
10311 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
10329 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
10347 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
10355 /* 39455*/ OPC_CheckType, MVT::f32,
10373 MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
10379 /* 39561*/ OPC_CheckType, MVT::f32,
10394 MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
10399 /* 39634*/ OPC_CheckType, MVT::f32,
10435 MVT::f32, 20/*#Ops*/, 1, 2, 3, 4, 5, 6, 0, 7, 8, 9, 10, 23, 24, 25, 26, 27, 28, 29, 30, 31,
10473 MVT::f32, 20/*#Ops*/, 1, 2, 3, 4, 5, 6, 0, 7, 8, 9, 10, 23, 24, 25, 26, 27, 28, 29, 30, 31,
10511 MVT::f32, 20/*#Ops*/, 1, 2, 3, 4, 5, 6, 0, 7, 8, 9, 10, 23, 24, 25, 26, 27, 28, 29, 30, 31,
10518 /* 40142*/ OPC_CheckType, MVT::f32,
10568 MVT::f32, 13/*#Ops*/, 2, 3, 4, 5, 37, 38, 39, 40, 41, 42, 43, 44, 45,
10620 MVT::f32, 13/*#Ops*/, 2, 3, 4, 5, 37, 38, 39, 40, 41, 42, 43, 44, 45,
10672 MVT::f32, 13/*#Ops*/, 2, 3, 4, 5, 37, 38, 39, 40, 41, 42, 43, 44, 45,
10678 /* 40840*/ OPC_CheckType, MVT::f32,
10682 MVT::f32, 1/*#Ops*/, 1,
10687 /* 40857*/ OPC_CheckType, MVT::f32,
10689 MVT::f32, 1/*#Ops*/, 0,
10694 /* 40870*/ OPC_CheckType, MVT::f32,
10696 MVT::f32, 1/*#Ops*/, 0,
10703 /* 40888*/ OPC_CheckChild1Type, MVT::f32,
10704 /* 40890*/ OPC_SwitchType /*2 cases */, 112, MVT::f32,// ->41005
10725 MVT::f32, 18/*#Ops*/, 2, 3, 5, 6, 7, 8, 0, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18,
10766 /* 41167*/ OPC_SwitchType /*2 cases */, 123, MVT::f32,// ->41293
10790 MVT::f32, 18/*#Ops*/, 2, 3, 5, 6, 7, 8, 0, 9, 10, 11, 13, 14, 15, 16, 17, 18, 19, 20,
gen/lib/Target/AMDGPU/R600GenRegisterInfo.inc 8869 /* 0 */ MVT::f32, MVT::i32, MVT::Other,
gen/lib/Target/ARM/ARMGenCallingConv.inc 109 if (LocVT == MVT::f32) {
184 if (LocVT == MVT::f32) {
300 if (LocVT == MVT::f32) {
382 if (LocVT == MVT::f32) {
463 if (LocVT == MVT::f32) {
557 if (LocVT == MVT::f32) {
567 if (LocVT == MVT::f32) {
651 if (LocVT == MVT::f32) {
770 if (LocVT == MVT::f32) {
803 if (LocVT == MVT::f32) {
923 if (LocVT == MVT::f32) {
gen/lib/Target/ARM/ARMGenDAGISel.inc10806 /* 22876*/ OPC_CheckChild0Type, MVT::f32,
11013 /* 23375*/ OPC_CheckChild0Type, MVT::f32,
15025 MVT::f32, 2/*#Ops*/, 0, 2, // Results = #3
15033 MVT::f32, 2/*#Ops*/, 6, 7, // Results = #8
15049 /* 32330*/ /*SwitchType*/ 11, MVT::f32,// ->32343
15050 /* 32332*/ OPC_CheckChild1Type, MVT::f32,
15053 MVT::f32, 1/*#Ops*/, 0,
15101 MVT::f32, 3/*#Ops*/, 0, 1, 2,
15105 /* 32436*/ OPC_CheckChild1Type, MVT::f32,
15110 MVT::f32, 3/*#Ops*/, 0, 1, 2,
15123 MVT::f32, 3/*#Ops*/, 0, 1, 2,
15127 /* 32483*/ OPC_CheckChild1Type, MVT::f32,
15132 MVT::f32, 3/*#Ops*/, 0, 1, 2,
21174 MVT::f32, 2/*#Ops*/, 1, 4, // Results = #5
21191 MVT::f32, 2/*#Ops*/, 1, 4, // Results = #5
21208 MVT::f32, 2/*#Ops*/, 1, 4, // Results = #5
22278 /* 47867*/ OPC_CheckType, MVT::f32,
22300 /* 47911*/ OPC_CheckType, MVT::f32,
22508 MVT::f32, 3/*#Ops*/, 1, 5, 6, // Results = #7
22516 /* 48384*/ OPC_CheckChild0Type, MVT::f32,
22529 MVT::f32, 3/*#Ops*/, 1, 5, 6, // Results = #7
22554 MVT::f32, 3/*#Ops*/, 1, 5, 6, // Results = #7
22562 /* 48492*/ OPC_CheckChild0Type, MVT::f32,
22575 MVT::f32, 3/*#Ops*/, 1, 5, 6, // Results = #7
22932 /* 49318*/ OPC_CheckChild1Type, MVT::f32,
26652 /* 57525*/ /*SwitchType*/ 10, MVT::f32,// ->57537
26655 MVT::f32, 2/*#Ops*/, 1, 0,
26673 /* 57566*/ /*SwitchType*/ 10, MVT::f32,// ->57578
26676 MVT::f32, 2/*#Ops*/, 1, 0,
26694 /* 57607*/ /*SwitchType*/ 10, MVT::f32,// ->57619
26697 MVT::f32, 2/*#Ops*/, 1, 0,
26715 /* 57648*/ /*SwitchType*/ 10, MVT::f32,// ->57660
26718 MVT::f32, 2/*#Ops*/, 1, 0,
26737 /* 57693*/ /*SwitchType*/ 15, MVT::f32,// ->57710
26741 MVT::f32, 4/*#Ops*/, 0, 1, 3, 4,
27907 /* 60364*/ /*SwitchType*/ 22, MVT::f32,// ->60388
27914 MVT::f32, 4/*#Ops*/, 2, 3, 4, 5,
36888 MVT::f32, 2/*#Ops*/, 0, 3, // Results = #4
36890 MVT::f32, 1/*#Ops*/, 4, // Results = #5
36904 MVT::f32, 2/*#Ops*/, 3, 5, // Results = #6
36906 MVT::f32, 1/*#Ops*/, 6, // Results = #7
36945 MVT::f32, 2/*#Ops*/, 3, 5, // Results = #6
36947 MVT::f32, 1/*#Ops*/, 6, // Results = #7
36983 /* 81368*/ OPC_CheckType, MVT::f32,
36991 MVT::f32, 2/*#Ops*/, 3, 5,
37000 /* 81405*/ OPC_CheckType, MVT::f32,
37009 MVT::f32, 2/*#Ops*/, 3, 5,
37017 MVT::f32, 2/*#Ops*/, 0, 3, // Results = #4
37020 MVT::f32, 2/*#Ops*/, 4, 5,
37035 MVT::f32, 1/*#Ops*/, 0, // Results = #1
37041 /* 81503*/ /*SwitchType*/ 23, MVT::f32,// ->81528
37046 MVT::f32, 1/*#Ops*/, 0, // Results = #1
37057 MVT::f32, 1/*#Ops*/, 0, // Results = #1
37071 MVT::f32, 1/*#Ops*/, 0, // Results = #1
37077 /* 81584*/ /*SwitchType*/ 23, MVT::f32,// ->81609
37082 MVT::f32, 1/*#Ops*/, 0, // Results = #1
37093 MVT::f32, 1/*#Ops*/, 0, // Results = #1
37107 MVT::f32, 1/*#Ops*/, 0, // Results = #1
37113 /* 81665*/ /*SwitchType*/ 23, MVT::f32,// ->81690
37118 MVT::f32, 1/*#Ops*/, 0, // Results = #1
37129 MVT::f32, 1/*#Ops*/, 0, // Results = #1
37146 MVT::f32, 3/*#Ops*/, 0, 1, 2, // Results = #3
37153 /* 81757*/ OPC_CheckChild0Type, MVT::f32,
37159 MVT::f32, 3/*#Ops*/, 0, 1, 2, // Results = #3
37188 MVT::f32, 3/*#Ops*/, 0, 1, 2, // Results = #3
37287 MVT::f32, 1/*#Ops*/, 0, // Results = #1
37293 /* 82104*/ /*SwitchType*/ 23, MVT::f32,// ->82129
37298 MVT::f32, 1/*#Ops*/, 0, // Results = #1
37309 MVT::f32, 1/*#Ops*/, 0, // Results = #1
37323 MVT::f32, 1/*#Ops*/, 0, // Results = #1
37329 /* 82185*/ /*SwitchType*/ 23, MVT::f32,// ->82210
37334 MVT::f32, 1/*#Ops*/, 0, // Results = #1
37345 MVT::f32, 1/*#Ops*/, 0, // Results = #1
37359 MVT::f32, 1/*#Ops*/, 0, // Results = #1
37365 /* 82266*/ /*SwitchType*/ 23, MVT::f32,// ->82291
37370 MVT::f32, 1/*#Ops*/, 0, // Results = #1
37381 MVT::f32, 1/*#Ops*/, 0, // Results = #1
37398 MVT::f32, 3/*#Ops*/, 0, 1, 2, // Results = #3
37405 /* 82358*/ OPC_CheckChild0Type, MVT::f32,
37411 MVT::f32, 3/*#Ops*/, 0, 1, 2, // Results = #3
37440 MVT::f32, 3/*#Ops*/, 0, 1, 2, // Results = #3
38645 /* 85201*/ OPC_CheckChild0Type, MVT::f32,
38677 /* 85271*/ OPC_CheckChild0Type, MVT::f32,
38698 /* 85318*/ OPC_CheckChild0Type, MVT::f32,
38718 /* 85356*/ OPC_CheckType, MVT::f32,
38723 MVT::f32, 2/*#Ops*/, 0, 3,
39238 /* 86319*/ OPC_CheckType, MVT::f32,
39244 MVT::f32, 3/*#Ops*/, 0, 1, 2,
39255 MVT::f32, 2/*#Ops*/, 3, 4,
40700 /* 89181*/ OPC_CheckChild0Type, MVT::f32,
40705 MVT::f32, 3/*#Ops*/, 0, 1, 2, // Results = #3
40717 MVT::f32, 3/*#Ops*/, 0, 1, 2, // Results = #3
40999 MVT::f32, 4/*#Ops*/, 2, 3, 4, 5, // Results = #6
41006 /* 89983*/ /*SwitchType*/ 37, MVT::f32,// ->90022
41013 MVT::f32, 4/*#Ops*/, 2, 3, 4, 5, // Results = #6
41017 MVT::f32, 3/*#Ops*/, 6, 7, 8,
41035 MVT::f32, 2/*#Ops*/, 0, 3, // Results = #4
41054 MVT::f32, 2/*#Ops*/, 0, 3, // Results = #4
41069 MVT::f32, 2/*#Ops*/, 0, 1, // Results = #2
41076 /* 90148*/ /*SwitchType*/ 89, MVT::f32,// ->90239
41081 MVT::f32, 2/*#Ops*/, 0, 1, // Results = #2
41085 MVT::f32, 3/*#Ops*/, 2, 3, 4,
41104 MVT::f32, 2/*#Ops*/, 8, 9,
41112 MVT::f32, 2/*#Ops*/, 0, 1, // Results = #2
41248 MVT::f32, 4/*#Ops*/, 2, 3, 4, 5, // Results = #6
41255 /* 90619*/ /*SwitchType*/ 37, MVT::f32,// ->90658
41262 MVT::f32, 4/*#Ops*/, 2, 3, 4, 5, // Results = #6
41266 MVT::f32, 3/*#Ops*/, 6, 7, 8,
41284 MVT::f32, 2/*#Ops*/, 0, 3, // Results = #4
41303 MVT::f32, 2/*#Ops*/, 0, 3, // Results = #4
41318 MVT::f32, 2/*#Ops*/, 0, 1, // Results = #2
41325 /* 90784*/ /*SwitchType*/ 89, MVT::f32,// ->90875
41330 MVT::f32, 2/*#Ops*/, 0, 1, // Results = #2
41334 MVT::f32, 3/*#Ops*/, 2, 3, 4,
41353 MVT::f32, 2/*#Ops*/, 8, 9,
41361 MVT::f32, 2/*#Ops*/, 0, 1, // Results = #2
41509 /* 91259*/ /*SwitchType*/ 42, MVT::f32,// ->91303
41515 MVT::f32, 5/*#Ops*/, 2, 0, 1, 3, 4,
41523 MVT::f32, 5/*#Ops*/, 2, 0, 1, 3, 4,
41576 /* 91412*/ /*SwitchType*/ 42, MVT::f32,// ->91456
41582 MVT::f32, 5/*#Ops*/, 0, 1, 2, 3, 4,
41590 MVT::f32, 5/*#Ops*/, 0, 1, 2, 3, 4,
41630 /* 91536*/ /*SwitchType*/ 19, MVT::f32,// ->91557
41635 MVT::f32, 5/*#Ops*/, 2, 0, 1, 3, 4,
41664 /* 91614*/ /*SwitchType*/ 19, MVT::f32,// ->91635
41669 MVT::f32, 5/*#Ops*/, 0, 1, 2, 3, 4,
41698 /* 91692*/ /*SwitchType*/ 19, MVT::f32,// ->91713
41703 MVT::f32, 5/*#Ops*/, 2, 0, 1, 3, 4,
41732 /* 91770*/ /*SwitchType*/ 19, MVT::f32,// ->91791
41737 MVT::f32, 5/*#Ops*/, 0, 1, 2, 3, 4,
41801 /* 91923*/ OPC_CheckType, MVT::f32,
41837 MVT::f32, 2/*#Ops*/, 22, 23,
41875 MVT::f32, 2/*#Ops*/, 22, 23,
41886 /* 92197*/ OPC_CheckType, MVT::f32,
41922 MVT::f32, 2/*#Ops*/, 22, 23,
41960 MVT::f32, 2/*#Ops*/, 22, 23,
41976 /* 92489*/ /*SwitchType*/ 120, MVT::f32,// ->92611
41982 MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
42012 MVT::f32, 2/*#Ops*/, 16, 17,
42807 /* 94290*/ /*SwitchType*/ 19, MVT::f32,// ->94311
42812 MVT::f32, 5/*#Ops*/, 2, 0, 1, 3, 4,
42852 /* 94392*/ /*SwitchType*/ 19, MVT::f32,// ->94413
42857 MVT::f32, 5/*#Ops*/, 0, 1, 2, 3, 4,
42887 /* 94471*/ /*SwitchType*/ 19, MVT::f32,// ->94492
42892 MVT::f32, 5/*#Ops*/, 2, 0, 1, 3, 4,
42922 /* 94550*/ /*SwitchType*/ 19, MVT::f32,// ->94571
42927 MVT::f32, 5/*#Ops*/, 0, 1, 2, 3, 4,
42956 /* 94628*/ /*SwitchType*/ 19, MVT::f32,// ->94649
42961 MVT::f32, 5/*#Ops*/, 2, 0, 1, 3, 4,
43000 /* 94729*/ /*SwitchType*/ 19, MVT::f32,// ->94750
43005 MVT::f32, 5/*#Ops*/, 0, 1, 2, 3, 4,
43034 /* 94807*/ /*SwitchType*/ 19, MVT::f32,// ->94828
43039 MVT::f32, 5/*#Ops*/, 2, 0, 1, 3, 4,
43059 /* 94863*/ OPC_CheckType, MVT::f32,
43095 MVT::f32, 2/*#Ops*/, 22, 23,
43133 MVT::f32, 2/*#Ops*/, 22, 23,
43147 /* 95151*/ /*SwitchType*/ 120, MVT::f32,// ->95273
43153 MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
43183 MVT::f32, 2/*#Ops*/, 16, 17,
43565 /* 96124*/ /*SwitchType*/ 19, MVT::f32,// ->96145
43570 MVT::f32, 5/*#Ops*/, 2, 0, 1, 3, 4,
43584 /* 96170*/ /*SwitchType*/ 19, MVT::f32,// ->96191
43589 MVT::f32, 5/*#Ops*/, 2, 0, 1, 3, 4,
43610 /* 96227*/ /*SwitchType*/ 19, MVT::f32,// ->96248
43615 MVT::f32, 5/*#Ops*/, 2, 0, 1, 3, 4,
43634 /* 96281*/ /*SwitchType*/ 19, MVT::f32,// ->96302
43639 MVT::f32, 5/*#Ops*/, 2, 0, 1, 3, 4,
43653 /* 96327*/ /*SwitchType*/ 19, MVT::f32,// ->96348
43658 MVT::f32, 5/*#Ops*/, 2, 0, 1, 3, 4,
43774 /* 96609*/ /*SwitchType*/ 19, MVT::f32,// ->96630
43779 MVT::f32, 5/*#Ops*/, 2, 0, 1, 3, 4,
43800 /* 96665*/ /*SwitchType*/ 19, MVT::f32,// ->96686
43805 MVT::f32, 5/*#Ops*/, 2, 0, 1, 3, 4,
43821 /* 96713*/ /*SwitchType*/ 19, MVT::f32,// ->96734
43826 MVT::f32, 5/*#Ops*/, 2, 0, 1, 3, 4,
43844 /* 96764*/ /*SwitchType*/ 18, MVT::f32,// ->96784
43849 MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
43905 /* 96929*/ /*SwitchType*/ 89, MVT::f32,// ->97020
43911 MVT::f32, 3/*#Ops*/, 0, 1, 2,
43933 MVT::f32, 2/*#Ops*/, 10, 11,
44018 /* 97207*/ /*SwitchType*/ 18, MVT::f32,// ->97227
44023 MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
44042 /* 97260*/ /*SwitchType*/ 18, MVT::f32,// ->97280
44047 MVT::f32, 4/*#Ops*/, 1, 0, 2, 3,
44061 /* 97305*/ /*SwitchType*/ 120, MVT::f32,// ->97427
44067 MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
44097 MVT::f32, 2/*#Ops*/, 16, 17,
44330 /* 97924*/ OPC_CheckChild0Type, MVT::f32,
44399 /* 98113*/ OPC_CheckChild0Type, MVT::f32,
44570 /* 98562*/ /*SwitchType*/ 89, MVT::f32,// ->98653
44576 MVT::f32, 3/*#Ops*/, 0, 1, 2,
44598 MVT::f32, 2/*#Ops*/, 10, 11,
44681 /* 98837*/ /*SwitchType*/ 24, MVT::f32,// ->98863
44689 MVT::f32, 3/*#Ops*/, 2, 3, 4,
44715 /* 98916*/ /*SwitchType*/ 18, MVT::f32,// ->98936
44720 MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
44741 /* 98976*/ /*SwitchType*/ 10, MVT::f32,// ->98988
44744 MVT::f32, 2/*#Ops*/, 0, 1,
44811 /* 99126*/ /*SwitchType*/ 10, MVT::f32,// ->99138
44814 MVT::f32, 2/*#Ops*/, 0, 1,
44876 /* 99266*/ OPC_CheckChild0Type, MVT::f32,
44889 MVT::f32, 2/*#Ops*/, 0, 1, // Results = #2
44897 /* 99317*/ /*SwitchType*/ 28, MVT::f32,// ->99347
44901 MVT::f32, 2/*#Ops*/, 0, 1, // Results = #2
44905 MVT::f32, 3/*#Ops*/, 2, 3, 4,
44911 /* 99352*/ OPC_SwitchType /*2 cases */, 17, MVT::f32,// ->99372
44916 MVT::f32, 3/*#Ops*/, 0, 1, 2,
44921 /* 99376*/ OPC_CheckChild0Type, MVT::f32,
44926 MVT::f32, 3/*#Ops*/, 0, 1, 2, // Results = #3
44938 MVT::f32, 3/*#Ops*/, 0, 1, 2, // Results = #3
44956 /* 99463*/ /*SwitchType*/ 17, MVT::f32,// ->99482
44961 MVT::f32, 3/*#Ops*/, 0, 1, 2,
45003 /* 99578*/ /*SwitchType*/ 17, MVT::f32,// ->99597
45008 MVT::f32, 3/*#Ops*/, 0, 1, 2,
45030 /* 99641*/ /*SwitchType*/ 17, MVT::f32,// ->99660
45035 MVT::f32, 3/*#Ops*/, 0, 1, 2,
45075 /* 99748*/ /*SwitchType*/ 9, MVT::f32,// ->99759
45078 MVT::f32, 1/*#Ops*/, 0,
45116 /* 99839*/ /*SwitchType*/ 9, MVT::f32,// ->99850
45119 MVT::f32, 1/*#Ops*/, 0,
45157 /* 99930*/ /*SwitchType*/ 9, MVT::f32,// ->99941
45160 MVT::f32, 1/*#Ops*/, 0,
45200 /*100029*/ /*SwitchType*/ 17, MVT::f32,// ->100048
45205 MVT::f32, 3/*#Ops*/, 0, 1, 2,
45224 MVT::f32, 3/*#Ops*/, 0, 1, 2,
45235 MVT::f32, 2/*#Ops*/, 3, 4,
45261 /*100172*/ OPC_SwitchType /*2 cases */, 28, MVT::f32,// ->100203
45265 MVT::f32, 2/*#Ops*/, 0, 1, // Results = #2
45269 MVT::f32, 3/*#Ops*/, 2, 3, 4,
45276 MVT::f32, 2/*#Ops*/, 0, 1, // Results = #2
45317 /*100341*/ /*SwitchType*/ 98, MVT::f32,// ->100441
45344 MVT::f32, 2/*#Ops*/, 16, 17,
45413 /*100629*/ /*SwitchType*/ 98, MVT::f32,// ->100729
45440 MVT::f32, 2/*#Ops*/, 16, 17,
46097 /*102181*/ /*SwitchType*/ 65, MVT::f32,// ->102248
46442 /*102984*/ OPC_CheckType, MVT::f32,
46468 /*103043*/ OPC_CheckType, MVT::f32,
46501 /*103114*/ OPC_CheckChild0Type, MVT::f32,
48848 /*108660*/ OPC_CheckChild0Type, MVT::f32,
53698 /*120205*/ OPC_CheckChild0Type, MVT::f32,
54702 return (ScalarVT == MVT::i32 || ScalarVT == MVT::f32) && St->getAlignment() >= 4;
54840 return (ScalarVT == MVT::i32 || ScalarVT == MVT::f32) && Ld->getAlignment() >= 4;
gen/lib/Target/ARM/ARMGenFastISel.inc 170 case MVT::f32: return fastEmit_ARMISD_CMPFPw0_MVT_f32_r(RetVT, Op0, Op0IsKill);
329 if (RetVT.SimpleTy != MVT::f32)
731 if (RetVT.SimpleTy != MVT::f32)
1519 case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0, Op0IsKill);
1757 if (RetVT.SimpleTy != MVT::f32)
1819 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
1841 if (RetVT.SimpleTy != MVT::f32)
1879 case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0, Op0IsKill);
1899 if (RetVT.SimpleTy != MVT::f32)
1937 case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
1957 if (RetVT.SimpleTy != MVT::f32)
1977 case MVT::f32: return fastEmit_ISD_FNEARBYINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
1995 if (RetVT.SimpleTy != MVT::f32)
2057 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
2080 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill);
2088 if (RetVT.SimpleTy != MVT::f32)
2223 if (RetVT.SimpleTy != MVT::f32)
2261 case MVT::f32: return fastEmit_ISD_FRINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
2281 if (RetVT.SimpleTy != MVT::f32)
2319 case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
2339 if (RetVT.SimpleTy != MVT::f32)
2359 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
2377 if (RetVT.SimpleTy != MVT::f32)
2415 case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0, Op0IsKill);
2790 case MVT::f32: return fastEmit_ARMISD_CMPFP_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3600 if (RetVT.SimpleTy != MVT::f32)
3662 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3684 if (RetVT.SimpleTy != MVT::f32)
3704 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3770 if (RetVT.SimpleTy != MVT::f32)
3832 case MVT::f32: return fastEmit_ISD_FMAXNUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3902 if (RetVT.SimpleTy != MVT::f32)
3964 case MVT::f32: return fastEmit_ISD_FMINNUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3986 if (RetVT.SimpleTy != MVT::f32)
4048 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4070 if (RetVT.SimpleTy != MVT::f32)
4132 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 3748 /* 4 */ MVT::f32, MVT::Other,
gen/lib/Target/Hexagon/HexagonGenCallingConv.inc 42 if (LocVT == MVT::f32) {
257 if (LocVT == MVT::f32) {
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc18596 /* 35493*/ OPC_CheckChild1Type, MVT::f32,
30254 /* 58426*/ OPC_CheckChild0Type, MVT::f32,
40298 MVT::f32, 1/*#Ops*/, 0,
40310 MVT::f32, 1/*#Ops*/, 0,
40343 MVT::f32, 2/*#Ops*/, 0, 1,
40351 MVT::f32, 1/*#Ops*/, 0,
40361 MVT::f32, 3/*#Ops*/, 0, 1, 2,
40371 MVT::f32, 3/*#Ops*/, 0, 1, 2,
40388 MVT::f32, 2/*#Ops*/, 0, 1,
40404 MVT::f32, 1/*#Ops*/, 0,
40413 MVT::f32, 2/*#Ops*/, 0, 1,
40423 MVT::f32, 3/*#Ops*/, 0, 1, 2,
40431 MVT::f32, 1/*#Ops*/, 0,
40448 MVT::f32, 2/*#Ops*/, 0, 1,
40456 MVT::f32, 1/*#Ops*/, 0,
40464 MVT::f32, 1/*#Ops*/, 0,
40473 MVT::f32, 2/*#Ops*/, 0, 1,
40481 MVT::f32, MVT::i32, 1/*#Ops*/, 0,
40490 MVT::f32, 2/*#Ops*/, 0, 1,
40499 MVT::f32, MVT::i32, 2/*#Ops*/, 0, 1,
40508 MVT::f32, 2/*#Ops*/, 0, 1,
40516 MVT::f32, 1/*#Ops*/, 0,
40543 MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
40553 MVT::f32, 3/*#Ops*/, 0, 1, 2,
51938 /* 97895*/ OPC_CheckChild0Type, MVT::f32,
51944 /* 97905*/ OPC_CheckType, MVT::f32,
51949 MVT::f32, 2/*#Ops*/, 0, 1,
51956 MVT::f32, 2/*#Ops*/, 0, 1,
51963 /* 97939*/ OPC_CheckType, MVT::f32,
51968 MVT::f32, 2/*#Ops*/, 0, 1,
51975 MVT::f32, 2/*#Ops*/, 0, 1,
51982 /* 97973*/ OPC_CheckType, MVT::f32,
51987 MVT::f32, 2/*#Ops*/, 0, 1,
51994 MVT::f32, 2/*#Ops*/, 0, 1,
52001 /* 98007*/ OPC_CheckType, MVT::f32,
52006 MVT::f32, 2/*#Ops*/, 0, 1,
52013 MVT::f32, 2/*#Ops*/, 0, 1,
52029 /* 98065*/ OPC_CheckType, MVT::f32,
52032 MVT::f32, 3/*#Ops*/, 0, 2, 3,
52040 /* 98086*/ OPC_CheckType, MVT::f32,
52043 MVT::f32, 3/*#Ops*/, 0, 3, 1,
52057 /* 98115*/ OPC_CheckType, MVT::f32,
52060 MVT::f32, 3/*#Ops*/, 0, 1, 3,
52068 /* 98136*/ OPC_CheckType, MVT::f32,
52071 MVT::f32, 3/*#Ops*/, 0, 3, 2,
52081 /* 98161*/ OPC_CheckChild0Type, MVT::f32,
52087 /* 98169*/ OPC_CheckType, MVT::f32,
52091 MVT::f32, 3/*#Ops*/, 4, 2, 3,
52114 /* 98224*/ OPC_SwitchType /*11 cases */, 9, MVT::f32,// ->98236
52116 MVT::f32, 3/*#Ops*/, 0, 1, 2,
59579 /*113836*/ /*SwitchType*/ 11, MVT::f32,// ->113849
59583 MVT::f32, 1/*#Ops*/, 2,
59613 /*113895*/ OPC_SwitchType /*2 cases */, 15, MVT::f32,// ->113913
59618 MVT::f32, 3/*#Ops*/, 1, 5, 4,
59646 /*113956*/ OPC_SwitchType /*2 cases */, 15, MVT::f32,// ->113974
59651 MVT::f32, 3/*#Ops*/, 2, 5, 4,
59669 /*114001*/ OPC_SwitchType /*2 cases */, 11, MVT::f32,// ->114015
59673 MVT::f32, 1/*#Ops*/, 2,
59703 /*114063*/ OPC_SwitchType /*2 cases */, 12, MVT::f32,// ->114078
59707 MVT::f32, 3/*#Ops*/, 1, 2, 4,
59734 /*114118*/ OPC_SwitchType /*2 cases */, 12, MVT::f32,// ->114133
59738 MVT::f32, 3/*#Ops*/, 3, 1, 4,
59756 /*114159*/ OPC_SwitchType /*2 cases */, 60, MVT::f32,// ->114222
59762 MVT::f32, 2/*#Ops*/, 3, 4,
59770 MVT::f32, 2/*#Ops*/, 4, 3,
59777 MVT::f32, 2/*#Ops*/, 1, 3,
59784 MVT::f32, 2/*#Ops*/, 2, 3,
59830 /*114301*/ OPC_SwitchType /*2 cases */, 60, MVT::f32,// ->114364
59836 MVT::f32, 2/*#Ops*/, 3, 4,
59844 MVT::f32, 2/*#Ops*/, 4, 3,
59851 MVT::f32, 2/*#Ops*/, 1, 3,
59858 MVT::f32, 2/*#Ops*/, 2, 3,
59901 /*114436*/ OPC_SwitchType /*2 cases */, 15, MVT::f32,// ->114454
59906 MVT::f32, 2/*#Ops*/, 2, 3,
59927 /*114486*/ OPC_SwitchType /*2 cases */, 13, MVT::f32,// ->114502
59931 MVT::f32, 3/*#Ops*/, 1, 2, 3,
59947 /*114527*/ OPC_SwitchType /*9 cases */, 12, MVT::f32,// ->114542
59951 MVT::f32, 2/*#Ops*/, 1, 2,
66580 /*127956*/ OPC_CheckChild0Type, MVT::f32,
66660 /*128064*/ OPC_SwitchType /*3 cases */, 3, MVT::f32,// ->128070
67107 /*128901*/ OPC_CheckChild0Type, MVT::f32,
67136 /*128953*/ OPC_CheckChild0Type, MVT::f32,
68283 /*132212*/ OPC_CheckType, MVT::f32,
68285 MVT::f32, 3/*#Ops*/, 2, 0, 1,
68296 /*132234*/ OPC_CheckType, MVT::f32,
68298 MVT::f32, 3/*#Ops*/, 2, 0, 1,
68304 /*132248*/ OPC_CheckType, MVT::f32,
68306 MVT::f32, 3/*#Ops*/, 2, 0, 1,
68313 /*132265*/ OPC_SwitchType /*2 cases */, 10, MVT::f32,// ->132278
68316 MVT::f32, 1/*#Ops*/, 1,
68335 MVT::f32, 1/*#Ops*/, 0,
68342 /*132321*/ OPC_SwitchType /*2 cases */, 7, MVT::f32,// ->132331
68344 MVT::f32, 1/*#Ops*/, 0,
68355 /*132344*/ OPC_SwitchType /*2 cases */, 7, MVT::f32,// ->132354
68357 MVT::f32, 1/*#Ops*/, 0,
68371 /*132373*/ OPC_SwitchType /*2 cases */, 7, MVT::f32,// ->132383
68373 MVT::f32, 1/*#Ops*/, 0,
68384 /*132396*/ OPC_SwitchType /*2 cases */, 7, MVT::f32,// ->132406
68386 MVT::f32, 1/*#Ops*/, 0,
68398 /*132421*/ OPC_SwitchType /*2 cases */, 11, MVT::f32,// ->132435
68401 MVT::f32, 2/*#Ops*/, 0, 1,
68424 /*132495*/ OPC_SwitchType /*2 cases */, 11, MVT::f32,// ->132509
68427 MVT::f32, 2/*#Ops*/, 0, 1,
68451 /*132570*/ OPC_SwitchType /*2 cases */, 8, MVT::f32,// ->132581
68453 MVT::f32, 2/*#Ops*/, 0, 1,
68466 /*132599*/ OPC_SwitchType /*2 cases */, 8, MVT::f32,// ->132610
68468 MVT::f32, 2/*#Ops*/, 0, 1,
68481 /*132628*/ OPC_CheckType, MVT::f32,
68483 MVT::f32, 2/*#Ops*/, 0, 1,
68489 /*132643*/ OPC_CheckType, MVT::f32,
68491 MVT::f32, 2/*#Ops*/, 0, 1,
68497 /*132658*/ OPC_CheckType, MVT::f32,
68499 MVT::f32, 2/*#Ops*/, 0, 1,
gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc 2344 /* 22 */ MVT::i32, MVT::f32, MVT::v4i8, MVT::v2i16, MVT::Other,
gen/lib/Target/Mips/MipsGenCallingConv.inc 164 if (LocVT == MVT::f32) {
190 if (LocVT == MVT::f32) {
298 if (LocVT == MVT::f32) {
319 if (LocVT == MVT::f32) {
353 LocVT == MVT::f32) {
505 if (LocVT == MVT::f32) {
517 if (LocVT == MVT::f32) {
530 LocVT == MVT::f32) {
754 if (LocVT == MVT::f32) {
806 if (LocVT == MVT::f32) {
gen/lib/Target/Mips/MipsGenDAGISel.inc 126 /* 124*/ OPC_CheckChild1Type, MVT::f32,
354 /* 539*/ OPC_CheckChild1Type, MVT::f32,
1170 /* 2069*/ /*SwitchType*/ 32, MVT::f32,// ->2103
1176 MVT::f32, 2/*#Ops*/, 2, 3,
1184 MVT::f32, 2/*#Ops*/, 2, 3,
1198 /* 2117*/ OPC_SwitchType /*2 cases */, 26, MVT::f32,// ->2146
1203 MVT::f32, 2/*#Ops*/, 1, 2,
1210 MVT::f32, 2/*#Ops*/, 1, 2,
1235 /* 2182*/ OPC_SwitchType /*12 cases */, 32, MVT::f32,// ->2217
1241 MVT::f32, 2/*#Ops*/, 2, 3,
1249 MVT::f32, 2/*#Ops*/, 2, 3,
5251 /* 10119*/ OPC_CheckType, MVT::f32,
5254 MVT::f32, 3/*#Ops*/, 1, 0, 2,
5262 /* 10138*/ OPC_CheckType, MVT::f32,
5265 MVT::f32, 3/*#Ops*/, 1, 0, 2,
5317 /* 10233*/ OPC_CheckType, MVT::f32,
5320 MVT::f32, 3/*#Ops*/, 1, 0, 2,
5328 /* 10252*/ OPC_CheckType, MVT::f32,
5331 MVT::f32, 3/*#Ops*/, 1, 0, 2,
5371 /* 10328*/ OPC_CheckType, MVT::f32,
5377 MVT::f32, 3/*#Ops*/, 2, 5, 3,
5385 /* 10357*/ OPC_CheckType, MVT::f32,
5391 MVT::f32, 3/*#Ops*/, 2, 5, 3,
5404 /* 10394*/ OPC_CheckType, MVT::f32,
5411 MVT::f32, 3/*#Ops*/, 2, 6, 3,
5419 /* 10426*/ OPC_CheckType, MVT::f32,
5426 MVT::f32, 3/*#Ops*/, 2, 6, 3,
5575 /* 10742*/ OPC_CheckType, MVT::f32,
5581 MVT::f32, 3/*#Ops*/, 2, 5, 3,
5589 /* 10771*/ OPC_CheckType, MVT::f32,
5595 MVT::f32, 3/*#Ops*/, 2, 5, 3,
5608 /* 10808*/ OPC_CheckType, MVT::f32,
5615 MVT::f32, 3/*#Ops*/, 2, 6, 3,
5623 /* 10840*/ OPC_CheckType, MVT::f32,
5630 MVT::f32, 3/*#Ops*/, 2, 6, 3,
5709 /* 11014*/ OPC_CheckType, MVT::f32,
5714 MVT::f32, 3/*#Ops*/, 2, 4, 3,
5723 /* 11043*/ OPC_CheckType, MVT::f32,
5728 MVT::f32, 3/*#Ops*/, 2, 4, 3,
5737 /* 11072*/ OPC_CheckType, MVT::f32,
5742 MVT::f32, 3/*#Ops*/, 2, 4, 3,
5751 /* 11101*/ OPC_CheckType, MVT::f32,
5756 MVT::f32, 3/*#Ops*/, 2, 4, 3,
5765 /* 11130*/ OPC_CheckType, MVT::f32,
5770 MVT::f32, 3/*#Ops*/, 2, 4, 3,
5779 /* 11159*/ OPC_CheckType, MVT::f32,
5784 MVT::f32, 3/*#Ops*/, 2, 4, 3,
5961 /* 11536*/ OPC_CheckType, MVT::f32,
5966 MVT::f32, 3/*#Ops*/, 2, 4, 3,
5975 /* 11565*/ OPC_CheckType, MVT::f32,
5980 MVT::f32, 3/*#Ops*/, 2, 4, 3,
5989 /* 11594*/ OPC_CheckType, MVT::f32,
5994 MVT::f32, 3/*#Ops*/, 2, 4, 3,
6003 /* 11623*/ OPC_CheckType, MVT::f32,
6008 MVT::f32, 3/*#Ops*/, 2, 4, 3,
6017 /* 11652*/ OPC_CheckType, MVT::f32,
6022 MVT::f32, 3/*#Ops*/, 2, 4, 3,
6031 /* 11681*/ OPC_CheckType, MVT::f32,
6036 MVT::f32, 3/*#Ops*/, 2, 4, 3,
6135 /* 11895*/ OPC_CheckType, MVT::f32,
6138 MVT::f32, 3/*#Ops*/, 1, 0, 2,
6146 /* 11914*/ OPC_CheckType, MVT::f32,
6149 MVT::f32, 3/*#Ops*/, 1, 0, 2,
6189 /* 11990*/ OPC_CheckType, MVT::f32,
6195 MVT::f32, 3/*#Ops*/, 2, 5, 3,
6203 /* 12019*/ OPC_CheckType, MVT::f32,
6209 MVT::f32, 3/*#Ops*/, 2, 5, 3,
6222 /* 12056*/ OPC_CheckType, MVT::f32,
6229 MVT::f32, 3/*#Ops*/, 2, 6, 3,
6237 /* 12088*/ OPC_CheckType, MVT::f32,
6244 MVT::f32, 3/*#Ops*/, 2, 6, 3,
6323 /* 12262*/ OPC_CheckType, MVT::f32,
6328 MVT::f32, 3/*#Ops*/, 2, 4, 3,
6337 /* 12291*/ OPC_CheckType, MVT::f32,
6342 MVT::f32, 3/*#Ops*/, 2, 4, 3,
6351 /* 12320*/ OPC_CheckType, MVT::f32,
6356 MVT::f32, 3/*#Ops*/, 2, 4, 3,
6365 /* 12349*/ OPC_CheckType, MVT::f32,
6370 MVT::f32, 3/*#Ops*/, 2, 4, 3,
6379 /* 12378*/ OPC_CheckType, MVT::f32,
6384 MVT::f32, 3/*#Ops*/, 2, 4, 3,
6393 /* 12407*/ OPC_CheckType, MVT::f32,
6398 MVT::f32, 3/*#Ops*/, 2, 4, 3,
6494 /* 12615*/ OPC_SwitchType /*2 cases */, 62, MVT::f32,// ->12680
6498 MVT::f32, 3/*#Ops*/, 1, 0, 2,
6504 MVT::f32, 3/*#Ops*/, 0, 2, 1,
6510 MVT::f32, 3/*#Ops*/, 1, 0, 2,
6516 MVT::f32, 3/*#Ops*/, 0, 2, 1,
6522 MVT::f32, 3/*#Ops*/, 0, 1, 2,
6563 /* 12750*/ OPC_SwitchType /*2 cases */, 11, MVT::f32,// ->12764
6566 MVT::f32, 3/*#Ops*/, 1, 0, 2,
17122 /* 31974*/ OPC_CheckChild0Type, MVT::f32,
22219 /* 41680*/ OPC_CheckType, MVT::f32,
22223 MVT::f32, 2/*#Ops*/, 0, 2,
22228 /* 41697*/ OPC_CheckType, MVT::f32,
22234 MVT::f32, 2/*#Ops*/, 2, 3,
22239 /* 41723*/ OPC_CheckType, MVT::f32,
22251 MVT::f32, 2/*#Ops*/, 6, 7,
23242 /* 43573*/ OPC_CheckChild0Type, MVT::f32,
23301 MVT::f32, 1/*#Ops*/, 0, // Results = #3
23303 MVT::f32, 1/*#Ops*/, 1, // Results = #4
24662 /* 46183*/ OPC_CheckChild0Type, MVT::f32,
24715 /* 46284*/ /*SwitchType*/ 13, MVT::f32,// ->46299
24719 MVT::f32, 2/*#Ops*/, 0, 1,
24732 /* 46319*/ /*SwitchType*/ 13, MVT::f32,// ->46334
24736 MVT::f32, 2/*#Ops*/, 0, 1,
24742 /* 46338*/ OPC_SwitchType /*3 cases */, 32, MVT::f32,// ->46373
24746 MVT::f32, 1/*#Ops*/, 0,
24752 MVT::f32, 1/*#Ops*/, 0,
24758 MVT::f32, 1/*#Ops*/, 0,
25704 /* 48683*/ /*SwitchType*/ 38, MVT::f32,// ->48723
25708 MVT::f32, 3/*#Ops*/, 0, 1, 2,
25714 MVT::f32, 3/*#Ops*/, 0, 1, 2,
25720 MVT::f32, 3/*#Ops*/, 1, 0, 2,
25796 /* 48865*/ /*SwitchType*/ 38, MVT::f32,// ->48905
25800 MVT::f32, 3/*#Ops*/, 0, 1, 2,
25806 MVT::f32, 3/*#Ops*/, 0, 1, 2,
25812 MVT::f32, 3/*#Ops*/, 1, 0, 2,
26733 /* 50609*/ OPC_SwitchType /*2 cases */, 11, MVT::f32,// ->50623
26736 MVT::f32, 3/*#Ops*/, 2, 0, 1,
26762 /* 50662*/ OPC_SwitchType /*2 cases */, 11, MVT::f32,// ->50676
26765 MVT::f32, 3/*#Ops*/, 0, 1, 2,
26792 /* 50718*/ OPC_SwitchType /*2 cases */, 11, MVT::f32,// ->50732
26795 MVT::f32, 3/*#Ops*/, 2, 0, 1,
26819 /* 50769*/ OPC_SwitchType /*2 cases */, 11, MVT::f32,// ->50783
26822 MVT::f32, 3/*#Ops*/, 2, 0, 1,
26845 /* 50819*/ OPC_SwitchType /*2 cases */, 35, MVT::f32,// ->50857
26849 MVT::f32, 2/*#Ops*/, 0, 1,
26855 MVT::f32, 2/*#Ops*/, 0, 1,
26861 MVT::f32, 2/*#Ops*/, 1, 0,
26940 /* 50996*/ OPC_SwitchType /*2 cases */, 26, MVT::f32,// ->51025
26944 MVT::f32, 3/*#Ops*/, 2, 0, 1,
26950 MVT::f32, 3/*#Ops*/, 2, 0, 1,
26983 /* 51076*/ OPC_SwitchType /*2 cases */, 26, MVT::f32,// ->51105
26987 MVT::f32, 3/*#Ops*/, 0, 1, 2,
26993 MVT::f32, 3/*#Ops*/, 0, 1, 2,
27027 /* 51159*/ OPC_SwitchType /*2 cases */, 26, MVT::f32,// ->51188
27031 MVT::f32, 3/*#Ops*/, 2, 0, 1,
27037 MVT::f32, 3/*#Ops*/, 2, 0, 1,
27065 /* 51232*/ OPC_SwitchType /*2 cases */, 32, MVT::f32,// ->51267
27069 MVT::f32, 1/*#Ops*/, 0,
27075 MVT::f32, 1/*#Ops*/, 0,
27081 MVT::f32, 1/*#Ops*/, 0,
27121 /* 51327*/ OPC_SwitchType /*2 cases */, 11, MVT::f32,// ->51341
27124 MVT::f32, 3/*#Ops*/, 2, 0, 1,
27150 /* 51382*/ OPC_SwitchType /*2 cases */, 11, MVT::f32,// ->51396
27153 MVT::f32, 3/*#Ops*/, 0, 1, 2,
27173 /* 51427*/ OPC_SwitchType /*2 cases */, 35, MVT::f32,// ->51465
27177 MVT::f32, 2/*#Ops*/, 0, 1,
27183 MVT::f32, 2/*#Ops*/, 0, 1,
27189 MVT::f32, 2/*#Ops*/, 1, 0,
27280 /* 51626*/ OPC_SwitchType /*2 cases */, 41, MVT::f32,// ->51670
27285 MVT::f32, 1/*#Ops*/, 0,
27292 MVT::f32, 1/*#Ops*/, 0,
27299 MVT::f32, 1/*#Ops*/, 0,
27313 /* 51689*/ OPC_SwitchType /*2 cases */, 62, MVT::f32,// ->51754
27318 MVT::f32, 1/*#Ops*/, 0, // Results = #1
27320 MVT::f32, 1/*#Ops*/, 1,
27327 MVT::f32, 1/*#Ops*/, 0, // Results = #1
27329 MVT::f32, 1/*#Ops*/, 1,
27336 MVT::f32, 1/*#Ops*/, 0, // Results = #1
27338 MVT::f32, 1/*#Ops*/, 1,
27355 /* 51782*/ OPC_SwitchType /*4 cases */, 22, MVT::f32,// ->51807
27359 MVT::f32, 1/*#Ops*/, 0,
27365 MVT::f32, 1/*#Ops*/, 0,
27410 /* 51878*/ OPC_SwitchType /*4 cases */, 22, MVT::f32,// ->51903
27414 MVT::f32, 1/*#Ops*/, 0,
27420 MVT::f32, 1/*#Ops*/, 0,
27466 /* 51975*/ OPC_SwitchType /*4 cases */, 35, MVT::f32,// ->52013
27470 MVT::f32, 2/*#Ops*/, 0, 1,
27476 MVT::f32, 2/*#Ops*/, 0, 1,
27482 MVT::f32, 2/*#Ops*/, 1, 0,
27530 /* 52096*/ OPC_SwitchType /*2 cases */, 35, MVT::f32,// ->52134
27534 MVT::f32, 2/*#Ops*/, 0, 1,
27540 MVT::f32, 2/*#Ops*/, 0, 1,
27546 MVT::f32, 2/*#Ops*/, 1, 0,
27652 /* 52318*/ OPC_SwitchType /*2 cases */, 7, MVT::f32,// ->52328
27654 MVT::f32, 1/*#Ops*/, 0,
27680 /* 52368*/ /*SwitchType*/ 20, MVT::f32,// ->52390
27686 MVT::f32, 2/*#Ops*/, 1, 2,
27710 /* 52427*/ OPC_CheckChild0Type, MVT::f32,
27711 /* 52429*/ OPC_SwitchType /*2 cases */, 32, MVT::f32,// ->52464
27715 MVT::f32, 1/*#Ops*/, 0,
27721 MVT::f32, 1/*#Ops*/, 0,
27727 MVT::f32, 1/*#Ops*/, 0,
27740 /* 52479*/ OPC_SwitchType /*2 cases */, 52, MVT::f32,// ->52534
27744 MVT::f32, 1/*#Ops*/, 0,
27750 MVT::f32, 1/*#Ops*/, 0,
27756 MVT::f32, 1/*#Ops*/, 0,
27762 MVT::f32, 1/*#Ops*/, 0,
27768 MVT::f32, 1/*#Ops*/, 0,
27781 /* 52549*/ OPC_CheckType, MVT::f32,
27786 MVT::f32, 1/*#Ops*/, 1,
27807 /* 52598*/ OPC_SwitchType /*2 cases */, 42, MVT::f32,// ->52643
27811 MVT::f32, 1/*#Ops*/, 0,
27817 MVT::f32, 1/*#Ops*/, 0,
27823 MVT::f32, 1/*#Ops*/, 0,
27829 MVT::f32, 1/*#Ops*/, 0,
27835 /* 52647*/ OPC_CheckChild0Type, MVT::f32,
27854 /* 52681*/ OPC_CheckChild0Type, MVT::f32,
27888 /* 52738*/ /*SwitchType*/ 9, MVT::f32,// ->52749
27891 MVT::f32, 1/*#Ops*/, 0,
28858 /* 54587*/ OPC_CheckChild1Type, MVT::f32,
29088 /* 55008*/ OPC_CheckChild0Type, MVT::f32,
gen/lib/Target/Mips/MipsGenFastISel.inc 56 if (RetVT.SimpleTy != MVT::f32)
107 case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0, Op0IsKill);
316 if (RetVT.SimpleTy != MVT::f32)
365 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
432 if (RetVT.SimpleTy != MVT::f32)
466 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
490 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(Op0, Op0IsKill);
517 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill);
559 case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(Op0, Op0IsKill);
566 case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
659 if (RetVT.SimpleTy != MVT::f32)
708 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
752 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill);
1040 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Op0, Op0IsKill);
1074 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Op0, Op0IsKill);
1082 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_r(RetVT, Op0, Op0IsKill);
1451 if (RetVT.SimpleTy != MVT::f32)
1500 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1511 if (RetVT.SimpleTy != MVT::f32)
1560 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1571 if (RetVT.SimpleTy != MVT::f32)
1620 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1631 if (RetVT.SimpleTy != MVT::f32)
1680 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3798 if (RetVT.SimpleTy != MVT::f32)
gen/lib/Target/Mips/MipsGenRegisterInfo.inc 3925 /* 6 */ MVT::f32, MVT::Other,
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc 3375 MVT::f32, 2/*#Ops*/, 0, 1,
3387 MVT::f32, 2/*#Ops*/, 0, 1,
3406 MVT::f32, 2/*#Ops*/, 0, 1,
3422 MVT::f32, 2/*#Ops*/, 0, 1,
3431 MVT::f32, 2/*#Ops*/, 0, 1,
3519 MVT::f32, 2/*#Ops*/, 0, 1,
3527 MVT::f32, 2/*#Ops*/, 0, 1,
3535 MVT::f32, 2/*#Ops*/, 0, 1,
3551 MVT::f32, 2/*#Ops*/, 0, 1,
3559 MVT::f32, 2/*#Ops*/, 0, 1,
3567 MVT::f32, 2/*#Ops*/, 0, 1,
3575 MVT::f32, 2/*#Ops*/, 0, 1,
3583 MVT::f32, 2/*#Ops*/, 0, 1,
3591 MVT::f32, 2/*#Ops*/, 0, 1,
3599 MVT::f32, 2/*#Ops*/, 0, 1,
3607 MVT::f32, 2/*#Ops*/, 0, 1,
3647 MVT::f32, 2/*#Ops*/, 0, 1,
3655 MVT::f32, 2/*#Ops*/, 0, 1,
3663 MVT::f32, 2/*#Ops*/, 0, 1,
3671 MVT::f32, 2/*#Ops*/, 0, 1,
3679 MVT::f32, 2/*#Ops*/, 0, 1,
3687 MVT::f32, 2/*#Ops*/, 0, 1,
3695 MVT::f32, 2/*#Ops*/, 0, 1,
3703 MVT::f32, 2/*#Ops*/, 0, 1,
3711 MVT::f32, 2/*#Ops*/, 0, 1,
3719 MVT::f32, 2/*#Ops*/, 0, 1,
3759 MVT::f32, 2/*#Ops*/, 0, 1,
3767 MVT::f32, 2/*#Ops*/, 0, 1,
3783 MVT::f32, 2/*#Ops*/, 0, 1,
3791 MVT::f32, 2/*#Ops*/, 0, 1,
3806 MVT::f32, 1/*#Ops*/, 0,
3813 MVT::f32, 1/*#Ops*/, 0,
3828 MVT::f32, 2/*#Ops*/, 0, 1,
3836 MVT::f32, 2/*#Ops*/, 0, 1,
3852 MVT::f32, 2/*#Ops*/, 0, 1,
3860 MVT::f32, 2/*#Ops*/, 0, 1,
3876 MVT::f32, 2/*#Ops*/, 0, 1,
3884 MVT::f32, 2/*#Ops*/, 0, 1,
3899 MVT::f32, 1/*#Ops*/, 0,
3906 MVT::f32, 1/*#Ops*/, 0,
3920 MVT::f32, 1/*#Ops*/, 0,
3927 MVT::f32, 1/*#Ops*/, 0,
3941 MVT::f32, 1/*#Ops*/, 0,
3948 MVT::f32, 1/*#Ops*/, 0,
3955 MVT::f32, 1/*#Ops*/, 0,
3962 MVT::f32, 1/*#Ops*/, 0,
3971 MVT::f32, 3/*#Ops*/, 0, 1, 2,
3980 MVT::f32, 3/*#Ops*/, 0, 1, 2,
3989 MVT::f32, 3/*#Ops*/, 0, 1, 2,
3998 MVT::f32, 3/*#Ops*/, 0, 1, 2,
4007 MVT::f32, 3/*#Ops*/, 0, 1, 2,
4016 MVT::f32, 3/*#Ops*/, 0, 1, 2,
4025 MVT::f32, 3/*#Ops*/, 0, 1, 2,
4034 MVT::f32, 3/*#Ops*/, 0, 1, 2,
4077 MVT::f32, 1/*#Ops*/, 0,
4084 MVT::f32, 1/*#Ops*/, 0,
4091 MVT::f32, 1/*#Ops*/, 0,
4098 MVT::f32, 1/*#Ops*/, 0,
4105 MVT::f32, 1/*#Ops*/, 0,
4112 MVT::f32, 1/*#Ops*/, 0,
4119 MVT::f32, 1/*#Ops*/, 0,
4126 MVT::f32, 1/*#Ops*/, 0,
4168 MVT::f32, 1/*#Ops*/, 0,
4175 MVT::f32, 1/*#Ops*/, 0,
4182 MVT::f32, 1/*#Ops*/, 0,
4189 MVT::f32, 1/*#Ops*/, 0,
4196 MVT::f32, 1/*#Ops*/, 0,
4203 MVT::f32, 1/*#Ops*/, 0,
4210 MVT::f32, 1/*#Ops*/, 0,
4217 MVT::f32, 1/*#Ops*/, 0,
4224 MVT::f32, 1/*#Ops*/, 0,
4231 MVT::f32, 1/*#Ops*/, 0,
4268 MVT::f32, 1/*#Ops*/, 0,
4274 MVT::f32, 1/*#Ops*/, 0,
4280 MVT::f32, 1/*#Ops*/, 0,
4285 MVT::f32, 1/*#Ops*/, 0,
4293 MVT::f32, 1/*#Ops*/, 0,
4300 MVT::f32, 1/*#Ops*/, 0,
4315 MVT::f32, 2/*#Ops*/, 0, 1,
4323 MVT::f32, 2/*#Ops*/, 0, 1,
4331 MVT::f32, 2/*#Ops*/, 0, 1,
4339 MVT::f32, 2/*#Ops*/, 0, 1,
4347 MVT::f32, 2/*#Ops*/, 0, 1,
4355 MVT::f32, 2/*#Ops*/, 0, 1,
4363 MVT::f32, 2/*#Ops*/, 0, 1,
4371 MVT::f32, 2/*#Ops*/, 0, 1,
4411 MVT::f32, 2/*#Ops*/, 0, 1,
4419 MVT::f32, 2/*#Ops*/, 0, 1,
4427 MVT::f32, 2/*#Ops*/, 0, 1,
4435 MVT::f32, 2/*#Ops*/, 0, 1,
4443 MVT::f32, 2/*#Ops*/, 0, 1,
4451 MVT::f32, 2/*#Ops*/, 0, 1,
4459 MVT::f32, 2/*#Ops*/, 0, 1,
4467 MVT::f32, 2/*#Ops*/, 0, 1,
4539 MVT::f32, 2/*#Ops*/, 0, 1,
4547 MVT::f32, 2/*#Ops*/, 0, 1,
4555 MVT::f32, 2/*#Ops*/, 0, 1,
4563 MVT::f32, 2/*#Ops*/, 0, 1,
4571 MVT::f32, 2/*#Ops*/, 0, 1,
4579 MVT::f32, 2/*#Ops*/, 0, 1,
4587 MVT::f32, 2/*#Ops*/, 0, 1,
4595 MVT::f32, 2/*#Ops*/, 0, 1,
4611 MVT::f32, 2/*#Ops*/, 0, 1,
4619 MVT::f32, 2/*#Ops*/, 0, 1,
4627 MVT::f32, 2/*#Ops*/, 0, 1,
4635 MVT::f32, 2/*#Ops*/, 0, 1,
4643 MVT::f32, 2/*#Ops*/, 0, 1,
4651 MVT::f32, 2/*#Ops*/, 0, 1,
4659 MVT::f32, 2/*#Ops*/, 0, 1,
4667 MVT::f32, 2/*#Ops*/, 0, 1,
4738 MVT::f32, 1/*#Ops*/, 0,
4752 MVT::f32, 1/*#Ops*/, 0,
4778 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
4778 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
4778 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
4778 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
4778 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
4778 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
4778 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
4778 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
4809 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
4809 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
4809 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
4809 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
4809 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
4809 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
4809 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
4809 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
4864 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
4864 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
4864 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
4864 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
4864 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
4864 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
4864 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
4864 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
4931 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
4931 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
4931 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
4931 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
4931 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
4931 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
4931 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
4931 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
4986 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
4986 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
4986 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
4986 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
4986 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
4986 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
4986 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
4986 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5053 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5053 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5053 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5053 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5053 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5053 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5053 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5053 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5108 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5108 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5108 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5108 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5108 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5108 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5108 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5108 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5175 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5175 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5175 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5175 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5175 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5175 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5175 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5175 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5230 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5230 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5230 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5230 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5230 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5230 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5230 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5230 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5297 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5297 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5297 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5297 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5297 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5297 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5297 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5297 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5352 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5352 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5352 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5352 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5352 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5352 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5352 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5352 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5419 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5419 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5419 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5419 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5419 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5419 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5419 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5419 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5474 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5474 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5474 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5474 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5474 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5474 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5474 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5474 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5541 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5541 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5541 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5541 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5541 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5541 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5541 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5541 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5560 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
5560 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
5560 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
5560 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
5560 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
5560 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
5560 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
5560 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
5591 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
5591 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
5591 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
5591 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
5591 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
5591 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
5591 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
5591 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
5646 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5646 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5646 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5646 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5646 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5646 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5646 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5646 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5713 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5713 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5713 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5713 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5713 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5713 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5713 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5713 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5768 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5768 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5768 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5768 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5768 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5768 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5768 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5768 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5835 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5835 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5835 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5835 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5835 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5835 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5835 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5835 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5890 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5890 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5890 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5890 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5890 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5890 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5890 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5890 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
5957 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5957 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5957 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5957 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5957 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5957 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5957 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
5957 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6012 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6012 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6012 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6012 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6012 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6012 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6012 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6012 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6079 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6079 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6079 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6079 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6079 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6079 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6079 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6079 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6134 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6134 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6134 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6134 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6134 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6134 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6134 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6134 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6201 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6201 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6201 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6201 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6201 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6201 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6201 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6201 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6256 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6256 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6256 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6256 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6256 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6256 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6256 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6256 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6323 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6323 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6323 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6323 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6323 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6323 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6323 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6323 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6342 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
6342 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
6342 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
6342 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
6342 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
6342 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
6342 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
6342 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
6373 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
6373 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
6373 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
6373 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
6373 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
6373 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
6373 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
6373 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
6428 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6428 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6428 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6428 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6428 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6428 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6428 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6428 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6495 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6495 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6495 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6495 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6495 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6495 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6495 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6495 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6550 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6550 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6550 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6550 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6550 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6550 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6550 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6550 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6617 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6617 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6617 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6617 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6617 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6617 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6617 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6617 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6672 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6672 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6672 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6672 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6672 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6672 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6672 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6672 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6739 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6739 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6739 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6739 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6739 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6739 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6739 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6739 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6794 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6794 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6794 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6794 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6794 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6794 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6794 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6794 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6861 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6861 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6861 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6861 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6861 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6861 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6861 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6861 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6916 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6916 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6916 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6916 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6916 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6916 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6916 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6916 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
6983 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6983 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6983 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6983 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6983 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6983 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6983 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
6983 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7038 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7038 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7038 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7038 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7038 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7038 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7038 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7038 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7105 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7105 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7105 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7105 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7105 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7105 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7105 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7105 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7124 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
7124 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
7124 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
7124 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
7124 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
7124 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
7124 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
7124 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 9/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 9,
7155 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
7155 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
7155 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
7155 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
7155 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
7155 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
7155 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
7155 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 13/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
7210 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7210 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7210 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7210 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7210 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7210 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7210 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7210 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7277 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7277 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7277 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7277 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7277 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7277 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7277 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7277 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7332 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7332 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7332 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7332 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7332 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7332 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7332 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7332 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7399 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7399 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7399 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7399 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7399 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7399 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7399 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7399 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7454 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7454 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7454 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7454 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7454 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7454 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7454 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7454 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7521 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7521 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7521 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7521 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7521 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7521 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7521 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7521 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7576 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7576 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7576 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7576 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7576 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7576 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7576 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7576 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7643 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7643 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7643 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7643 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7643 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7643 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7643 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7643 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7698 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7698 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7698 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7698 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7698 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7698 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7698 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7698 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7765 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7765 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7765 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7765 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7765 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7765 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7765 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7765 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7820 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7820 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7820 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7820 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7820 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7820 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7820 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7820 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 21/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21,
7887 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7887 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7887 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7887 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7887 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7887 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7887 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
7887 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 25/*#Ops*/, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25,
29608 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29608 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29608 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29608 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29608 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29608 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29608 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29608 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29619 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29619 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29619 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29619 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29619 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29619 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29619 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29619 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29630 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29630 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29630 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29630 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29630 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29630 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29630 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29630 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29644 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29644 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29644 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29644 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29644 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29644 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29644 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29644 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29655 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29655 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29655 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29655 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29655 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29655 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29655 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29655 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29666 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29666 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29666 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29666 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29666 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29666 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29666 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29666 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29678 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29678 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29678 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29678 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29678 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29678 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29678 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29678 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29689 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29689 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29689 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29689 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29689 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29689 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29689 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29689 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29700 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29700 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29700 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29700 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29700 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29700 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29700 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29700 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29712 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29712 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29712 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29712 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29712 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29712 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29712 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29712 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29722 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29722 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29722 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29722 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29722 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29722 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29722 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29722 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29732 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29732 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29732 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29732 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29732 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29732 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29732 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29732 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29745 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29745 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29745 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29745 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29745 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29745 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29745 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29745 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29755 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29755 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29755 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29755 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29755 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29755 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29755 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29755 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29765 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29765 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29765 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29765 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29765 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29765 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29765 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29765 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29783 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29783 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29783 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29783 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29783 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29783 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29783 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29783 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29794 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29794 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29794 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29794 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29794 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29794 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29794 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29794 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29805 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29805 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29805 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29805 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29805 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29805 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29805 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29805 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29819 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29819 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29819 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29819 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29819 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29819 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29819 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29819 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29830 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29830 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29830 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29830 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29830 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29830 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29830 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29830 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29841 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29841 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29841 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29841 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29841 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29841 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29841 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29841 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29853 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29853 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29853 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29853 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29853 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29853 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29853 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29853 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29864 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29864 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29864 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29864 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29864 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29864 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29864 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29864 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29875 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29875 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29875 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29875 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29875 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29875 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29875 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29875 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
29887 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29887 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29887 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29887 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29887 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29887 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29887 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29887 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29897 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29897 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29897 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29897 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29897 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29897 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29897 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29897 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29907 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29907 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29907 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29907 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29907 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29907 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29907 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29907 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29920 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29920 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29920 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29920 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29920 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29920 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29920 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29920 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29930 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29930 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29930 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29930 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29930 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29930 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29930 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29930 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29940 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29940 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29940 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29940 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29940 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29940 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29940 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29940 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
29958 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29958 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29958 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29958 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29958 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29958 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29958 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29958 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29969 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29969 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29969 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29969 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29969 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29969 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29969 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29969 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29980 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29980 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29980 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29980 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29980 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29980 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29980 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29980 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29994 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29994 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29994 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29994 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29994 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29994 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29994 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
29994 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30005 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30005 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30005 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30005 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30005 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30005 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30005 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30005 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30016 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30016 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30016 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30016 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30016 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30016 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30016 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30016 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30028 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30028 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30028 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30028 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30028 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30028 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30028 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30028 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30039 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30039 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30039 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30039 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30039 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30039 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30039 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30039 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30050 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30050 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30050 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30050 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30050 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30050 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30050 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30050 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30062 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30062 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30062 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30062 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30062 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30062 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30062 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30062 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30072 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30072 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30072 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30072 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30072 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30072 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30072 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30072 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30082 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30082 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30082 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30082 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30082 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30082 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30082 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30082 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30095 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30095 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30095 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30095 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30095 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30095 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30095 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30095 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30105 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30105 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30105 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30105 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30105 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30105 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30105 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30105 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30115 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30115 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30115 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30115 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30115 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30115 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30115 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30115 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30134 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30134 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30134 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30134 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30134 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30134 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30134 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30134 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30145 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30145 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30145 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30145 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30145 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30145 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30145 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30145 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30156 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30156 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30156 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30156 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30156 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30156 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30156 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30156 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30171 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30171 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30171 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30171 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30171 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30171 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30171 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30171 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30182 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30182 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30182 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30182 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30182 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30182 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30182 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30182 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30193 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30193 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30193 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30193 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30193 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30193 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30193 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30193 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30207 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30207 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30207 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30207 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30207 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30207 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30207 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30207 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30218 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30218 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30218 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30218 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30218 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30218 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30218 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30218 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30229 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30229 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30229 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30229 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30229 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30229 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30229 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30229 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30243 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30243 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30243 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30243 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30243 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30243 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30243 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30243 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30253 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30253 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30253 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30253 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30253 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30253 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30253 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30253 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30263 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30263 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30263 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30263 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30263 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30263 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30263 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30263 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30277 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30277 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30277 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30277 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30277 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30277 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30277 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30277 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30287 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30287 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30287 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30287 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30287 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30287 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30287 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30287 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30297 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30297 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30297 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30297 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30297 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30297 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30297 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30297 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30316 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30316 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30316 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30316 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30316 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30316 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30316 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30316 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30327 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30327 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30327 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30327 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30327 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30327 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30327 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30327 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30338 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30338 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30338 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30338 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30338 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30338 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30338 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30338 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30353 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30353 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30353 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30353 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30353 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30353 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30353 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30353 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30364 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30364 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30364 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30364 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30364 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30364 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30364 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30364 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30375 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30375 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30375 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30375 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30375 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30375 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30375 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30375 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30389 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30389 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30389 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30389 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30389 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30389 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30389 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30389 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30400 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30400 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30400 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30400 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30400 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30400 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30400 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30400 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30411 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30411 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30411 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30411 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30411 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30411 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30411 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30411 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30425 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30425 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30425 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30425 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30425 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30425 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30425 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30425 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30435 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30435 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30435 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30435 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30435 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30435 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30435 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30435 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30445 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30445 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30445 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30445 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30445 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30445 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30445 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30445 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30459 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30459 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30459 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30459 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30459 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30459 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30459 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30459 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30469 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30469 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30469 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30469 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30469 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30469 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30469 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30469 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30479 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30479 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30479 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30479 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30479 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30479 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30479 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30479 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30498 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30498 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30498 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30498 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30498 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30498 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30498 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30498 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30509 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30509 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30509 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30509 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30509 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30509 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30509 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30509 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30520 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30520 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30520 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30520 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30520 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30520 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30520 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30520 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30535 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30535 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30535 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30535 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30535 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30535 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30535 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30535 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30546 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30546 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30546 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30546 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30546 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30546 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30546 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30546 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30557 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30557 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30557 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30557 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30557 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30557 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30557 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30557 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
30571 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30571 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30571 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30571 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30571 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30571 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30571 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30571 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30582 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30582 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30582 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30582 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30582 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30582 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30582 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30582 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30593 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30593 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30593 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30593 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30593 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30593 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30593 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30593 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
30607 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30607 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30607 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30607 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30607 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30607 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30607 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30607 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30617 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30617 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30617 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30617 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30617 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30617 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30617 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30617 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30627 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30627 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30627 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30627 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30627 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30627 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30627 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30627 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30641 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30641 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30641 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30641 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30641 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30641 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30641 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30641 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30651 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30651 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30651 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30651 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30651 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30651 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30651 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30651 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30661 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30661 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30661 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30661 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30661 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30661 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30661 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30661 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
30679 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30679 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30679 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30679 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30679 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30679 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30679 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30679 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30690 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30690 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30690 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30690 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30690 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30690 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30690 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30690 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30701 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30701 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30701 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30701 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30701 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30701 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30701 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30701 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30715 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30715 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30715 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30715 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30715 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30715 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30715 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30715 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30726 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30726 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30726 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30726 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30726 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30726 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30726 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30726 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30737 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30737 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30737 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30737 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30737 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30737 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30737 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30737 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30749 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30749 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30749 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30749 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30749 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30749 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30749 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30749 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30760 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30760 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30760 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30760 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30760 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30760 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30760 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30760 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30771 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30771 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30771 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30771 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30771 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30771 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30771 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30771 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30783 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30783 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30783 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30783 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30783 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30783 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30783 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30783 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30793 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30793 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30793 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30793 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30793 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30793 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30793 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30793 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30803 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30803 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30803 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30803 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30803 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30803 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30803 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30803 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30816 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30816 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30816 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30816 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30816 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30816 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30816 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30816 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30826 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30826 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30826 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30826 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30826 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30826 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30826 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30826 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30836 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30836 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30836 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30836 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30836 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30836 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30836 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30836 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30854 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30854 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30854 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30854 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30854 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30854 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30854 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30854 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30865 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30865 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30865 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30865 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30865 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30865 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30865 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30865 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30876 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30876 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30876 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30876 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30876 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30876 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30876 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30876 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30890 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30890 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30890 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30890 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30890 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30890 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30890 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30890 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30901 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30901 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30901 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30901 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30901 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30901 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30901 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30901 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30912 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30912 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30912 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30912 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30912 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30912 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30912 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30912 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
30924 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30924 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30924 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30924 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30924 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30924 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30924 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30924 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30935 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30935 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30935 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30935 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30935 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30935 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30935 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30935 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30946 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30946 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30946 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30946 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30946 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30946 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30946 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30946 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
30958 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30958 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30958 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30958 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30958 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30958 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30958 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30958 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30968 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30968 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30968 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30968 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30968 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30968 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30968 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30968 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30978 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30978 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30978 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30978 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30978 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30978 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30978 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30978 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30991 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30991 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30991 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30991 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30991 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30991 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30991 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
30991 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31001 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31001 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31001 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31001 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31001 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31001 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31001 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31001 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31011 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31011 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31011 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31011 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31011 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31011 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31011 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31011 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31029 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31029 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31029 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31029 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31029 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31029 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31029 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31029 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31040 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31040 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31040 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31040 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31040 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31040 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31040 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31040 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31051 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31051 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31051 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31051 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31051 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31051 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31051 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31051 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31065 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31065 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31065 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31065 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31065 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31065 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31065 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31065 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31076 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31076 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31076 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31076 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31076 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31076 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31076 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31076 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31087 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31087 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31087 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31087 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31087 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31087 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31087 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31087 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 2, 3, 5,
31099 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
31099 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
31099 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
31099 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
31099 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
31099 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
31099 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
31099 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
31110 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
31110 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
31110 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
31110 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
31110 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
31110 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
31110 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
31110 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
31121 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
31121 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
31121 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
31121 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
31121 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
31121 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
31121 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
31121 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 2, 4,
31133 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31133 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31133 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31133 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31133 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31133 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31133 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31133 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31143 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31143 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31143 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31143 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31143 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31143 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31143 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31143 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31153 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31153 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31153 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31153 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31153 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31153 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31153 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31153 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31166 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31166 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31166 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31166 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31166 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31166 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31166 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31166 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31176 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31176 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31176 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31176 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31176 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31176 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31176 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31176 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31186 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31186 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31186 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31186 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31186 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31186 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31186 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31186 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 2/*#Ops*/, 1, 3,
31205 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31205 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31205 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31205 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31205 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31205 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31205 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31205 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31216 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31216 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31216 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31216 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31216 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31216 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31216 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31216 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31227 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31227 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31227 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31227 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31227 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31227 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31227 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31227 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31242 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31242 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31242 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31242 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31242 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31242 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31242 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31242 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31253 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31253 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31253 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31253 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31253 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31253 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31253 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31253 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31264 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31264 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31264 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31264 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31264 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31264 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31264 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31264 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31278 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31278 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31278 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31278 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31278 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31278 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31278 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31278 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31289 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31289 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31289 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31289 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31289 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31289 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31289 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31289 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31300 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31300 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31300 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31300 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31300 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31300 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31300 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31300 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31314 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31314 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31314 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31314 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31314 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31314 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31314 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31314 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31324 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31324 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31324 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31324 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31324 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31324 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31324 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31324 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31334 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31334 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31334 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31334 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31334 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31334 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31334 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31334 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31348 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31348 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31348 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31348 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31348 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31348 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31348 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31348 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31358 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31358 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31358 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31358 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31358 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31358 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31358 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31358 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31368 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31368 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31368 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31368 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31368 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31368 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31368 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31368 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31387 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31387 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31387 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31387 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31387 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31387 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31387 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31387 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31398 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31398 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31398 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31398 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31398 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31398 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31398 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31398 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31409 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31409 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31409 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31409 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31409 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31409 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31409 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31409 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31424 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31424 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31424 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31424 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31424 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31424 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31424 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31424 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31435 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31435 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31435 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31435 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31435 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31435 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31435 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31435 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31446 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31446 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31446 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31446 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31446 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31446 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31446 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31446 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31460 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31460 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31460 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31460 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31460 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31460 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31460 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31460 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31471 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31471 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31471 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31471 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31471 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31471 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31471 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31471 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31482 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31482 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31482 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31482 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31482 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31482 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31482 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31482 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31496 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31496 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31496 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31496 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31496 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31496 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31496 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31496 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31506 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31506 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31506 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31506 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31506 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31506 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31506 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31506 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31516 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31516 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31516 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31516 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31516 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31516 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31516 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31516 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31530 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31530 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31530 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31530 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31530 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31530 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31530 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31530 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31540 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31540 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31540 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31540 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31540 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31540 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31540 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31540 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31550 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31550 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31550 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31550 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31550 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31550 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31550 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31550 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31569 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31569 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31569 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31569 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31569 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31569 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31569 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31569 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31580 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31580 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31580 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31580 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31580 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31580 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31580 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31580 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31591 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31591 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31591 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31591 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31591 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31591 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31591 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31591 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31606 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31606 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31606 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31606 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31606 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31606 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31606 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31606 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31617 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31617 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31617 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31617 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31617 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31617 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31617 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31617 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31628 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31628 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31628 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31628 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31628 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31628 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31628 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31628 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 4/*#Ops*/, 3, 4, 2, 6,
31642 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31642 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31642 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31642 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31642 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31642 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31642 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31642 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31653 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31653 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31653 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31653 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31653 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31653 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31653 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31653 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31664 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31664 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31664 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31664 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31664 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31664 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31664 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31664 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 3, 2, 5,
31678 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31678 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31678 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31678 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31678 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31678 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31678 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31678 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31688 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31688 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31688 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31688 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31688 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31688 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31688 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31688 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31698 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31698 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31698 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31698 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31698 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31698 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31698 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31698 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31712 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31712 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31712 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31712 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31712 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31712 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31712 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31712 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31722 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31722 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31722 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31722 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31722 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31722 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31722 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31722 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31732 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31732 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31732 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31732 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31732 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31732 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31732 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31732 8/*#VTs*/, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, MVT::f32, 3/*#Ops*/, 1, 2, 4,
31760 MVT::f32, 4/*#Ops*/, 5, 2, 6, 7,
31773 MVT::f32, 4/*#Ops*/, 5, 2, 3, 6,
31786 MVT::f32, 4/*#Ops*/, 5, 2, 6, 4,
31805 MVT::f32, 4/*#Ops*/, 1, 2, 5, 6,
31819 MVT::f32, 4/*#Ops*/, 5, 2, 3, 4,
31834 MVT::f32, 4/*#Ops*/, 1, 2, 3, 5,
31846 MVT::f32, 4/*#Ops*/, 1, 2, 5, 4,
31854 MVT::f32, 4/*#Ops*/, 1, 2, 3, 4,
31882 MVT::f32, MVT::i1, 4/*#Ops*/, 5, 2, 6, 7,
31895 MVT::f32, MVT::i1, 4/*#Ops*/, 5, 2, 3, 6,
31908 MVT::f32, MVT::i1, 4/*#Ops*/, 5, 2, 6, 4,
31927 MVT::f32, MVT::i1, 4/*#Ops*/, 1, 2, 5, 6,
31941 MVT::f32, MVT::i1, 4/*#Ops*/, 5, 2, 3, 4,
31956 MVT::f32, MVT::i1, 4/*#Ops*/, 1, 2, 3, 5,
31968 MVT::f32, MVT::i1, 4/*#Ops*/, 1, 2, 5, 4,
31976 MVT::f32, MVT::i1, 4/*#Ops*/, 1, 2, 3, 4,
32004 MVT::f32, 4/*#Ops*/, 5, 2, 6, 7,
32017 MVT::f32, 4/*#Ops*/, 5, 2, 3, 6,
32030 MVT::f32, 4/*#Ops*/, 5, 2, 6, 4,
32049 MVT::f32, 4/*#Ops*/, 1, 2, 5, 6,
32063 MVT::f32, 4/*#Ops*/, 5, 2, 3, 4,
32078 MVT::f32, 4/*#Ops*/, 1, 2, 3, 5,
32090 MVT::f32, 4/*#Ops*/, 1, 2, 5, 4,
32098 MVT::f32, 4/*#Ops*/, 1, 2, 3, 4,
32126 MVT::f32, MVT::i1, 4/*#Ops*/, 5, 2, 6, 7,
32139 MVT::f32, MVT::i1, 4/*#Ops*/, 5, 2, 3, 6,
32152 MVT::f32, MVT::i1, 4/*#Ops*/, 5, 2, 6, 4,
32171 MVT::f32, MVT::i1, 4/*#Ops*/, 1, 2, 5, 6,
32185 MVT::f32, MVT::i1, 4/*#Ops*/, 5, 2, 3, 4,
32200 MVT::f32, MVT::i1, 4/*#Ops*/, 1, 2, 3, 5,
32212 MVT::f32, MVT::i1, 4/*#Ops*/, 1, 2, 5, 4,
32220 MVT::f32, MVT::i1, 4/*#Ops*/, 1, 2, 3, 4,
32248 MVT::f32, 4/*#Ops*/, 5, 2, 6, 7,
32261 MVT::f32, 4/*#Ops*/, 5, 2, 3, 6,
32274 MVT::f32, 4/*#Ops*/, 5, 2, 6, 4,
32293 MVT::f32, 4/*#Ops*/, 1, 2, 5, 6,
32307 MVT::f32, 4/*#Ops*/, 5, 2, 3, 4,
32322 MVT::f32, 4/*#Ops*/, 1, 2, 3, 5,
32334 MVT::f32, 4/*#Ops*/, 1, 2, 5, 4,
32342 MVT::f32, 4/*#Ops*/, 1, 2, 3, 4,
32370 MVT::f32, MVT::i1, 4/*#Ops*/, 5, 2, 6, 7,
32383 MVT::f32, MVT::i1, 4/*#Ops*/, 5, 2, 3, 6,
32396 MVT::f32, MVT::i1, 4/*#Ops*/, 5, 2, 6, 4,
32415 MVT::f32, MVT::i1, 4/*#Ops*/, 1, 2, 5, 6,
32429 MVT::f32, MVT::i1, 4/*#Ops*/, 5, 2, 3, 4,
32444 MVT::f32, MVT::i1, 4/*#Ops*/, 1, 2, 3, 5,
32456 MVT::f32, MVT::i1, 4/*#Ops*/, 1, 2, 5, 4,
32464 MVT::f32, MVT::i1, 4/*#Ops*/, 1, 2, 3, 4,
32492 MVT::f32, 4/*#Ops*/, 5, 2, 6, 7,
32505 MVT::f32, 4/*#Ops*/, 5, 2, 3, 6,
32518 MVT::f32, 4/*#Ops*/, 5, 2, 6, 4,
32537 MVT::f32, 4/*#Ops*/, 1, 2, 5, 6,
32551 MVT::f32, 4/*#Ops*/, 5, 2, 3, 4,
32566 MVT::f32, 4/*#Ops*/, 1, 2, 3, 5,
32578 MVT::f32, 4/*#Ops*/, 1, 2, 5, 4,
32586 MVT::f32, 4/*#Ops*/, 1, 2, 3, 4,
32614 MVT::f32, MVT::i1, 4/*#Ops*/, 5, 2, 6, 7,
32627 MVT::f32, MVT::i1, 4/*#Ops*/, 5, 2, 3, 6,
32640 MVT::f32, MVT::i1, 4/*#Ops*/, 5, 2, 6, 4,
32659 MVT::f32, MVT::i1, 4/*#Ops*/, 1, 2, 5, 6,
32673 MVT::f32, MVT::i1, 4/*#Ops*/, 5, 2, 3, 4,
32688 MVT::f32, MVT::i1, 4/*#Ops*/, 1, 2, 3, 5,
32700 MVT::f32, MVT::i1, 4/*#Ops*/, 1, 2, 5, 4,
32708 MVT::f32, MVT::i1, 4/*#Ops*/, 1, 2, 3, 4,
32730 MVT::f32, 3/*#Ops*/, 1, 4, 5,
32742 MVT::f32, 3/*#Ops*/, 1, 2, 4,
32754 MVT::f32, 3/*#Ops*/, 1, 4, 3,
32762 MVT::f32, 3/*#Ops*/, 1, 2, 3,
32783 MVT::f32, MVT::i1, 3/*#Ops*/, 1, 4, 5,
32795 MVT::f32, MVT::i1, 3/*#Ops*/, 1, 2, 4,
32807 MVT::f32, MVT::i1, 3/*#Ops*/, 1, 4, 3,
32815 MVT::f32, MVT::i1, 3/*#Ops*/, 1, 2, 3,
32836 MVT::f32, 3/*#Ops*/, 1, 4, 5,
32848 MVT::f32, 3/*#Ops*/, 1, 2, 4,
32860 MVT::f32, 3/*#Ops*/, 1, 4, 3,
32868 MVT::f32, 3/*#Ops*/, 1, 2, 3,
32889 MVT::f32, MVT::i1, 3/*#Ops*/, 1, 4, 5,
32901 MVT::f32, MVT::i1, 3/*#Ops*/, 1, 2, 4,
32913 MVT::f32, MVT::i1, 3/*#Ops*/, 1, 4, 3,
32921 MVT::f32, MVT::i1, 3/*#Ops*/, 1, 2, 3,
32942 MVT::f32, 3/*#Ops*/, 1, 4, 5,
32954 MVT::f32, 3/*#Ops*/, 1, 2, 4,
32966 MVT::f32, 3/*#Ops*/, 1, 4, 3,
32974 MVT::f32, 3/*#Ops*/, 1, 2, 3,
32995 MVT::f32, MVT::i1, 3/*#Ops*/, 1, 4, 5,
33007 MVT::f32, MVT::i1, 3/*#Ops*/, 1, 2, 4,
33019 MVT::f32, MVT::i1, 3/*#Ops*/, 1, 4, 3,
33027 MVT::f32, MVT::i1, 3/*#Ops*/, 1, 2, 3,
33048 MVT::f32, 3/*#Ops*/, 1, 4, 5,
33060 MVT::f32, 3/*#Ops*/, 1, 2, 4,
33072 MVT::f32, 3/*#Ops*/, 1, 4, 3,
33080 MVT::f32, 3/*#Ops*/, 1, 2, 3,
33101 MVT::f32, MVT::i1, 3/*#Ops*/, 1, 4, 5,
33113 MVT::f32, MVT::i1, 3/*#Ops*/, 1, 2, 4,
33125 MVT::f32, MVT::i1, 3/*#Ops*/, 1, 4, 3,
33133 MVT::f32, MVT::i1, 3/*#Ops*/, 1, 2, 3,
33146 /* 69567*/ OPC_SwitchType /*2 cases */, 16, MVT::f32,// ->69586
33148 /* 69571*/ OPC_CheckType, MVT::f32,
33153 MVT::f32, 2/*#Ops*/, 1, 3,
33168 /* 69606*/ OPC_CheckChild3Type, MVT::f32,
33169 /* 69608*/ OPC_CheckType, MVT::f32,
33173 MVT::f32, 2/*#Ops*/, 1, 2,
33192 /* 69648*/ OPC_SwitchType /*2 cases */, 16, MVT::f32,// ->69667
33194 /* 69652*/ OPC_CheckType, MVT::f32,
33199 MVT::f32, 2/*#Ops*/, 1, 3,
33214 /* 69687*/ OPC_CheckChild3Type, MVT::f32,
33215 /* 69689*/ OPC_CheckType, MVT::f32,
33219 MVT::f32, 2/*#Ops*/, 1, 2,
33242 /* 69737*/ OPC_SwitchType /*2 cases */, 16, MVT::f32,// ->69756
33244 /* 69741*/ OPC_CheckType, MVT::f32,
33249 MVT::f32, 2/*#Ops*/, 1, 3,
33264 /* 69776*/ OPC_CheckChild3Type, MVT::f32,
33265 /* 69778*/ OPC_CheckType, MVT::f32,
33269 MVT::f32, 2/*#Ops*/, 1, 2,
33288 /* 69818*/ OPC_SwitchType /*2 cases */, 16, MVT::f32,// ->69837
33290 /* 69822*/ OPC_CheckType, MVT::f32,
33295 MVT::f32, 2/*#Ops*/, 1, 3,
33310 /* 69857*/ OPC_CheckChild3Type, MVT::f32,
33311 /* 69859*/ OPC_CheckType, MVT::f32,
33315 MVT::f32, 2/*#Ops*/, 1, 2,
52894 /*114254*/ OPC_CheckChild2Type, MVT::f32,
52963 /*114358*/ OPC_CheckChild2Type, MVT::f32,
54481 /*117140*/ /*SwitchType*/ 13, MVT::f32,// ->117155
54485 MVT::f32, 3/*#Ops*/, 3, 4, 0,
54523 /*117218*/ OPC_CheckType, MVT::f32,
54526 MVT::f32, 3/*#Ops*/, 1, 3, 0,
54534 /*117238*/ OPC_CheckType, MVT::f32,
54537 MVT::f32, 3/*#Ops*/, 3, 2, 0,
54569 /*117305*/ /*SwitchType*/ 9, MVT::f32,// ->117316
54571 MVT::f32, 3/*#Ops*/, 1, 2, 0,
54638 /*117495*/ /*SwitchType*/ 35, MVT::f32,// ->117532
54647 MVT::f32, 3/*#Ops*/, 1, 2, 7,
60763 /*128582*/ OPC_CheckChild0Type, MVT::f32,
60789 /*128634*/ OPC_CheckType, MVT::f32,
60839 /*128732*/ OPC_CheckChild0Type, MVT::f32,
60865 /*128784*/ OPC_CheckType, MVT::f32,
60915 /*128882*/ OPC_CheckChild0Type, MVT::f32,
60941 /*128934*/ OPC_CheckType, MVT::f32,
60991 /*129032*/ OPC_CheckChild0Type, MVT::f32,
61017 /*129084*/ OPC_CheckType, MVT::f32,
61067 /*129182*/ OPC_CheckChild0Type, MVT::f32,
61093 /*129234*/ OPC_CheckType, MVT::f32,
61143 /*129332*/ OPC_CheckChild0Type, MVT::f32,
61169 /*129384*/ OPC_CheckType, MVT::f32,
61219 /*129482*/ OPC_CheckChild0Type, MVT::f32,
61245 /*129534*/ OPC_CheckType, MVT::f32,
61295 /*129632*/ OPC_CheckChild0Type, MVT::f32,
61321 /*129684*/ OPC_CheckType, MVT::f32,
61371 /*129782*/ OPC_CheckChild0Type, MVT::f32,
61397 /*129834*/ OPC_CheckType, MVT::f32,
61447 /*129932*/ OPC_CheckChild0Type, MVT::f32,
61473 /*129984*/ OPC_CheckType, MVT::f32,
61523 /*130082*/ OPC_CheckChild0Type, MVT::f32,
61549 /*130134*/ OPC_CheckType, MVT::f32,
61599 /*130232*/ OPC_CheckChild0Type, MVT::f32,
61625 /*130284*/ OPC_CheckType, MVT::f32,
61675 /*130382*/ OPC_CheckChild0Type, MVT::f32,
61701 /*130434*/ OPC_CheckType, MVT::f32,
61751 /*130532*/ OPC_CheckChild0Type, MVT::f32,
61777 /*130584*/ OPC_CheckType, MVT::f32,
61827 /*130682*/ OPC_CheckChild0Type, MVT::f32,
61853 /*130734*/ OPC_CheckType, MVT::f32,
61903 /*130832*/ OPC_CheckChild0Type, MVT::f32,
61929 /*130884*/ OPC_CheckType, MVT::f32,
61979 /*130982*/ OPC_CheckChild0Type, MVT::f32,
62005 /*131034*/ OPC_CheckType, MVT::f32,
62055 /*131132*/ OPC_CheckChild0Type, MVT::f32,
62081 /*131184*/ OPC_CheckType, MVT::f32,
62131 /*131282*/ OPC_CheckChild0Type, MVT::f32,
62157 /*131334*/ OPC_CheckType, MVT::f32,
62207 /*131432*/ OPC_CheckChild0Type, MVT::f32,
62233 /*131484*/ OPC_CheckType, MVT::f32,
62283 /*131582*/ OPC_CheckChild0Type, MVT::f32,
62309 /*131634*/ OPC_CheckType, MVT::f32,
62359 /*131732*/ OPC_CheckChild0Type, MVT::f32,
62385 /*131784*/ OPC_CheckType, MVT::f32,
62435 /*131882*/ OPC_CheckChild0Type, MVT::f32,
62461 /*131934*/ OPC_CheckType, MVT::f32,
62511 /*132032*/ OPC_CheckChild0Type, MVT::f32,
62537 /*132084*/ OPC_CheckType, MVT::f32,
62587 /*132182*/ OPC_CheckChild0Type, MVT::f32,
62613 /*132234*/ OPC_CheckType, MVT::f32,
62663 /*132332*/ OPC_CheckChild0Type, MVT::f32,
62689 /*132384*/ OPC_CheckType, MVT::f32,
62739 /*132482*/ OPC_CheckChild0Type, MVT::f32,
62765 /*132534*/ OPC_CheckType, MVT::f32,
62815 /*132632*/ OPC_CheckChild0Type, MVT::f32,
62841 /*132684*/ OPC_CheckType, MVT::f32,
62891 /*132782*/ OPC_CheckChild0Type, MVT::f32,
62917 /*132834*/ OPC_CheckType, MVT::f32,
62967 /*132932*/ OPC_CheckChild0Type, MVT::f32,
62993 /*132984*/ OPC_CheckType, MVT::f32,
63043 /*133082*/ OPC_CheckChild0Type, MVT::f32,
63069 /*133134*/ OPC_CheckType, MVT::f32,
63119 /*133232*/ OPC_CheckChild0Type, MVT::f32,
63145 /*133284*/ OPC_CheckType, MVT::f32,
63195 /*133382*/ OPC_CheckChild0Type, MVT::f32,
63221 /*133434*/ OPC_CheckType, MVT::f32,
63271 /*133532*/ OPC_CheckChild0Type, MVT::f32,
63297 /*133584*/ OPC_CheckType, MVT::f32,
63347 /*133682*/ OPC_CheckChild0Type, MVT::f32,
63373 /*133734*/ OPC_CheckType, MVT::f32,
63423 /*133832*/ OPC_CheckChild0Type, MVT::f32,
63449 /*133884*/ OPC_CheckType, MVT::f32,
63499 /*133982*/ OPC_CheckChild0Type, MVT::f32,
63525 /*134034*/ OPC_CheckType, MVT::f32,
63575 /*134132*/ OPC_CheckChild0Type, MVT::f32,
63601 /*134184*/ OPC_CheckType, MVT::f32,
63651 /*134282*/ OPC_CheckChild0Type, MVT::f32,
63677 /*134334*/ OPC_CheckType, MVT::f32,
63727 /*134432*/ OPC_CheckChild0Type, MVT::f32,
63753 /*134484*/ OPC_CheckType, MVT::f32,
67434 /*142560*/ OPC_CheckChild0Type, MVT::f32,
68873 /*145547*/ /*SwitchType*/ 9, MVT::f32,// ->145558
68874 /*145549*/ OPC_CheckChild0Type, MVT::f32,
68876 MVT::f32, 1/*#Ops*/, 0,
68919 /*145618*/ OPC_CheckChild1Type, MVT::f32,
68965 /*145695*/ /*SwitchType*/ 10, MVT::f32,// ->145707
68966 /*145697*/ OPC_CheckChild1Type, MVT::f32,
68969 MVT::f32, 1/*#Ops*/, 1,
68997 /*145750*/ OPC_CheckChild0Type, MVT::f32,
69026 /*145800*/ OPC_SwitchType /*2 cases */, 7, MVT::f32,// ->145810
69028 MVT::f32, 1/*#Ops*/, 0,
69078 /*145908*/ OPC_CheckChild0Type, MVT::f32,
69198 /*146170*/ OPC_CheckChild0Type, MVT::f32,
69531 /*146918*/ OPC_SwitchType /*2 cases */, 34, MVT::f32,// ->146955
69537 MVT::f32, 3/*#Ops*/, 0, 3, 4,
69545 MVT::f32, 3/*#Ops*/, 0, 3, 4,
69563 /*146980*/ OPC_CheckType, MVT::f32,
69567 MVT::f32, 3/*#Ops*/, 0, 1, 3,
69575 /*147002*/ OPC_CheckType, MVT::f32,
69579 MVT::f32, 3/*#Ops*/, 0, 3, 2,
69587 /*147024*/ OPC_CheckType, MVT::f32,
69591 MVT::f32, 3/*#Ops*/, 0, 1, 3,
69599 /*147046*/ OPC_CheckType, MVT::f32,
69603 MVT::f32, 3/*#Ops*/, 0, 3, 2,
69646 /*147136*/ /*SwitchType*/ 26, MVT::f32,// ->147164
69650 MVT::f32, 3/*#Ops*/, 0, 1, 2,
69656 MVT::f32, 3/*#Ops*/, 0, 1, 2,
69716 /*147267*/ OPC_CheckType, MVT::f32,
69721 MVT::f32, 2/*#Ops*/, 2, 1,
69728 MVT::f32, 2/*#Ops*/, 2, 1,
69735 MVT::f32, 2/*#Ops*/, 2, 1,
69742 MVT::f32, 2/*#Ops*/, 2, 1,
69749 MVT::f32, 2/*#Ops*/, 2, 1,
69755 MVT::f32, 2/*#Ops*/, 2, 1,
69772 /*147371*/ /*SwitchType*/ 78, MVT::f32,// ->147451
69777 MVT::f32, 2/*#Ops*/, 0, 2,
69784 MVT::f32, 2/*#Ops*/, 0, 2,
69791 MVT::f32, 2/*#Ops*/, 0, 2,
69798 MVT::f32, 2/*#Ops*/, 0, 2,
69805 MVT::f32, 2/*#Ops*/, 0, 2,
69811 MVT::f32, 2/*#Ops*/, 0, 2,
69823 /*147464*/ OPC_CheckType, MVT::f32,
69827 MVT::f32, 2/*#Ops*/, 0, 1,
69833 MVT::f32, 2/*#Ops*/, 0, 1,
69839 MVT::f32, 2/*#Ops*/, 0, 1,
69845 MVT::f32, 2/*#Ops*/, 0, 1,
69851 MVT::f32, 2/*#Ops*/, 0, 1,
69856 MVT::f32, 2/*#Ops*/, 0, 1,
69873 /*147554*/ OPC_SwitchType /*2 cases */, 44, MVT::f32,// ->147601
69879 MVT::f32, 2/*#Ops*/, 1, 3,
69887 MVT::f32, 2/*#Ops*/, 1, 3,
69895 MVT::f32, 2/*#Ops*/, 1, 3,
69931 /*147657*/ OPC_CheckType, MVT::f32,
69934 MVT::f32, 2/*#Ops*/, 1, 2,
69939 /*147671*/ OPC_CheckType, MVT::f32,
69942 MVT::f32, 2/*#Ops*/, 1, 2,
69947 /*147685*/ OPC_CheckType, MVT::f32,
69950 MVT::f32, 2/*#Ops*/, 1, 2,
69988 /*147757*/ OPC_SwitchType /*2 cases */, 44, MVT::f32,// ->147804
69994 MVT::f32, 2/*#Ops*/, 1, 3,
70002 MVT::f32, 2/*#Ops*/, 1, 3,
70010 MVT::f32, 2/*#Ops*/, 1, 3,
70046 /*147860*/ OPC_CheckType, MVT::f32,
70049 MVT::f32, 2/*#Ops*/, 1, 2,
70054 /*147874*/ OPC_CheckType, MVT::f32,
70057 MVT::f32, 2/*#Ops*/, 1, 2,
70062 /*147888*/ OPC_CheckType, MVT::f32,
70065 MVT::f32, 2/*#Ops*/, 1, 2,
70120 /*147993*/ /*SwitchType*/ 54, MVT::f32,// ->148049
70125 MVT::f32, 2/*#Ops*/, 0, 2,
70132 MVT::f32, 2/*#Ops*/, 0, 2,
70139 MVT::f32, 2/*#Ops*/, 0, 2,
70146 MVT::f32, 2/*#Ops*/, 0, 2,
70172 /*148088*/ /*SwitchType*/ 54, MVT::f32,// ->148144
70177 MVT::f32, 2/*#Ops*/, 1, 2,
70184 MVT::f32, 2/*#Ops*/, 1, 2,
70191 MVT::f32, 2/*#Ops*/, 1, 2,
70198 MVT::f32, 2/*#Ops*/, 1, 2,
70219 /*148175*/ /*SwitchType*/ 46, MVT::f32,// ->148223
70223 MVT::f32, 2/*#Ops*/, 0, 1,
70229 MVT::f32, 2/*#Ops*/, 0, 1,
70235 MVT::f32, 2/*#Ops*/, 0, 1,
70241 MVT::f32, 2/*#Ops*/, 0, 1,
70322 /*148365*/ /*SwitchType*/ 54, MVT::f32,// ->148421
70327 MVT::f32, 2/*#Ops*/, 0, 2,
70334 MVT::f32, 2/*#Ops*/, 0, 2,
70341 MVT::f32, 2/*#Ops*/, 0, 2,
70348 MVT::f32, 2/*#Ops*/, 0, 2,
70369 /*148450*/ OPC_CheckType, MVT::f32,
70373 MVT::f32, 2/*#Ops*/, 0, 1,
70379 MVT::f32, 2/*#Ops*/, 0, 1,
70385 MVT::f32, 2/*#Ops*/, 0, 1,
70391 MVT::f32, 2/*#Ops*/, 0, 1,
70473 /*148641*/ /*SwitchType*/ 54, MVT::f32,// ->148697
70478 MVT::f32, 2/*#Ops*/, 0, 2,
70485 MVT::f32, 2/*#Ops*/, 0, 2,
70492 MVT::f32, 2/*#Ops*/, 0, 2,
70499 MVT::f32, 2/*#Ops*/, 0, 2,
70525 /*148736*/ /*SwitchType*/ 54, MVT::f32,// ->148792
70530 MVT::f32, 2/*#Ops*/, 1, 2,
70537 MVT::f32, 2/*#Ops*/, 1, 2,
70544 MVT::f32, 2/*#Ops*/, 1, 2,
70551 MVT::f32, 2/*#Ops*/, 1, 2,
70572 /*148823*/ /*SwitchType*/ 46, MVT::f32,// ->148871
70576 MVT::f32, 2/*#Ops*/, 0, 1,
70582 MVT::f32, 2/*#Ops*/, 0, 1,
70588 MVT::f32, 2/*#Ops*/, 0, 1,
70594 MVT::f32, 2/*#Ops*/, 0, 1,
70665 /*148995*/ /*SwitchType*/ 26, MVT::f32,// ->149023
70670 MVT::f32, 2/*#Ops*/, 0, 2,
70676 MVT::f32, 2/*#Ops*/, 0, 2,
70692 /*149044*/ /*SwitchType*/ 26, MVT::f32,// ->149072
70697 MVT::f32, 2/*#Ops*/, 1, 2,
70703 MVT::f32, 2/*#Ops*/, 1, 2,
70715 /*149086*/ /*SwitchType*/ 22, MVT::f32,// ->149110
70719 MVT::f32, 2/*#Ops*/, 0, 1,
70724 MVT::f32, 2/*#Ops*/, 0, 1,
70743 /*149138*/ /*SwitchType*/ 26, MVT::f32,// ->149166
70748 MVT::f32, 2/*#Ops*/, 0, 2,
70754 MVT::f32, 2/*#Ops*/, 0, 2,
70770 /*149187*/ /*SwitchType*/ 26, MVT::f32,// ->149215
70775 MVT::f32, 2/*#Ops*/, 1, 2,
70781 MVT::f32, 2/*#Ops*/, 1, 2,
70793 /*149229*/ /*SwitchType*/ 22, MVT::f32,// ->149253
70797 MVT::f32, 2/*#Ops*/, 0, 1,
70802 MVT::f32, 2/*#Ops*/, 0, 1,
70815 /*149269*/ OPC_SwitchType /*2 cases */, 84, MVT::f32,// ->149356
70820 MVT::f32, 2/*#Ops*/, 0, 2, // Results = #3
70823 MVT::f32, 2/*#Ops*/, 3, 4, // Results = #5
70826 MVT::f32, 2/*#Ops*/, 5, 6, // Results = #7
70828 MVT::f32, 2/*#Ops*/, 0, 7,
70834 MVT::f32, 2/*#Ops*/, 0, 2, // Results = #3
70837 MVT::f32, 2/*#Ops*/, 3, 4, // Results = #5
70840 MVT::f32, 2/*#Ops*/, 5, 6, // Results = #7
70842 MVT::f32, 2/*#Ops*/, 0, 7,
70862 /*149399*/ OPC_CheckType, MVT::f32,
70866 MVT::f32, 2/*#Ops*/, 0, 1, // Results = #2
70869 MVT::f32, 2/*#Ops*/, 2, 3, // Results = #4
70871 MVT::f32, 2/*#Ops*/, 4, 1, // Results = #5
70873 MVT::f32, 2/*#Ops*/, 0, 5,
70878 MVT::f32, 2/*#Ops*/, 0, 1, // Results = #2
70881 MVT::f32, 2/*#Ops*/, 2, 3, // Results = #4
70883 MVT::f32, 2/*#Ops*/, 4, 1, // Results = #5
70885 MVT::f32, 2/*#Ops*/, 0, 5,
70910 /*149530*/ /*SwitchType*/ 20, MVT::f32,// ->149552
70914 MVT::f32, 1/*#Ops*/, 0,
70919 MVT::f32, 1/*#Ops*/, 0,
70931 /*149567*/ /*SwitchType*/ 20, MVT::f32,// ->149589
70935 MVT::f32, 1/*#Ops*/, 0,
70940 MVT::f32, 1/*#Ops*/, 0,
70952 /*149604*/ /*SwitchType*/ 20, MVT::f32,// ->149626
70956 MVT::f32, 1/*#Ops*/, 0,
70961 MVT::f32, 1/*#Ops*/, 0,
70968 /*149631*/ OPC_CheckType, MVT::f32,
70971 MVT::f32, 1/*#Ops*/, 0,
70976 /*149646*/ OPC_CheckType, MVT::f32,
70979 MVT::f32, 1/*#Ops*/, 0,
70984 /*149661*/ OPC_SwitchType /*2 cases */, 9, MVT::f32,// ->149673
70987 MVT::f32, 1/*#Ops*/, 1,
71007 /*149708*/ /*SwitchType*/ 11, MVT::f32,// ->149721
71010 MVT::f32, 2/*#Ops*/, 0, 1,
71028 /*149752*/ /*SwitchType*/ 11, MVT::f32,// ->149765
71031 MVT::f32, 2/*#Ops*/, 0, 1,
71049 /*149796*/ /*SwitchType*/ 11, MVT::f32,// ->149809
71052 MVT::f32, 2/*#Ops*/, 0, 1,
71074 /*149855*/ /*SwitchType*/ 26, MVT::f32,// ->149883
71081 MVT::f32, 2/*#Ops*/, 3, 4,
71106 /*149936*/ /*SwitchType*/ 11, MVT::f32,// ->149949
71109 MVT::f32, 2/*#Ops*/, 0, 1,
71127 /*149980*/ /*SwitchType*/ 11, MVT::f32,// ->149993
71130 MVT::f32, 2/*#Ops*/, 0, 1,
71148 /*150024*/ /*SwitchType*/ 11, MVT::f32,// ->150037
71151 MVT::f32, 2/*#Ops*/, 0, 1,
71173 /*150083*/ /*SwitchType*/ 26, MVT::f32,// ->150111
71180 MVT::f32, 2/*#Ops*/, 3, 4,
71199 /*150150*/ OPC_CheckChild0Type, MVT::f32,
71213 /*150178*/ /*SwitchType*/ 28, MVT::f32,// ->150208
71218 MVT::f32, 2/*#Ops*/, 0, 1,
71224 MVT::f32, 2/*#Ops*/, 0, 1,
71231 /*150213*/ OPC_SwitchType /*2 cases */, 28, MVT::f32,// ->150244
71236 MVT::f32, 2/*#Ops*/, 0, 1,
71242 MVT::f32, 2/*#Ops*/, 0, 1,
71255 /*150262*/ OPC_CheckChild0Type, MVT::f32,
71280 /*150312*/ /*SwitchType*/ 30, MVT::f32,// ->150344
71285 MVT::f32, 2/*#Ops*/, 0, 1,
71292 MVT::f32, 2/*#Ops*/, 0, 1,
71311 /*150376*/ /*SwitchType*/ 30, MVT::f32,// ->150408
71316 MVT::f32, 2/*#Ops*/, 0, 1,
71323 MVT::f32, 2/*#Ops*/, 0, 1,
71342 /*150440*/ /*SwitchType*/ 30, MVT::f32,// ->150472
71347 MVT::f32, 2/*#Ops*/, 0, 1,
71354 MVT::f32, 2/*#Ops*/, 0, 1,
71373 /*150504*/ /*SwitchType*/ 30, MVT::f32,// ->150536
71378 MVT::f32, 2/*#Ops*/, 0, 1,
71385 MVT::f32, 2/*#Ops*/, 0, 1,
71404 /*150568*/ /*SwitchType*/ 30, MVT::f32,// ->150600
71409 MVT::f32, 2/*#Ops*/, 0, 1,
71416 MVT::f32, 2/*#Ops*/, 0, 1,
gen/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc 815 /* 10 */ MVT::f32, MVT::Other,
gen/lib/Target/PowerPC/PPCGenCallingConv.inc 186 if (LocVT == MVT::f32 ||
206 if (LocVT == MVT::f32) {
232 if (LocVT == MVT::f32 ||
241 if (LocVT == MVT::f32) {
368 if (LocVT == MVT::f32 ||
448 if (LocVT == MVT::f32) {
472 if (LocVT == MVT::f32) {
618 if (LocVT == MVT::f32) {
736 if (LocVT == MVT::f32) {
gen/lib/Target/PowerPC/PPCGenDAGISel.inc 416 /* 850*/ /*SwitchType*/ 72, MVT::f32,// ->924
725 /* 1610*/ /*SwitchType*/ 84, MVT::f32,// ->1696
869 /* 1961*/ /*SwitchType*/ 72, MVT::f32,// ->2035
995 /* 2268*/ /*SwitchType*/ 84, MVT::f32,// ->2354
1750 /* 4013*/ OPC_CheckChild1Type, MVT::f32,
5600 /* 12980*/ OPC_CheckChild0Type, MVT::f32,
9255 /* 22746*/ OPC_CheckChild0Type, MVT::f32,
11915 /* 30408*/ OPC_CheckChild0Type, MVT::f32,
15887 /* 42383*/ OPC_CheckType, MVT::f32,
15893 MVT::f32, 1/*#Ops*/, 0,
15902 MVT::f32, 1/*#Ops*/, 2,
15911 MVT::f32, 1/*#Ops*/, 0,
15920 MVT::f32, 1/*#Ops*/, 2,
15932 MVT::f32, 1/*#Ops*/, 2,
15941 MVT::f32, 1/*#Ops*/, 2,
15953 MVT::f32, 1/*#Ops*/, 2,
15962 MVT::f32, 1/*#Ops*/, 2,
15981 MVT::f32, 1/*#Ops*/, 7,
16001 MVT::f32, 1/*#Ops*/, 10,
16018 /* 42698*/ OPC_CheckType, MVT::f32,
16022 MVT::f32, 2/*#Ops*/, 0, 1,
16038 /* 42745*/ /*SwitchType*/ 24, MVT::f32,// ->42771
16045 MVT::f32, 2/*#Ops*/, 2, 3,
16062 /* 42804*/ /*SwitchType*/ 24, MVT::f32,// ->42830
16069 MVT::f32, 2/*#Ops*/, 2, 3,
16086 /* 42863*/ /*SwitchType*/ 24, MVT::f32,// ->42889
16093 MVT::f32, 2/*#Ops*/, 2, 3,
16119 /* 42946*/ OPC_CheckType, MVT::f32,
16131 MVT::f32, 2/*#Ops*/, 6, 7,
18635 /* 47469*/ OPC_CheckChild0Type, MVT::f32,
18658 /* 47530*/ /*SwitchType*/ 109, MVT::f32,// ->47641
18689 MVT::f32, 1/*#Ops*/, 16,
19127 /* 48427*/ OPC_CheckChild0Type, MVT::f32,
19191 /* 48552*/ OPC_CheckChild0Type, MVT::f32,
19772 /* 50038*/ OPC_CheckChild0Type, MVT::f32,
21575 /* 53847*/ /*SwitchType*/ 32, MVT::f32,// ->53881
21581 MVT::f32, 2/*#Ops*/, 2, 3,
21589 MVT::f32, 2/*#Ops*/, 2, 3,
21647 MVT::f32, 2/*#Ops*/, 2, 3, // Results = #4
21658 MVT::f32, 2/*#Ops*/, 2, 3, // Results = #4
21667 /* 54041*/ OPC_SwitchType /*2 cases */, 64, MVT::f32,// ->54108
21674 MVT::f32, 2/*#Ops*/, 2, 3,
21681 MVT::f32, 2/*#Ops*/, 2, 3,
21691 MVT::f32, 2/*#Ops*/, 2, 3,
21698 MVT::f32, 2/*#Ops*/, 2, 3,
21750 MVT::f32, 2/*#Ops*/, 2, 3, // Results = #4
21760 MVT::f32, 2/*#Ops*/, 2, 3, // Results = #4
25970 /* 62692*/ OPC_CheckChild0Type, MVT::f32,
28641 /* 68780*/ /*SwitchType*/ 38, MVT::f32,// ->68820
28645 MVT::f32, 3/*#Ops*/, 0, 1, 2,
28651 MVT::f32, 3/*#Ops*/, 0, 1, 2,
28657 MVT::f32, 3/*#Ops*/, 0, 1, 2,
29177 /* 70083*/ OPC_CheckType, MVT::f32,
29182 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29188 /* 70108*/ OPC_CheckType, MVT::f32,
29193 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29199 /* 70133*/ OPC_CheckType, MVT::f32,
29204 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29210 /* 70158*/ OPC_CheckType, MVT::f32,
29215 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29221 /* 70183*/ OPC_CheckType, MVT::f32,
29226 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29232 /* 70208*/ OPC_CheckType, MVT::f32,
29237 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29243 /* 70233*/ OPC_CheckType, MVT::f32,
29248 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29254 /* 70258*/ OPC_CheckType, MVT::f32,
29259 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29265 /* 70283*/ OPC_CheckType, MVT::f32,
29270 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29276 /* 70308*/ OPC_CheckType, MVT::f32,
29281 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29287 /* 70333*/ OPC_CheckType, MVT::f32,
29292 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29298 /* 70358*/ OPC_CheckType, MVT::f32,
29303 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29309 /* 70383*/ OPC_CheckType, MVT::f32,
29314 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29320 /* 70408*/ OPC_CheckType, MVT::f32,
29325 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29331 /* 70433*/ OPC_CheckType, MVT::f32,
29336 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29342 /* 70458*/ OPC_CheckType, MVT::f32,
29347 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29353 /* 70483*/ OPC_CheckType, MVT::f32,
29358 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29364 /* 70508*/ OPC_CheckType, MVT::f32,
29369 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29375 /* 70533*/ OPC_CheckType, MVT::f32,
29380 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29386 /* 70558*/ OPC_CheckType, MVT::f32,
29391 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29507 /* 70833*/ OPC_CheckType, MVT::f32,
29512 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29518 /* 70858*/ OPC_CheckType, MVT::f32,
29523 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29529 /* 70883*/ OPC_CheckType, MVT::f32,
29534 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29540 /* 70908*/ OPC_CheckType, MVT::f32,
29545 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29551 /* 70933*/ OPC_CheckType, MVT::f32,
29556 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29562 /* 70958*/ OPC_CheckType, MVT::f32,
29567 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29573 /* 70983*/ OPC_CheckType, MVT::f32,
29578 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29584 /* 71008*/ OPC_CheckType, MVT::f32,
29589 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29595 /* 71033*/ OPC_CheckType, MVT::f32,
29600 MVT::f32, 3/*#Ops*/, 4, 2, 3,
29606 /* 71058*/ OPC_CheckType, MVT::f32,
29611 MVT::f32, 3/*#Ops*/, 4, 2, 3,
34559 /* 89170*/ /*SwitchType*/ 9, MVT::f32,// ->89181
34562 MVT::f32, 1/*#Ops*/, 0,
34625 /* 89286*/ OPC_CheckType, MVT::f32,
34631 MVT::f32, 2/*#Ops*/, 2, 3,
34639 MVT::f32, 2/*#Ops*/, 2, 3,
34651 /* 89334*/ /*SwitchType*/ 46, MVT::f32,// ->89382
34658 MVT::f32, 1/*#Ops*/, 1,
34666 MVT::f32, 1/*#Ops*/, 0,
34672 MVT::f32, 1/*#Ops*/, 0,
35901 /* 92337*/ /*SwitchType*/ 9, MVT::f32,// ->92348
35904 MVT::f32, 1/*#Ops*/, 0,
35975 /* 92470*/ /*SwitchType*/ 11, MVT::f32,// ->92483
35978 MVT::f32, 3/*#Ops*/, 2, 0, 1,
35997 /* 92514*/ /*SwitchType*/ 11, MVT::f32,// ->92527
36000 MVT::f32, 3/*#Ops*/, 2, 0, 1,
36060 /* 92630*/ /*SwitchType*/ 11, MVT::f32,// ->92643
36063 MVT::f32, 3/*#Ops*/, 0, 1, 2,
36076 /* 92661*/ /*SwitchType*/ 11, MVT::f32,// ->92674
36079 MVT::f32, 3/*#Ops*/, 0, 1, 2,
36087 /* 92681*/ OPC_SwitchType /*2 cases */, 22, MVT::f32,// ->92706
36091 MVT::f32, 1/*#Ops*/, 0,
36097 MVT::f32, 1/*#Ops*/, 0,
36119 /* 92734*/ OPC_SwitchType /*2 cases */, 22, MVT::f32,// ->92759
36123 MVT::f32, 1/*#Ops*/, 0,
36129 MVT::f32, 1/*#Ops*/, 0,
36709 /* 93984*/ OPC_CheckType, MVT::f32,
36716 MVT::f32, 1/*#Ops*/, 2,
36728 MVT::f32, 1/*#Ops*/, 4,
36737 /* 94049*/ OPC_CheckType, MVT::f32,
36747 MVT::f32, 1/*#Ops*/, 4,
36759 MVT::f32, 1/*#Ops*/, 4,
36770 /* 94130*/ OPC_CheckType, MVT::f32,
36779 MVT::f32, 1/*#Ops*/, 3,
36790 MVT::f32, 1/*#Ops*/, 3,
36799 /* 94197*/ OPC_CheckType, MVT::f32,
36808 MVT::f32, 1/*#Ops*/, 3,
36819 MVT::f32, 1/*#Ops*/, 3,
36828 /* 94264*/ OPC_CheckType, MVT::f32,
36837 MVT::f32, 1/*#Ops*/, 3,
36848 MVT::f32, 1/*#Ops*/, 3,
36857 /* 94331*/ OPC_CheckType, MVT::f32,
36866 MVT::f32, 1/*#Ops*/, 3,
36877 MVT::f32, 1/*#Ops*/, 3,
36886 /* 94397*/ OPC_CheckType, MVT::f32,
36890 MVT::f32, 1/*#Ops*/, 0,
36895 MVT::f32, 1/*#Ops*/, 0,
36914 /* 94450*/ OPC_CheckType, MVT::f32,
36921 MVT::f32, 1/*#Ops*/, 2,
36933 MVT::f32, 1/*#Ops*/, 4,
36942 /* 94515*/ OPC_CheckType, MVT::f32,
36952 MVT::f32, 1/*#Ops*/, 4,
36964 MVT::f32, 1/*#Ops*/, 4,
36979 /* 94604*/ OPC_CheckType, MVT::f32,
36986 MVT::f32, 1/*#Ops*/, 2,
36995 MVT::f32, 1/*#Ops*/, 2,
37004 /* 94657*/ OPC_CheckType, MVT::f32,
37011 MVT::f32, 1/*#Ops*/, 2,
37020 MVT::f32, 1/*#Ops*/, 2,
37029 /* 94710*/ OPC_CheckType, MVT::f32,
37036 MVT::f32, 1/*#Ops*/, 2,
37045 MVT::f32, 1/*#Ops*/, 2,
37054 /* 94763*/ OPC_CheckType, MVT::f32,
37061 MVT::f32, 1/*#Ops*/, 2,
37070 MVT::f32, 1/*#Ops*/, 2,
37079 /* 94815*/ OPC_CheckType, MVT::f32,
37083 MVT::f32, 1/*#Ops*/, 0,
37088 MVT::f32, 1/*#Ops*/, 0,
37152 /* 94947*/ /*SwitchType*/ 43, MVT::f32,// ->94992
37164 MVT::f32, 2/*#Ops*/, 6, 7,
37195 /* 95036*/ OPC_CheckType, MVT::f32,
37207 MVT::f32, 2/*#Ops*/, 6, 7,
37217 /* 95091*/ OPC_CheckType, MVT::f32,
37229 MVT::f32, 2/*#Ops*/, 6, 7,
37240 /* 95151*/ /*SwitchType*/ 43, MVT::f32,// ->95196
37252 MVT::f32, 2/*#Ops*/, 6, 7,
37275 /* 95232*/ /*SwitchType*/ 43, MVT::f32,// ->95277
37287 MVT::f32, 2/*#Ops*/, 6, 7,
37318 /* 95321*/ OPC_CheckType, MVT::f32,
37330 MVT::f32, 2/*#Ops*/, 6, 7,
37340 /* 95376*/ OPC_CheckType, MVT::f32,
37352 MVT::f32, 2/*#Ops*/, 6, 7,
37363 /* 95436*/ /*SwitchType*/ 43, MVT::f32,// ->95481
37375 MVT::f32, 2/*#Ops*/, 6, 7,
37451 /* 95617*/ OPC_CheckType, MVT::f32,
37454 MVT::f32, 3/*#Ops*/, 2, 0, 1,
37465 /* 95640*/ OPC_CheckType, MVT::f32,
37468 MVT::f32, 3/*#Ops*/, 2, 0, 1,
37479 /* 95664*/ OPC_CheckType, MVT::f32,
37482 MVT::f32, 3/*#Ops*/, 2, 0, 1,
37535 /* 95764*/ /*SwitchType*/ 11, MVT::f32,// ->95777
37538 MVT::f32, 3/*#Ops*/, 2, 0, 1,
37559 /* 95812*/ /*SwitchType*/ 11, MVT::f32,// ->95825
37562 MVT::f32, 3/*#Ops*/, 0, 1, 2,
37601 /* 95881*/ OPC_CheckType, MVT::f32,
37604 MVT::f32, 3/*#Ops*/, 0, 1, 2,
37615 /* 95905*/ OPC_CheckType, MVT::f32,
37618 MVT::f32, 3/*#Ops*/, 0, 1, 2,
37631 /* 95937*/ /*SwitchType*/ 11, MVT::f32,// ->95950
37634 MVT::f32, 3/*#Ops*/, 0, 1, 2,
37835 /* 96302*/ /*SwitchType*/ 8, MVT::f32,// ->96312
37838 MVT::f32, 0/*#Ops*/,
37865 /* 96357*/ /*SwitchType*/ 35, MVT::f32,// ->96394
37869 MVT::f32, 2/*#Ops*/, 0, 1,
37875 MVT::f32, 2/*#Ops*/, 0, 1,
37881 MVT::f32, 2/*#Ops*/, 0, 1,
37947 /* 96512*/ /*SwitchType*/ 35, MVT::f32,// ->96549
37951 MVT::f32, 2/*#Ops*/, 0, 1,
37957 MVT::f32, 2/*#Ops*/, 0, 1,
37963 MVT::f32, 2/*#Ops*/, 0, 1,
38035 /* 96688*/ /*SwitchType*/ 35, MVT::f32,// ->96725
38039 MVT::f32, 2/*#Ops*/, 0, 1,
38045 MVT::f32, 2/*#Ops*/, 0, 1,
38051 MVT::f32, 2/*#Ops*/, 0, 1,
38117 /* 96842*/ /*SwitchType*/ 35, MVT::f32,// ->96879
38121 MVT::f32, 2/*#Ops*/, 0, 1,
38127 MVT::f32, 2/*#Ops*/, 0, 1,
38133 MVT::f32, 2/*#Ops*/, 0, 1,
38172 /* 96945*/ /*SwitchType*/ 22, MVT::f32,// ->96969
38176 MVT::f32, 1/*#Ops*/, 0,
38182 MVT::f32, 1/*#Ops*/, 0,
38221 /* 97032*/ /*SwitchType*/ 22, MVT::f32,// ->97056
38225 MVT::f32, 1/*#Ops*/, 0,
38231 MVT::f32, 1/*#Ops*/, 0,
38284 /* 97142*/ /*SwitchType*/ 22, MVT::f32,// ->97166
38288 MVT::f32, 1/*#Ops*/, 0,
38294 MVT::f32, 1/*#Ops*/, 0,
38359 /* 97273*/ /*SwitchType*/ 22, MVT::f32,// ->97297
38363 MVT::f32, 1/*#Ops*/, 0,
38369 MVT::f32, 1/*#Ops*/, 0,
38419 /* 97381*/ /*SwitchType*/ 21, MVT::f32,// ->97404
38423 MVT::f32, 2/*#Ops*/, 1, 2, // Results = #3
38425 MVT::f32, 2/*#Ops*/, 3, 0,
38438 /* 97421*/ OPC_CheckChild1Type, MVT::f32,
38439 /* 97423*/ OPC_SwitchType /*2 cases */, 10, MVT::f32,// ->97436
38442 MVT::f32, 2/*#Ops*/, 1, 0,
38523 /* 97597*/ /*SwitchType*/ 9, MVT::f32,// ->97608
38526 MVT::f32, 1/*#Ops*/, 0,
38546 /* 97638*/ /*SwitchType*/ 9, MVT::f32,// ->97649
38549 MVT::f32, 1/*#Ops*/, 0,
38568 /* 97677*/ /*SwitchType*/ 9, MVT::f32,// ->97688
38571 MVT::f32, 1/*#Ops*/, 0,
38590 /* 97716*/ /*SwitchType*/ 9, MVT::f32,// ->97727
38593 MVT::f32, 1/*#Ops*/, 0,
38621 /* 97776*/ /*SwitchType*/ 9, MVT::f32,// ->97787
38624 MVT::f32, 1/*#Ops*/, 0,
38715 /* 97953*/ /*SwitchType*/ 9, MVT::f32,// ->97964
38718 MVT::f32, 1/*#Ops*/, 0,
38778 /* 98069*/ /*SwitchType*/ 9, MVT::f32,// ->98080
38781 MVT::f32, 1/*#Ops*/, 0,
38841 /* 98185*/ /*SwitchType*/ 9, MVT::f32,// ->98196
38844 MVT::f32, 1/*#Ops*/, 0,
38921 /* 98331*/ OPC_CheckChild0Type, MVT::f32,
39006 /* 98514*/ /*SwitchType*/ 43, MVT::f32,// ->98559
39018 MVT::f32, 2/*#Ops*/, 6, 7,
39031 /* 98578*/ /*SwitchType*/ 43, MVT::f32,// ->98623
39043 MVT::f32, 2/*#Ops*/, 6, 7,
39087 /* 98710*/ /*SwitchType*/ 11, MVT::f32,// ->98723
39090 MVT::f32, 3/*#Ops*/, 0, 1, 2,
39630 MVT::f32, 1/*#Ops*/, 0, // Results = #1
39663 MVT::f32, 1/*#Ops*/, 0, // Results = #1
40535 /*101908*/ OPC_CheckType, MVT::f32,
40549 /*101933*/ OPC_CheckType, MVT::f32,
40564 /*101959*/ OPC_CheckType, MVT::f32,
40578 /*101984*/ OPC_CheckType, MVT::f32,
40634 /*102140*/ OPC_CheckType, MVT::f32,
40648 /*102165*/ OPC_CheckType, MVT::f32,
40663 /*102191*/ OPC_CheckType, MVT::f32,
40677 /*102216*/ OPC_CheckType, MVT::f32,
40792 /*102517*/ OPC_CheckChild0Type, MVT::f32,
40807 /*102550*/ OPC_CheckChild1Type, MVT::f32,
40809 /*102553*/ OPC_CheckChild2Type, MVT::f32,
40811 /*102556*/ OPC_CheckChild3Type, MVT::f32,
40947 MVT::f32, 2/*#Ops*/, 2, 3, // Results = #4
40963 MVT::f32, 2/*#Ops*/, 2, 3, // Results = #4
41015 MVT::f32, 2/*#Ops*/, 2, 3, // Results = #4
41031 MVT::f32, 2/*#Ops*/, 2, 3, // Results = #4
41106 MVT::f32, 2/*#Ops*/, 2, 3, // Results = #4
41108 MVT::f32, 1/*#Ops*/, 4, // Results = #5
41203 MVT::f32, 2/*#Ops*/, 2, 3, // Results = #4
41205 MVT::f32, 1/*#Ops*/, 4, // Results = #5
41866 /*105184*/ /*SwitchType*/ 79, MVT::f32,// ->105265
41939 /*105365*/ OPC_CheckChild0Type, MVT::f32,
44400 if (cast<MemSDNode>(N)->getMemoryVT() != MVT::f32) return false;
gen/lib/Target/PowerPC/PPCGenFastISel.inc 312 if (RetVT.SimpleTy != MVT::f32)
379 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
392 if (RetVT.SimpleTy != MVT::f32)
447 case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0, Op0IsKill);
459 if (RetVT.SimpleTy != MVT::f32)
514 case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
567 if (RetVT.SimpleTy != MVT::f32)
634 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
666 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill);
675 if (RetVT.SimpleTy != MVT::f32)
746 case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
797 case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
808 if (RetVT.SimpleTy != MVT::f32)
860 case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
872 if (RetVT.SimpleTy != MVT::f32)
924 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
936 if (RetVT.SimpleTy != MVT::f32)
991 case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0, Op0IsKill);
1023 case MVT::f32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
1061 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill);
1137 case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill);
1194 if (RetVT.SimpleTy != MVT::f32)
1230 if (RetVT.SimpleTy != MVT::f32)
1248 if (RetVT.SimpleTy != MVT::f32)
1267 case MVT::f32: return fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
1276 if (RetVT.SimpleTy != MVT::f32)
1295 case MVT::f32: return fastEmit_PPCISD_FCTIDZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
1304 if (RetVT.SimpleTy != MVT::f32)
1323 case MVT::f32: return fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
1332 if (RetVT.SimpleTy != MVT::f32)
1354 case MVT::f32: return fastEmit_PPCISD_FCTIWZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
1363 if (RetVT.SimpleTy != MVT::f32)
1421 case MVT::f32: return fastEmit_PPCISD_FRE_MVT_f32_r(RetVT, Op0, Op0IsKill);
1433 if (RetVT.SimpleTy != MVT::f32)
1491 case MVT::f32: return fastEmit_PPCISD_FRSQRTE_MVT_f32_r(RetVT, Op0, Op0IsKill);
1922 if (RetVT.SimpleTy != MVT::f32)
1995 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2008 if (RetVT.SimpleTy != MVT::f32)
2066 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2170 if (RetVT.SimpleTy != MVT::f32)
2240 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2253 if (RetVT.SimpleTy != MVT::f32)
2326 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/PowerPC/PPCGenRegisterInfo.inc 3923 /* 6 */ MVT::i32, MVT::f32, MVT::Other,
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 2431 /* 4473*/ OPC_SwitchType /*2 cases */, 36, MVT::f32,// ->4512
2438 MVT::f32, 2/*#Ops*/, 3, 4,
2447 MVT::f32, 2/*#Ops*/, 3, 4,
2476 /* 4558*/ OPC_SwitchType /*2 cases */, 16, MVT::f32,// ->4577
2482 MVT::f32, 2/*#Ops*/, 3, 4,
2507 /* 4619*/ OPC_SwitchType /*2 cases */, 64, MVT::f32,// ->4686
2514 MVT::f32, 2/*#Ops*/, 3, 4,
2523 MVT::f32, 2/*#Ops*/, 3, 4,
2531 MVT::f32, 2/*#Ops*/, 1, 3,
2539 MVT::f32, 2/*#Ops*/, 1, 3,
2584 /* 4760*/ OPC_SwitchType /*2 cases */, 31, MVT::f32,// ->4794
2591 MVT::f32, 2/*#Ops*/, 3, 4,
2598 MVT::f32, 2/*#Ops*/, 1, 3,
2627 /* 4837*/ OPC_SwitchType /*2 cases */, 108, MVT::f32,// ->4948
2634 MVT::f32, 2/*#Ops*/, 2, 3,
2643 MVT::f32, 2/*#Ops*/, 2, 3,
2652 MVT::f32, 2/*#Ops*/, 2, 3,
2662 MVT::f32, 2/*#Ops*/, 1, 2,
2670 MVT::f32, 2/*#Ops*/, 1, 2,
2680 MVT::f32, 2/*#Ops*/, 1, 2,
3595 /* 6640*/ OPC_CheckChild1Type, MVT::f32,
5491 /* 10148*/ OPC_CheckChild0Type, MVT::f32,
7161 /* 13329*/ OPC_CheckChild0Type, MVT::f32,
8257 /* 15363*/ /*SwitchType*/ 34, MVT::f32,// ->15399
8262 MVT::f32, 5/*#Ops*/, 0, 1, 5, 3, 4,
8269 MVT::f32, 5/*#Ops*/, 0, 1, 5, 3, 4,
8307 /* 15468*/ /*SwitchType*/ 15, MVT::f32,// ->15485
8311 MVT::f32, 5/*#Ops*/, 0, 1, 5, 3, 4,
12350 /* 22988*/ OPC_CheckChild0Type, MVT::f32,
12397 /* 23070*/ OPC_SwitchType /*2 cases */, 22, MVT::f32,// ->23095
12401 MVT::f32, 1/*#Ops*/, 0,
12407 MVT::f32, 1/*#Ops*/, 0,
12428 /* 23123*/ OPC_SwitchType /*2 cases */, 9, MVT::f32,// ->23135
12431 MVT::f32, 1/*#Ops*/, 0,
12445 /* 23155*/ OPC_CheckChild0Type, MVT::f32,
12560 /* 23384*/ OPC_CheckChild0Type, MVT::f32,
12702 /* 23668*/ OPC_SwitchType /*2 cases */, 30, MVT::f32,// ->23701
12707 MVT::f32, 2/*#Ops*/, 0, 1,
12714 MVT::f32, 2/*#Ops*/, 0, 1,
12735 /* 23729*/ OPC_SwitchType /*2 cases */, 13, MVT::f32,// ->23745
12739 MVT::f32, 2/*#Ops*/, 0, 1,
12756 /* 23769*/ OPC_SwitchType /*2 cases */, 30, MVT::f32,// ->23802
12761 MVT::f32, 2/*#Ops*/, 0, 1,
12768 MVT::f32, 2/*#Ops*/, 0, 1,
12789 /* 23830*/ OPC_SwitchType /*2 cases */, 13, MVT::f32,// ->23846
12793 MVT::f32, 2/*#Ops*/, 0, 1,
12809 /* 23868*/ OPC_SwitchType /*2 cases */, 86, MVT::f32,// ->23957
12814 MVT::f32, 2/*#Ops*/, 0, 1,
12821 MVT::f32, 2/*#Ops*/, 0, 1,
12828 MVT::f32, 2/*#Ops*/, 0, 1,
12835 MVT::f32, 2/*#Ops*/, 0, 1,
12842 MVT::f32, 2/*#Ops*/, 0, 1,
12849 MVT::f32, 2/*#Ops*/, 0, 1,
12884 /* 24013*/ OPC_SwitchType /*2 cases */, 30, MVT::f32,// ->24046
12889 MVT::f32, 2/*#Ops*/, 0, 1,
12896 MVT::f32, 2/*#Ops*/, 0, 1,
12929 /* 24096*/ OPC_SwitchType /*2 cases */, 50, MVT::f32,// ->24149
12934 MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
12941 MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
12948 MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
12983 /* 24211*/ OPC_CheckType, MVT::f32,
12988 MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
12995 MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
13002 MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
13013 /* 24272*/ OPC_CheckType, MVT::f32,
13018 MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
13025 MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
13032 MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
13100 /* 24450*/ OPC_SwitchType /*2 cases */, 50, MVT::f32,// ->24503
13105 MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
13112 MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
13119 MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
13154 /* 24568*/ OPC_SwitchType /*2 cases */, 13, MVT::f32,// ->24584
13156 /* 24572*/ OPC_CheckType, MVT::f32,
13159 MVT::f32, 2/*#Ops*/, 0, 1,
13173 /* 24602*/ OPC_SwitchType /*2 cases */, 12, MVT::f32,// ->24617
13174 /* 24605*/ OPC_CheckChild1Type, MVT::f32,
13177 MVT::f32, 2/*#Ops*/, 0, 1,
13198 /* 24649*/ OPC_SwitchType /*2 cases */, 13, MVT::f32,// ->24665
13202 MVT::f32, 2/*#Ops*/, 0, 1,
13216 /* 24685*/ OPC_SwitchType /*2 cases */, 86, MVT::f32,// ->24774
13221 MVT::f32, 2/*#Ops*/, 0, 1,
13228 MVT::f32, 2/*#Ops*/, 0, 1,
13235 MVT::f32, 2/*#Ops*/, 0, 1,
13242 MVT::f32, 2/*#Ops*/, 0, 1,
13249 MVT::f32, 2/*#Ops*/, 0, 1,
13256 MVT::f32, 2/*#Ops*/, 0, 1,
13291 /* 24830*/ OPC_SwitchType /*2 cases */, 30, MVT::f32,// ->24863
13296 MVT::f32, 2/*#Ops*/, 0, 1,
13303 MVT::f32, 2/*#Ops*/, 0, 1,
13327 /* 24898*/ OPC_SwitchType /*2 cases */, 10, MVT::f32,// ->24911
13330 MVT::f32, 2/*#Ops*/, 0, 0,
13342 /* 24928*/ OPC_SwitchType /*2 cases */, 10, MVT::f32,// ->24941
13345 MVT::f32, 2/*#Ops*/, 0, 0,
13358 /* 24959*/ OPC_SwitchType /*2 cases */, 10, MVT::f32,// ->24972
13361 MVT::f32, 2/*#Ops*/, 0, 1,
13374 /* 24990*/ OPC_SwitchType /*2 cases */, 10, MVT::f32,// ->25003
13377 MVT::f32, 2/*#Ops*/, 0, 1,
13397 /* 25034*/ OPC_SwitchType /*2 cases */, 47, MVT::f32,// ->25084
13402 MVT::f32, 3/*#Ops*/, 0, 1, 2,
13409 MVT::f32, 3/*#Ops*/, 0, 1, 2,
13416 MVT::f32, 3/*#Ops*/, 0, 1, 2,
13447 /* 25139*/ OPC_SwitchType /*2 cases */, 47, MVT::f32,// ->25189
13452 MVT::f32, 3/*#Ops*/, 0, 1, 2,
13459 MVT::f32, 3/*#Ops*/, 0, 1, 2,
13466 MVT::f32, 3/*#Ops*/, 0, 1, 2,
13497 /* 25244*/ OPC_SwitchType /*2 cases */, 47, MVT::f32,// ->25294
13502 MVT::f32, 3/*#Ops*/, 0, 1, 2,
13509 MVT::f32, 3/*#Ops*/, 0, 1, 2,
13516 MVT::f32, 3/*#Ops*/, 0, 1, 2,
13547 /* 25349*/ OPC_SwitchType /*2 cases */, 47, MVT::f32,// ->25399
13552 MVT::f32, 3/*#Ops*/, 0, 1, 2,
13559 MVT::f32, 3/*#Ops*/, 0, 1, 2,
13566 MVT::f32, 3/*#Ops*/, 0, 1, 2,
13596 /* 25453*/ OPC_SwitchType /*2 cases */, 44, MVT::f32,// ->25500
13601 MVT::f32, 2/*#Ops*/, 0, 1,
13608 MVT::f32, 2/*#Ops*/, 0, 1,
13615 MVT::f32, 2/*#Ops*/, 0, 1,
13647 MVT::f32, 1/*#Ops*/, 0,
13656 MVT::f32, 2/*#Ops*/, 0, 1,
13663 MVT::f32, 2/*#Ops*/, 0, 1,
13670 MVT::f32, 2/*#Ops*/, 0, 1,
gen/lib/Target/RISCV/RISCVGenRegisterInfo.inc 1171 /* 4 */ MVT::f32, MVT::Other,
gen/lib/Target/Sparc/SparcGenCallingConv.inc 33 LocVT == MVT::f32) {
67 LocVT == MVT::f32) {
104 if (LocVT == MVT::f32) {
137 if (LocVT == MVT::f32) {
gen/lib/Target/Sparc/SparcGenDAGISel.inc 218 /* 299*/ OPC_CheckChild1Type, MVT::f32,
1199 /* 2150*/ OPC_SwitchType /*4 cases */, 28, MVT::f32,// ->2181
1204 MVT::f32, 2/*#Ops*/, 2, 3,
1211 MVT::f32, 2/*#Ops*/, 2, 3,
1759 /* 3223*/ /*SwitchType*/ 28, MVT::f32,// ->3253
1764 MVT::f32, 3/*#Ops*/, 0, 1, 3,
1770 MVT::f32, 3/*#Ops*/, 0, 1, 3,
1864 /* 3429*/ /*SwitchType*/ 28, MVT::f32,// ->3459
1869 MVT::f32, 3/*#Ops*/, 0, 1, 3,
1875 MVT::f32, 3/*#Ops*/, 0, 1, 3,
1961 /* 3619*/ /*SwitchType*/ 13, MVT::f32,// ->3634
1965 MVT::f32, 3/*#Ops*/, 0, 1, 3,
2925 /* 5396*/ OPC_CheckChild0Type, MVT::f32,
3051 /* 5637*/ OPC_SwitchType /*3 cases */, 10, MVT::f32,// ->5650
3054 MVT::f32, 2/*#Ops*/, 0, 1,
3072 /* 5678*/ OPC_SwitchType /*3 cases */, 7, MVT::f32,// ->5688
3074 MVT::f32, 1/*#Ops*/, 0,
3092 /* 5715*/ OPC_CheckChild0Type, MVT::f32,
3094 MVT::f32, 1/*#Ops*/, 0,
3100 MVT::f32, 1/*#Ops*/, 0,
3107 MVT::f32, 1/*#Ops*/, 0,
3120 /* 5765*/ OPC_CheckChild0Type, MVT::f32,
3137 /* 5794*/ OPC_SwitchType /*2 cases */, 24, MVT::f32,// ->5821
3141 MVT::f32, 1/*#Ops*/, 0,
3148 MVT::f32, 1/*#Ops*/, 0,
3161 /* 5837*/ OPC_SwitchType /*3 cases */, 7, MVT::f32,// ->5847
3163 MVT::f32, 1/*#Ops*/, 0,
3181 /* 5874*/ OPC_SwitchType /*3 cases */, 7, MVT::f32,// ->5884
3183 MVT::f32, 1/*#Ops*/, 0,
3201 /* 5911*/ OPC_SwitchType /*3 cases */, 9, MVT::f32,// ->5923
3204 MVT::f32, 1/*#Ops*/, 0,
3222 /* 5949*/ OPC_SwitchType /*3 cases */, 8, MVT::f32,// ->5960
3224 MVT::f32, 2/*#Ops*/, 0, 1,
3242 /* 5988*/ OPC_SwitchType /*3 cases */, 8, MVT::f32,// ->5999
3244 MVT::f32, 2/*#Ops*/, 0, 1,
3262 /* 6027*/ OPC_SwitchType /*3 cases */, 8, MVT::f32,// ->6038
3264 MVT::f32, 2/*#Ops*/, 0, 1,
3281 /* 6065*/ OPC_SwitchType /*3 cases */, 9, MVT::f32,// ->6077
3284 MVT::f32, 1/*#Ops*/, 0,
3303 /* 6106*/ OPC_CheckChild0Type, MVT::f32,
gen/lib/Target/Sparc/SparcGenRegisterInfo.inc 1946 /* 7 */ MVT::f32, MVT::Other,
gen/lib/Target/SystemZ/SystemZGenCallingConv.inc 81 if (LocVT == MVT::f32) {
149 LocVT == MVT::f32 ||
205 if (LocVT == MVT::f32) {
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc 627 /* 1049*/ OPC_CheckType, MVT::f32,
664 /* 1117*/ OPC_CheckType, MVT::f32,
3531 /* 6991*/ /*SwitchType*/ 32, MVT::f32,// ->7025
3670 /* 7272*/ OPC_CheckType, MVT::f32,
4001 /* 7909*/ OPC_CheckChild1Type, MVT::f32,
13414 /* 24668*/ /*SwitchType*/ 32, MVT::f32,// ->24702
13419 MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
13425 MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
18514 /* 34523*/ OPC_CheckChild0Type, MVT::f32,
19444 /* 36332*/ OPC_SwitchType /*3 cases */, 46, MVT::f32,// ->36381
19450 MVT::f32, 3/*#Ops*/, 2, 3, 4,
19457 MVT::f32, 3/*#Ops*/, 2, 3, 4,
19464 MVT::f32, 3/*#Ops*/, 2, 3, 4,
20477 /* 38432*/ OPC_CheckChild0Type, MVT::f32,
20920 /* 39344*/ OPC_CheckType, MVT::f32,
20923 MVT::f32, 2/*#Ops*/, 0, 1,
20932 /* 39366*/ OPC_CheckType, MVT::f32,
20938 MVT::f32, 2/*#Ops*/, 3, 4,
21525 /* 40445*/ OPC_CheckChild0Type, MVT::f32,
21699 /* 40682*/ OPC_CheckType, MVT::f32,
21702 MVT::f32, 1/*#Ops*/, 0,
21744 /* 40749*/ OPC_CheckChild1Type, MVT::f32,
21819 /* 40905*/ OPC_CheckChild0Type, MVT::f32,
21887 /* 41054*/ OPC_CheckChild1Type, MVT::f32,
21974 /* 41246*/ OPC_CheckChild0Type, MVT::f32,
22158 /* 41631*/ OPC_SwitchType /*2 cases */, 18, MVT::f32,// ->41652
22162 MVT::f32, 5/*#Ops*/, 4, 1, 5, 6, 7,
22175 /* 41675*/ OPC_SwitchType /*2 cases */, 18, MVT::f32,// ->41696
22179 MVT::f32, 5/*#Ops*/, 4, 1, 5, 6, 7,
22213 /* 41758*/ /*SwitchType*/ 26, MVT::f32,// ->41786
22218 MVT::f32, 3/*#Ops*/, 1, 2, 3,
22224 MVT::f32, 3/*#Ops*/, 3, 1, 2,
22253 /* 41832*/ /*SwitchType*/ 26, MVT::f32,// ->41860
22258 MVT::f32, 3/*#Ops*/, 1, 2, 3,
22264 MVT::f32, 3/*#Ops*/, 3, 1, 2,
22333 /* 41976*/ OPC_SwitchType /*2 cases */, 15, MVT::f32,// ->41994
22337 MVT::f32, 5/*#Ops*/, 3, 0, 4, 5, 6,
22350 /* 42014*/ OPC_SwitchType /*2 cases */, 15, MVT::f32,// ->42032
22354 MVT::f32, 5/*#Ops*/, 3, 0, 4, 5, 6,
22386 /* 42089*/ /*SwitchType*/ 24, MVT::f32,// ->42115
22390 MVT::f32, 3/*#Ops*/, 0, 1, 2,
22395 MVT::f32, 3/*#Ops*/, 2, 0, 1,
22421 /* 42158*/ /*SwitchType*/ 24, MVT::f32,// ->42184
22425 MVT::f32, 3/*#Ops*/, 0, 1, 2,
22430 MVT::f32, 3/*#Ops*/, 2, 0, 1,
22597 /* 42528*/ OPC_SwitchType /*2 cases */, 17, MVT::f32,// ->42548
22601 MVT::f32, 4/*#Ops*/, 1, 4, 5, 6,
22624 /* 42587*/ OPC_SwitchType /*2 cases */, 17, MVT::f32,// ->42607
22628 MVT::f32, 4/*#Ops*/, 3, 4, 5, 6,
22698 /* 42744*/ /*SwitchType*/ 24, MVT::f32,// ->42770
22703 MVT::f32, 2/*#Ops*/, 1, 2,
22709 MVT::f32, 2/*#Ops*/, 1, 2,
22864 /* 43074*/ OPC_SwitchType /*2 cases */, 14, MVT::f32,// ->43091
22868 MVT::f32, 4/*#Ops*/, 0, 3, 4, 5,
22891 /* 43127*/ OPC_SwitchType /*2 cases */, 14, MVT::f32,// ->43144
22895 MVT::f32, 4/*#Ops*/, 2, 3, 4, 5,
22961 /* 43274*/ /*SwitchType*/ 22, MVT::f32,// ->43298
22965 MVT::f32, 2/*#Ops*/, 0, 1,
22970 MVT::f32, 2/*#Ops*/, 0, 1,
23023 /* 43391*/ OPC_CheckType, MVT::f32,
23081 /* 43497*/ OPC_CheckChild1Type, MVT::f32,
23115 /* 43555*/ OPC_SwitchType /*2 cases */, 16, MVT::f32,// ->43574
23119 MVT::f32, 3/*#Ops*/, 3, 4, 5,
23147 /* 43620*/ /*SwitchType*/ 22, MVT::f32,// ->43644
23152 MVT::f32, 1/*#Ops*/, 1,
23158 MVT::f32, 1/*#Ops*/, 1,
23204 /* 43714*/ OPC_SwitchType /*2 cases */, 13, MVT::f32,// ->43730
23208 MVT::f32, 3/*#Ops*/, 2, 3, 4,
23234 /* 43771*/ /*SwitchType*/ 20, MVT::f32,// ->43793
23238 MVT::f32, 1/*#Ops*/, 0,
23243 MVT::f32, 1/*#Ops*/, 0,
23288 /* 43862*/ OPC_SwitchType /*2 cases */, 18, MVT::f32,// ->43883
23292 MVT::f32, MVT::i32, 4/*#Ops*/, 1, 4, 5, 6,
23315 /* 43921*/ OPC_SwitchType /*2 cases */, 18, MVT::f32,// ->43942
23319 MVT::f32, MVT::i32, 4/*#Ops*/, 3, 4, 5, 6,
23348 /* 43994*/ /*SwitchType*/ 25, MVT::f32,// ->44021
23353 MVT::f32, 2/*#Ops*/, 1, 2,
23359 MVT::f32, MVT::i32, 2/*#Ops*/, 1, 2,
23407 /* 44098*/ OPC_SwitchType /*2 cases */, 15, MVT::f32,// ->44116
23411 MVT::f32, MVT::i32, 4/*#Ops*/, 0, 3, 4, 5,
23434 /* 44151*/ OPC_SwitchType /*2 cases */, 15, MVT::f32,// ->44169
23438 MVT::f32, MVT::i32, 4/*#Ops*/, 2, 3, 4, 5,
23465 /* 44216*/ /*SwitchType*/ 23, MVT::f32,// ->44241
23469 MVT::f32, 2/*#Ops*/, 0, 1,
23474 MVT::f32, MVT::i32, 2/*#Ops*/, 0, 1,
23519 /* 44315*/ OPC_SwitchType /*2 cases */, 18, MVT::f32,// ->44336
23523 MVT::f32, MVT::i32, 4/*#Ops*/, 1, 4, 5, 6,
23551 /* 44387*/ /*SwitchType*/ 25, MVT::f32,// ->44414
23556 MVT::f32, 2/*#Ops*/, 1, 2,
23562 MVT::f32, MVT::i32, 2/*#Ops*/, 1, 2,
23610 /* 44491*/ OPC_SwitchType /*2 cases */, 15, MVT::f32,// ->44509
23614 MVT::f32, MVT::i32, 4/*#Ops*/, 0, 3, 4, 5,
23640 /* 44555*/ /*SwitchType*/ 23, MVT::f32,// ->44580
23644 MVT::f32, 2/*#Ops*/, 0, 1,
23649 MVT::f32, MVT::i32, 2/*#Ops*/, 0, 1,
23694 /* 44654*/ OPC_SwitchType /*2 cases */, 17, MVT::f32,// ->44674
23698 MVT::f32, 4/*#Ops*/, 1, 4, 5, 6,
23726 /* 44723*/ /*SwitchType*/ 24, MVT::f32,// ->44749
23731 MVT::f32, 2/*#Ops*/, 1, 2,
23737 MVT::f32, 2/*#Ops*/, 1, 2,
23785 /* 44825*/ OPC_SwitchType /*2 cases */, 14, MVT::f32,// ->44842
23789 MVT::f32, 4/*#Ops*/, 0, 3, 4, 5,
23815 /* 44886*/ /*SwitchType*/ 22, MVT::f32,// ->44910
23819 MVT::f32, 2/*#Ops*/, 0, 1,
23824 MVT::f32, 2/*#Ops*/, 0, 1,
23875 /* 44999*/ /*SwitchType*/ 12, MVT::f32,// ->45013
23879 MVT::f32, 3/*#Ops*/, 1, 2, 3,
23900 /* 45046*/ /*SwitchType*/ 12, MVT::f32,// ->45060
23904 MVT::f32, 3/*#Ops*/, 1, 2, 3,
23931 /* 45104*/ /*SwitchType*/ 11, MVT::f32,// ->45117
23934 MVT::f32, 3/*#Ops*/, 0, 1, 2,
23953 /* 45148*/ /*SwitchType*/ 11, MVT::f32,// ->45161
23956 MVT::f32, 3/*#Ops*/, 0, 1, 2,
23983 /* 45204*/ /*SwitchType*/ 20, MVT::f32,// ->45226
23987 MVT::f32, 1/*#Ops*/, 0,
23992 MVT::f32, 1/*#Ops*/, 0,
24026 /* 45276*/ /*SwitchType*/ 20, MVT::f32,// ->45298
24030 MVT::f32, 1/*#Ops*/, 0,
24035 MVT::f32, 1/*#Ops*/, 0,
24177 /* 45548*/ OPC_SwitchType /*2 cases */, 51, MVT::f32,// ->45602
24180 /* 45554*/ OPC_CheckType, MVT::f32,
24187 MVT::f32, 2/*#Ops*/, 0, 3,
24196 MVT::f32, 2/*#Ops*/, 0, 3,
24226 /* 45659*/ OPC_CheckChild1Type, MVT::f32,
24227 /* 45661*/ OPC_SwitchType /*3 cases */, 8, MVT::f32,// ->45672
24229 MVT::f32, 2/*#Ops*/, 0, 1,
24252 /* 45721*/ OPC_SwitchType /*3 cases */, 8, MVT::f32,// ->45732
24254 MVT::f32, 2/*#Ops*/, 0, 1,
24310 /* 45857*/ /*SwitchType*/ 6, MVT::f32,// ->45865
24312 MVT::f32, 0/*#Ops*/,
24340 /* 45913*/ /*SwitchType*/ 13, MVT::f32,// ->45928
24342 MVT::f32, 0/*#Ops*/, // Results = #0
24344 MVT::f32, 1/*#Ops*/, 0,
24377 /* 45988*/ /*SwitchType*/ 34, MVT::f32,// ->46024
24384 MVT::f32, 3/*#Ops*/, 1, 2, 3,
24391 MVT::f32, 2/*#Ops*/, 2, 1,
24452 /* 46147*/ /*SwitchType*/ 32, MVT::f32,// ->46181
24458 MVT::f32, 3/*#Ops*/, 0, 1, 2,
24464 MVT::f32, 2/*#Ops*/, 1, 0,
24524 /* 46303*/ /*SwitchType*/ 40, MVT::f32,// ->46345
24531 MVT::f32, 3/*#Ops*/, 1, 2, 3,
24540 MVT::f32, 3/*#Ops*/, 2, 1, 3,
24605 /* 46480*/ /*SwitchType*/ 38, MVT::f32,// ->46520
24611 MVT::f32, 3/*#Ops*/, 0, 1, 2,
24619 MVT::f32, 3/*#Ops*/, 1, 0, 2,
24681 /* 46648*/ /*SwitchType*/ 40, MVT::f32,// ->46690
24688 MVT::f32, 3/*#Ops*/, 1, 2, 3,
24697 MVT::f32, 3/*#Ops*/, 2, 1, 3,
24762 /* 46825*/ /*SwitchType*/ 38, MVT::f32,// ->46865
24768 MVT::f32, 3/*#Ops*/, 0, 1, 2,
24776 MVT::f32, 3/*#Ops*/, 1, 0, 2,
24838 /* 46993*/ /*SwitchType*/ 40, MVT::f32,// ->47035
24845 MVT::f32, 3/*#Ops*/, 1, 2, 3,
24854 MVT::f32, 3/*#Ops*/, 2, 1, 3,
24919 /* 47170*/ /*SwitchType*/ 38, MVT::f32,// ->47210
24925 MVT::f32, 3/*#Ops*/, 0, 1, 2,
24933 MVT::f32, 3/*#Ops*/, 1, 0, 2,
24995 /* 47338*/ /*SwitchType*/ 40, MVT::f32,// ->47380
25002 MVT::f32, 3/*#Ops*/, 1, 2, 3,
25011 MVT::f32, 3/*#Ops*/, 2, 1, 3,
25076 /* 47515*/ /*SwitchType*/ 38, MVT::f32,// ->47555
25082 MVT::f32, 3/*#Ops*/, 0, 1, 2,
25090 MVT::f32, 3/*#Ops*/, 1, 0, 2,
25152 /* 47683*/ /*SwitchType*/ 40, MVT::f32,// ->47725
25159 MVT::f32, 3/*#Ops*/, 1, 2, 3,
25168 MVT::f32, 3/*#Ops*/, 2, 1, 3,
25233 /* 47860*/ /*SwitchType*/ 38, MVT::f32,// ->47900
25239 MVT::f32, 3/*#Ops*/, 0, 1, 2,
25247 MVT::f32, 3/*#Ops*/, 1, 0, 2,
25318 /* 48035*/ OPC_CheckChild0Type, MVT::f32,
25339 /* 48074*/ OPC_SwitchType /*2 cases */, 96, MVT::f32,// ->48173
25348 MVT::f32, 3/*#Ops*/, 1, 2, 3,
25354 MVT::f32, 1/*#Ops*/, 1,
25370 MVT::f32, 3/*#Ops*/, 4, 5, 6,
25380 MVT::f32, 2/*#Ops*/, 2, 3,
25409 /* 48224*/ OPC_SwitchType /*2 cases */, 92, MVT::f32,// ->48319
25417 MVT::f32, 3/*#Ops*/, 0, 1, 2,
25422 MVT::f32, 1/*#Ops*/, 0,
25437 MVT::f32, 3/*#Ops*/, 3, 4, 5,
25446 MVT::f32, 2/*#Ops*/, 1, 2,
25483 /* 48387*/ /*SwitchType*/ 15, MVT::f32,// ->48404
25488 MVT::f32, 3/*#Ops*/, 1, 2, 3,
25528 /* 48484*/ /*SwitchType*/ 14, MVT::f32,// ->48500
25532 MVT::f32, 3/*#Ops*/, 0, 1, 2,
25567 /* 48571*/ /*SwitchType*/ 14, MVT::f32,// ->48587
25571 MVT::f32, 3/*#Ops*/, 0, 1, 2,
25608 /* 48660*/ /*SwitchType*/ 15, MVT::f32,// ->48677
25613 MVT::f32, 3/*#Ops*/, 1, 2, 3,
25653 /* 48757*/ /*SwitchType*/ 14, MVT::f32,// ->48773
25657 MVT::f32, 3/*#Ops*/, 0, 1, 2,
25692 /* 48844*/ /*SwitchType*/ 14, MVT::f32,// ->48860
25696 MVT::f32, 3/*#Ops*/, 0, 1, 2,
25736 /* 48936*/ /*SwitchType*/ 20, MVT::f32,// ->48958
25740 MVT::f32, 1/*#Ops*/, 0,
25745 MVT::f32, 1/*#Ops*/, 0,
25779 /* 49012*/ OPC_SwitchType /*3 cases */, 7, MVT::f32,// ->49022
25781 MVT::f32, 1/*#Ops*/, 0,
25797 /* 49044*/ OPC_SwitchType /*3 cases */, 7, MVT::f32,// ->49054
25799 MVT::f32, 1/*#Ops*/, 0,
25838 /* 49127*/ OPC_SwitchType /*3 cases */, 17, MVT::f32,// ->49147
25843 MVT::f32, 3/*#Ops*/, 1, 0, 2,
25865 /* 49189*/ OPC_SwitchType /*3 cases */, 17, MVT::f32,// ->49209
25870 MVT::f32, 3/*#Ops*/, 1, 0, 2,
25928 /* 49327*/ OPC_CheckType, MVT::f32,
25966 /* 49390*/ OPC_CheckType, MVT::f32,
26656 /* 50668*/ OPC_SwitchType /*2 cases */, 18, MVT::f32,// ->50689
26689 /* 50729*/ OPC_SwitchType /*2 cases */, 30, MVT::f32,// ->50762
28289 /* 53532*/ OPC_SwitchType /*2 cases */, 18, MVT::f32,// ->53553
28313 /* 53579*/ OPC_CheckChild0Type, MVT::f32,
28391 /* 53749*/ /*SwitchType*/ 16, MVT::f32,// ->53767
28414 /* 53792*/ OPC_CheckChild0Type, MVT::f32,
30386 if (cast<MemSDNode>(N)->getMemoryVT() != MVT::f32) return false;
gen/lib/Target/SystemZ/SystemZGenRegisterInfo.inc 1848 /* 4 */ MVT::f32, MVT::Other,
1851 /* 16 */ MVT::f32, MVT::v4i8, MVT::v2i16, MVT::Other,
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc 7726 /* 14324*/ OPC_CheckChild0Type, MVT::f32,
10216 /* 19356*/ OPC_SwitchType /*2 cases */, 15, MVT::f32,// ->19374
10221 MVT::f32, 3/*#Ops*/, 3, 4, 1,
10244 /* 19411*/ OPC_SwitchType /*2 cases */, 15, MVT::f32,// ->19429
10249 MVT::f32, 3/*#Ops*/, 3, 4, 1,
10269 /* 19461*/ OPC_SwitchType /*2 cases */, 25, MVT::f32,// ->19489
10277 MVT::f32, 3/*#Ops*/, 2, 1, 4,
10301 /* 19531*/ OPC_SwitchType /*2 cases */, 25, MVT::f32,// ->19559
10309 MVT::f32, 3/*#Ops*/, 2, 3, 5,
10328 /* 19594*/ OPC_SwitchType /*2 cases */, 16, MVT::f32,// ->19613
10333 MVT::f32, 3/*#Ops*/, 2, 3, 1,
11810 /* 22726*/ OPC_CheckChild1Type, MVT::f32,
12749 /* 24545*/ OPC_SwitchType /*2 cases */, 9, MVT::f32,// ->24557
12751 MVT::f32, 3/*#Ops*/, 1, 2, 0,
12765 /* 24575*/ OPC_SwitchType /*2 cases */, 9, MVT::f32,// ->24587
12767 MVT::f32, 3/*#Ops*/, 2, 1, 0,
12784 /* 24611*/ OPC_SwitchType /*2 cases */, 9, MVT::f32,// ->24623
12786 MVT::f32, 3/*#Ops*/, 1, 2, 0,
12801 /* 24642*/ OPC_SwitchType /*2 cases */, 9, MVT::f32,// ->24654
12803 MVT::f32, 3/*#Ops*/, 1, 2, 0,
15320 /* 29958*/ OPC_SwitchType /*2 cases */, 8, MVT::f32,// ->29969
15323 MVT::f32, 1/*#Ops*/, 1,
15336 /* 29985*/ OPC_SwitchType /*2 cases */, 8, MVT::f32,// ->29996
15339 MVT::f32, 1/*#Ops*/, 1,
15357 /* 30019*/ OPC_SwitchType /*2 cases */, 10, MVT::f32,// ->30032
15361 MVT::f32, 1/*#Ops*/, 2,
15374 /* 30048*/ OPC_SwitchType /*2 cases */, 8, MVT::f32,// ->30059
15377 MVT::f32, 1/*#Ops*/, 1,
15757 /* 30686*/ OPC_CheckChild1Type, MVT::f32,
15801 /* 30763*/ OPC_CheckChild1Type, MVT::f32,
15845 /* 30840*/ OPC_CheckChild1Type, MVT::f32,
15875 /* 30893*/ OPC_CheckChild1Type, MVT::f32,
16373 /* 31805*/ OPC_CheckType, MVT::f32,
16377 MVT::f32, 2/*#Ops*/, 0, 2,
16384 /* 31825*/ OPC_CheckType, MVT::f32,
16387 MVT::f32, 2/*#Ops*/, 0, 1,
16439 /* 31926*/ /*SwitchType*/ 7, MVT::f32,// ->31935
16441 MVT::f32, 1/*#Ops*/, 0,
18441 /* 35337*/ OPC_CheckChild0Type, MVT::f32,
18520 /* 35474*/ OPC_CheckChild0Type, MVT::f32,
18599 /* 35611*/ OPC_CheckChild0Type, MVT::f32,
18614 /* 35637*/ OPC_CheckType, MVT::f32,
18616 MVT::f32, 1/*#Ops*/, 0,
18767 /* 35843*/ OPC_SwitchType /*2 cases */, 9, MVT::f32,// ->35855
18770 MVT::f32, 1/*#Ops*/, 1,
18784 /* 35875*/ OPC_SwitchType /*2 cases */, 7, MVT::f32,// ->35885
18786 MVT::f32, 1/*#Ops*/, 0,
18797 /* 35898*/ OPC_SwitchType /*2 cases */, 7, MVT::f32,// ->35908
18799 MVT::f32, 1/*#Ops*/, 0,
18827 /* 35951*/ OPC_SwitchType /*2 cases */, 7, MVT::f32,// ->35961
18829 MVT::f32, 1/*#Ops*/, 0,
18840 /* 35974*/ OPC_SwitchType /*2 cases */, 7, MVT::f32,// ->35984
18842 MVT::f32, 1/*#Ops*/, 0,
18875 MVT::f32, 1/*#Ops*/, 0,
18881 /* 36046*/ OPC_SwitchType /*4 cases */, 8, MVT::f32,// ->36057
18883 MVT::f32, 2/*#Ops*/, 0, 1,
18907 /* 36097*/ OPC_SwitchType /*4 cases */, 8, MVT::f32,// ->36108
18909 MVT::f32, 2/*#Ops*/, 0, 1,
18933 /* 36148*/ OPC_SwitchType /*4 cases */, 8, MVT::f32,// ->36159
18935 MVT::f32, 2/*#Ops*/, 0, 1,
18959 /* 36199*/ OPC_SwitchType /*4 cases */, 8, MVT::f32,// ->36210
18961 MVT::f32, 2/*#Ops*/, 0, 1,
18984 /* 36249*/ OPC_SwitchType /*4 cases */, 7, MVT::f32,// ->36259
18986 MVT::f32, 1/*#Ops*/, 0,
19009 /* 36295*/ OPC_SwitchType /*4 cases */, 7, MVT::f32,// ->36305
19011 MVT::f32, 1/*#Ops*/, 0,
19034 /* 36341*/ OPC_SwitchType /*4 cases */, 7, MVT::f32,// ->36351
19036 MVT::f32, 1/*#Ops*/, 0,
19061 /* 36390*/ OPC_CheckChild1Type, MVT::f32,
19062 /* 36392*/ OPC_SwitchType /*2 cases */, 8, MVT::f32,// ->36403
19064 MVT::f32, 2/*#Ops*/, 0, 1,
19082 /* 36435*/ /*SwitchType*/ 15, MVT::f32,// ->36452
19084 MVT::f32, 1/*#Ops*/, 1, // Results = #2
19086 MVT::f32, 2/*#Ops*/, 0, 2,
19094 /* 36459*/ OPC_SwitchType /*4 cases */, 8, MVT::f32,// ->36470
19096 MVT::f32, 2/*#Ops*/, 0, 1,
19120 /* 36510*/ OPC_SwitchType /*4 cases */, 8, MVT::f32,// ->36521
19122 MVT::f32, 2/*#Ops*/, 0, 1,
19145 /* 36560*/ OPC_SwitchType /*2 cases */, 7, MVT::f32,// ->36570
19147 MVT::f32, 1/*#Ops*/, 0,
19158 /* 36584*/ OPC_SwitchType /*2 cases */, 7, MVT::f32,// ->36594
19160 MVT::f32, 1/*#Ops*/, 0,
19171 /* 36608*/ OPC_SwitchType /*2 cases */, 7, MVT::f32,// ->36618
19173 MVT::f32, 1/*#Ops*/, 0,
19184 /* 36632*/ OPC_SwitchType /*2 cases */, 7, MVT::f32,// ->36642
19186 MVT::f32, 1/*#Ops*/, 0,
19197 /* 36656*/ OPC_SwitchType /*2 cases */, 7, MVT::f32,// ->36666
19199 MVT::f32, 1/*#Ops*/, 0,
19507 /* 37222*/ OPC_CheckChild0Type, MVT::f32,
19529 /* 37262*/ OPC_SwitchType /*2 cases */, 47, MVT::f32,// ->37312
19534 /* 37271*/ OPC_CheckType, MVT::f32,
19539 /* 37279*/ OPC_CheckType, MVT::f32,
19544 /* 37287*/ OPC_CheckType, MVT::f32,
20651 /* 39459*/ OPC_SwitchType /*2 cases */, 20, MVT::f32,// ->39482
20685 /* 39524*/ OPC_SwitchType /*2 cases */, 20, MVT::f32,// ->39547
20716 /* 39584*/ OPC_SwitchType /*2 cases */, 28, MVT::f32,// ->39615
20752 /* 39661*/ OPC_SwitchType /*2 cases */, 30, MVT::f32,// ->39694
20785 /* 39734*/ OPC_SwitchType /*2 cases */, 21, MVT::f32,// ->39758
20903 /* 39965*/ OPC_CheckChild1Type, MVT::f32,
20996 /* 40138*/ OPC_CheckChild0Type, MVT::f32,
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 52 if (RetVT.SimpleTy != MVT::f32)
79 case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0, Op0IsKill);
154 if (RetVT.SimpleTy != MVT::f32)
185 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
196 if (RetVT.SimpleTy != MVT::f32)
209 case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0, Op0IsKill);
218 if (RetVT.SimpleTy != MVT::f32)
231 case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
240 if (RetVT.SimpleTy != MVT::f32)
253 case MVT::f32: return fastEmit_ISD_FNEARBYINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
262 if (RetVT.SimpleTy != MVT::f32)
293 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
311 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill);
319 if (RetVT.SimpleTy != MVT::f32)
409 case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
495 case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
506 if (RetVT.SimpleTy != MVT::f32)
519 case MVT::f32: return fastEmit_ISD_FRINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
528 if (RetVT.SimpleTy != MVT::f32)
559 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
570 if (RetVT.SimpleTy != MVT::f32)
583 case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0, Op0IsKill);
634 case MVT::f32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
667 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill);
683 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(Op0, Op0IsKill);
744 case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill);
760 case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f32_r(Op0, Op0IsKill);
917 case MVT::f32: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_f32_r(Op0, Op0IsKill);
1117 if (RetVT.SimpleTy != MVT::f32)
1148 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1159 if (RetVT.SimpleTy != MVT::f32)
1172 case MVT::f32: return fastEmit_ISD_FCOPYSIGN_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1181 if (RetVT.SimpleTy != MVT::f32)
1212 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1223 if (RetVT.SimpleTy != MVT::f32)
1254 case MVT::f32: return fastEmit_ISD_FMAXIMUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1265 if (RetVT.SimpleTy != MVT::f32)
1296 case MVT::f32: return fastEmit_ISD_FMINIMUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1307 if (RetVT.SimpleTy != MVT::f32)
1338 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1349 if (RetVT.SimpleTy != MVT::f32)
1380 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1943 if (RetVT.SimpleTy != MVT::f32)
2056 if (RetVT.SimpleTy != MVT::f32)
2069 case MVT::f32: return fastEmit_ISD_ConstantFP_MVT_f32_f(RetVT, f0);
2177 case MVT::f32: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_f32_i(imm0);
gen/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc 304 /* 4 */ MVT::f32, MVT::Other,
gen/lib/Target/X86/X86GenCallingConv.inc 225 if (LocVT == MVT::f32 ||
434 if (LocVT == MVT::f32 ||
462 LocVT == MVT::f32) {
599 if (LocVT == MVT::f32 ||
745 LocVT == MVT::f32) {
875 if (LocVT == MVT::f32 ||
950 LocVT == MVT::f32 ||
959 LocVT == MVT::f32) {
1539 if (LocVT == MVT::f32 ||
1599 LocVT == MVT::f32 ||
1678 if (LocVT == MVT::f32 ||
1799 LocVT == MVT::f32 ||
1840 LocVT == MVT::f32) {
1947 if (LocVT == MVT::f32 ||
2022 LocVT == MVT::f32 ||
2031 LocVT == MVT::f32) {
2285 if (LocVT == MVT::f32 ||
2309 LocVT == MVT::f32 ||
2410 if (LocVT == MVT::f32 ||
2485 LocVT == MVT::f32 ||
2494 LocVT == MVT::f32) {
2585 if (LocVT == MVT::f32 ||
2888 if (LocVT == MVT::f32 ||
2901 if (LocVT == MVT::f32 ||
2923 if (LocVT == MVT::f32) {
3122 if (LocVT == MVT::f32 ||
3195 if (LocVT == MVT::f32 ||
3297 if (LocVT == MVT::f32) {
3486 if (LocVT == MVT::f32) {
3537 if (LocVT == MVT::f32 ||
3698 if (LocVT == MVT::f32 ||
3898 if (LocVT == MVT::f32 ||
gen/lib/Target/X86/X86GenDAGISel.inc 509 /* 949*/ OPC_CheckChild1Type, MVT::f32,
6242 /* 13388*/ OPC_CheckChild1Type, MVT::f32,
9758 /* 21085*/ OPC_CheckChild0Type, MVT::f32,
10274 /* 22114*/ OPC_CheckChild0Type, MVT::f32,
10606 /* 22723*/ OPC_CheckChild0Type, MVT::f32,
33534 /* 69700*/ OPC_SwitchType /*3 cases */, 14, MVT::f32,// ->69717
33538 MVT::f32, MVT::i16, 2/*#Ops*/, 0, 1,
33559 /* 69754*/ OPC_SwitchType /*3 cases */, 14, MVT::f32,// ->69771
33563 MVT::f32, MVT::i16, 2/*#Ops*/, 0, 1,
33584 /* 69808*/ OPC_SwitchType /*3 cases */, 14, MVT::f32,// ->69825
33588 MVT::f32, MVT::i16, 2/*#Ops*/, 0, 1,
33609 /* 69862*/ OPC_SwitchType /*3 cases */, 14, MVT::f32,// ->69879
33613 MVT::f32, MVT::i16, 2/*#Ops*/, 0, 1,
33634 /* 69916*/ OPC_SwitchType /*3 cases */, 14, MVT::f32,// ->69933
33638 MVT::f32, MVT::i16, 2/*#Ops*/, 0, 1,
33659 /* 69970*/ OPC_SwitchType /*3 cases */, 14, MVT::f32,// ->69987
33663 MVT::f32, MVT::i16, 2/*#Ops*/, 0, 1,
33684 /* 70024*/ OPC_SwitchType /*3 cases */, 14, MVT::f32,// ->70041
33688 MVT::f32, MVT::i16, 2/*#Ops*/, 0, 1,
33709 /* 70078*/ OPC_SwitchType /*3 cases */, 14, MVT::f32,// ->70095
33713 MVT::f32, MVT::i16, 2/*#Ops*/, 0, 1,
33737 /* 70137*/ OPC_SwitchType /*28 cases */, 47, MVT::f32,// ->70187
33742 MVT::f32, 3/*#Ops*/, 0, 1, 2,
33749 MVT::f32, 3/*#Ops*/, 0, 1, 2,
33756 MVT::f32, 3/*#Ops*/, 0, 1, 2,
35636 /* 74211*/ OPC_CheckType, MVT::f32,
35664 /* 74273*/ OPC_CheckType, MVT::f32,
35750 /* 74461*/ OPC_SwitchType /*2 cases */, 45, MVT::f32,// ->74509
35789 /* 74561*/ OPC_SwitchType /*2 cases */, 48, MVT::f32,// ->74612
35841 /* 74688*/ OPC_CheckType, MVT::f32,
35869 /* 74750*/ OPC_CheckType, MVT::f32,
35955 /* 74938*/ OPC_SwitchType /*2 cases */, 45, MVT::f32,// ->74986
35994 /* 75038*/ OPC_SwitchType /*2 cases */, 48, MVT::f32,// ->75089
36046 /* 75165*/ OPC_CheckType, MVT::f32,
36074 /* 75227*/ OPC_CheckType, MVT::f32,
36160 /* 75415*/ OPC_SwitchType /*2 cases */, 45, MVT::f32,// ->75463
36199 /* 75515*/ OPC_SwitchType /*2 cases */, 48, MVT::f32,// ->75566
36251 /* 75642*/ OPC_CheckType, MVT::f32,
36279 /* 75704*/ OPC_CheckType, MVT::f32,
36365 /* 75892*/ OPC_SwitchType /*2 cases */, 45, MVT::f32,// ->75940
36404 /* 75992*/ OPC_SwitchType /*2 cases */, 48, MVT::f32,// ->76043
40534 /* 84800*/ OPC_SwitchType /*2 cases */, 119, MVT::f32,// ->84922
40648 /* 85049*/ OPC_CheckChild0Type, MVT::f32,
41442 /* 86678*/ OPC_SwitchType /*2 cases */, 41, MVT::f32,// ->86722
41484 /* 86770*/ OPC_CheckChild0Type, MVT::f32,
42068 /* 87959*/ OPC_SwitchType /*2 cases */, 59, MVT::f32,// ->88021
42128 /* 88088*/ OPC_CheckChild0Type, MVT::f32,
50452 /*106490*/ OPC_CheckChild1Type, MVT::f32,
50623 /*106878*/ OPC_CheckChild1Type, MVT::f32,
51044 /*107872*/ OPC_SwitchType /*3 cases */, 18, MVT::f32,// ->107893
51049 MVT::f32, MVT::i16, 5/*#Ops*/, 2, 3, 4, 5, 6,
51100 /*108005*/ OPC_SwitchType /*15 cases */, 56, MVT::f32,// ->108064
51106 MVT::f32, 5/*#Ops*/, 2, 3, 4, 5, 6,
51114 MVT::f32, 5/*#Ops*/, 2, 3, 4, 5, 6,
51122 MVT::f32, 5/*#Ops*/, 2, 3, 4, 5, 6,
55006 /*116599*/ OPC_CheckChild0Type, MVT::f32,
56152 /*118944*/ OPC_CheckChild0Type, MVT::f32,
56221 /*119078*/ OPC_CheckType, MVT::f32,
56227 MVT::f32, 5/*#Ops*/, 2, 3, 4, 5, 6,
56235 MVT::f32, 5/*#Ops*/, 2, 3, 4, 5, 6,
56243 MVT::f32, 5/*#Ops*/, 2, 3, 4, 5, 6,
56309 /*119254*/ /*SwitchType*/ 34, MVT::f32,// ->119290
56314 MVT::f32, 1/*#Ops*/, 0,
56320 MVT::f32, 1/*#Ops*/, 0,
56326 MVT::f32, 1/*#Ops*/, 0,
57393 /*121414*/ OPC_CheckType, MVT::f32,
57398 MVT::f32, 2/*#Ops*/, 0, 1,
57405 MVT::f32, 2/*#Ops*/, 0, 1,
58742 /*123824*/ OPC_CheckChild0Type, MVT::f32,
58860 /*124072*/ /*SwitchType*/ 54, MVT::f32,// ->124128
58868 /*124084*/ OPC_CheckType, MVT::f32,
58874 MVT::f32, 7/*#Ops*/, 2, 4, 5, 6, 7, 8, 3,
58882 MVT::f32, 7/*#Ops*/, 2, 4, 5, 6, 7, 8, 3,
58890 /*124134*/ OPC_CheckChild0Type, MVT::f32,
58905 /*124157*/ OPC_CheckType, MVT::f32,
58911 MVT::f32, 7/*#Ops*/, 0, 4, 5, 6, 7, 8, 3,
58919 MVT::f32, 7/*#Ops*/, 0, 4, 5, 6, 7, 8, 3,
58929 /*124209*/ OPC_CheckType, MVT::f32,
58933 MVT::f32, 3/*#Ops*/, 0, 1, 2,
58939 MVT::f32, 3/*#Ops*/, 0, 1, 2,
59019 /*124377*/ OPC_CheckType, MVT::f32,
59026 MVT::f32, 2/*#Ops*/, 8, 9,
59045 /*124442*/ OPC_SwitchType /*2 cases */, 39, MVT::f32,// ->124484
59055 MVT::f32, 2/*#Ops*/, 11, 12,
59081 /*124541*/ OPC_CheckType, MVT::f32,
59091 MVT::f32, 2/*#Ops*/, 5, 6,
59113 /*124626*/ OPC_SwitchType /*2 cases */, 49, MVT::f32,// ->124678
59126 MVT::f32, 2/*#Ops*/, 8, 9,
61429 /*129698*/ OPC_SwitchType /*2 cases */, 73, MVT::f32,// ->129774
61435 MVT::f32, 6/*#Ops*/, 3, 4, 5, 6, 7, 2,
61443 MVT::f32, 0/*#Ops*/, // Results = #8
61445 MVT::f32, 7/*#Ops*/, 8, 3, 4, 5, 6, 7, 2,
61453 MVT::f32, 0/*#Ops*/, // Results = #8
61455 MVT::f32, 7/*#Ops*/, 8, 3, 4, 5, 6, 7, 2,
61496 /*129858*/ OPC_SwitchType /*2 cases */, 49, MVT::f32,// ->129910
61500 MVT::f32, 2/*#Ops*/, 0, 1,
61506 MVT::f32, 0/*#Ops*/, // Results = #2
61508 MVT::f32, 3/*#Ops*/, 2, 0, 1,
61514 MVT::f32, 0/*#Ops*/, // Results = #2
61516 MVT::f32, 3/*#Ops*/, 2, 0, 1,
61847 /*130597*/ OPC_CheckType, MVT::f32,
61853 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
61861 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
61869 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
61918 /*130748*/ OPC_CheckType, MVT::f32,
61924 MVT::f32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
61932 MVT::f32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
61940 MVT::f32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
61988 /*130898*/ OPC_SwitchType /*2 cases */, 19, MVT::f32,// ->130920
61993 MVT::f32, MVT::i16, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
62046 /*131030*/ OPC_CheckType, MVT::f32,
62051 MVT::f32, MVT::i16, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
62057 /*131055*/ OPC_CheckType, MVT::f32,
62062 MVT::f32, MVT::i16, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
62121 /*131194*/ OPC_SwitchType /*2 cases */, 19, MVT::f32,// ->131216
62126 MVT::f32, MVT::i16, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
62182 /*131329*/ OPC_CheckType, MVT::f32,
62187 MVT::f32, MVT::i16, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
62194 /*131355*/ OPC_CheckType, MVT::f32,
62199 MVT::f32, MVT::i16, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
62261 /*131494*/ OPC_SwitchType /*2 cases */, 59, MVT::f32,// ->131556
62267 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
62275 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
62283 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
62325 /*131634*/ OPC_SwitchType /*2 cases */, 59, MVT::f32,// ->131696
62331 MVT::f32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
62339 MVT::f32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
62347 MVT::f32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
62382 /*131764*/ OPC_SwitchType /*3 cases */, 47, MVT::f32,// ->131814
62386 MVT::f32, MVT::i16, 2/*#Ops*/, 0, 1,
62392 MVT::f32, 2/*#Ops*/, 0, 1,
62398 MVT::f32, 2/*#Ops*/, 0, 1,
62404 MVT::f32, 2/*#Ops*/, 0, 1,
62916 /*132911*/ OPC_SwitchType /*2 cases */, 19, MVT::f32,// ->132933
62921 MVT::f32, MVT::i16, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
62974 /*133043*/ OPC_CheckType, MVT::f32,
62979 MVT::f32, MVT::i16, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
62985 /*133068*/ OPC_CheckType, MVT::f32,
62990 MVT::f32, MVT::i16, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
63049 /*133207*/ OPC_SwitchType /*2 cases */, 19, MVT::f32,// ->133229
63054 MVT::f32, MVT::i16, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
63110 /*133342*/ OPC_CheckType, MVT::f32,
63115 MVT::f32, MVT::i16, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
63122 /*133368*/ OPC_CheckType, MVT::f32,
63127 MVT::f32, MVT::i16, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
63190 /*133510*/ OPC_SwitchType /*2 cases */, 59, MVT::f32,// ->133572
63196 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
63204 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
63212 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
63245 /*133636*/ OPC_SwitchType /*3 cases */, 47, MVT::f32,// ->133686
63249 MVT::f32, MVT::i16, 2/*#Ops*/, 0, 1,
63255 MVT::f32, 2/*#Ops*/, 0, 1,
63261 MVT::f32, 2/*#Ops*/, 0, 1,
63267 MVT::f32, 2/*#Ops*/, 0, 1,
63586 /*134352*/ OPC_SwitchType /*2 cases */, 19, MVT::f32,// ->134374
63591 MVT::f32, MVT::i16, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
63644 /*134484*/ OPC_CheckType, MVT::f32,
63649 MVT::f32, MVT::i16, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
63655 /*134509*/ OPC_CheckType, MVT::f32,
63660 MVT::f32, MVT::i16, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
63719 /*134648*/ OPC_SwitchType /*2 cases */, 19, MVT::f32,// ->134670
63724 MVT::f32, MVT::i16, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
63780 /*134783*/ OPC_CheckType, MVT::f32,
63785 MVT::f32, MVT::i16, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
63792 /*134809*/ OPC_CheckType, MVT::f32,
63797 MVT::f32, MVT::i16, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
63859 /*134948*/ OPC_SwitchType /*2 cases */, 59, MVT::f32,// ->135010
63865 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
63873 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
63881 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
63923 /*135088*/ OPC_SwitchType /*2 cases */, 59, MVT::f32,// ->135150
63929 MVT::f32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
63937 MVT::f32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
63945 MVT::f32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
63980 /*135218*/ OPC_SwitchType /*3 cases */, 47, MVT::f32,// ->135268
63984 MVT::f32, MVT::i16, 2/*#Ops*/, 0, 1,
63990 MVT::f32, 2/*#Ops*/, 0, 1,
63996 MVT::f32, 2/*#Ops*/, 0, 1,
64002 MVT::f32, 2/*#Ops*/, 0, 1,
64514 /*136365*/ OPC_SwitchType /*2 cases */, 19, MVT::f32,// ->136387
64519 MVT::f32, MVT::i16, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
64572 /*136497*/ OPC_CheckType, MVT::f32,
64577 MVT::f32, MVT::i16, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
64583 /*136522*/ OPC_CheckType, MVT::f32,
64588 MVT::f32, MVT::i16, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
64647 /*136661*/ OPC_SwitchType /*2 cases */, 19, MVT::f32,// ->136683
64652 MVT::f32, MVT::i16, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
64708 /*136796*/ OPC_CheckType, MVT::f32,
64713 MVT::f32, MVT::i16, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
64720 /*136822*/ OPC_CheckType, MVT::f32,
64725 MVT::f32, MVT::i16, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
64788 /*136964*/ OPC_SwitchType /*2 cases */, 59, MVT::f32,// ->137026
64794 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
64802 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
64810 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
64843 /*137090*/ OPC_SwitchType /*3 cases */, 47, MVT::f32,// ->137140
64847 MVT::f32, MVT::i16, 2/*#Ops*/, 0, 1,
64853 MVT::f32, 2/*#Ops*/, 0, 1,
64859 MVT::f32, 2/*#Ops*/, 0, 1,
64865 MVT::f32, 2/*#Ops*/, 0, 1,
65185 /*137804*/ OPC_CheckType, MVT::f32,
65190 MVT::f32, 7/*#Ops*/, 1, 0, 4, 5, 6, 7, 8,
65204 /*137840*/ OPC_CheckType, MVT::f32,
65209 MVT::f32, 7/*#Ops*/, 3, 0, 4, 5, 6, 7, 8,
65225 /*137878*/ OPC_CheckType, MVT::f32,
65230 MVT::f32, 7/*#Ops*/, 2, 3, 4, 5, 6, 7, 8,
65307 /*138031*/ OPC_CheckType, MVT::f32,
65312 MVT::f32, 7/*#Ops*/, 0, 1, 4, 5, 6, 7, 8,
65326 /*138067*/ OPC_CheckType, MVT::f32,
65331 MVT::f32, 7/*#Ops*/, 0, 4, 5, 6, 7, 8, 3,
65383 /*138175*/ OPC_CheckType, MVT::f32,
65388 MVT::f32, 7/*#Ops*/, 1, 0, 4, 5, 6, 7, 8,
65402 /*138211*/ OPC_CheckType, MVT::f32,
65407 MVT::f32, 7/*#Ops*/, 3, 0, 4, 5, 6, 7, 8,
65423 /*138249*/ OPC_CheckType, MVT::f32,
65428 MVT::f32, 7/*#Ops*/, 2, 3, 4, 5, 6, 7, 8,
65502 /*138407*/ /*SwitchType*/ 19, MVT::f32,// ->138428
65507 MVT::f32, 7/*#Ops*/, 2, 4, 5, 6, 7, 8, 3,
65517 /*138438*/ OPC_SwitchType /*2 cases */, 38, MVT::f32,// ->138479
65521 MVT::f32, 3/*#Ops*/, 1, 0, 2,
65527 MVT::f32, 3/*#Ops*/, 0, 1, 2,
65533 MVT::f32, 3/*#Ops*/, 1, 0, 2,
66483 /*140463*/ OPC_CheckType, MVT::f32,
66488 MVT::f32, 7/*#Ops*/, 1, 0, 4, 5, 6, 7, 8,
66502 /*140499*/ OPC_CheckType, MVT::f32,
66507 MVT::f32, 7/*#Ops*/, 3, 0, 4, 5, 6, 7, 8,
66523 /*140537*/ OPC_CheckType, MVT::f32,
66528 MVT::f32, 7/*#Ops*/, 2, 3, 4, 5, 6, 7, 8,
66605 /*140690*/ OPC_CheckType, MVT::f32,
66610 MVT::f32, 7/*#Ops*/, 0, 1, 4, 5, 6, 7, 8,
66624 /*140726*/ OPC_CheckType, MVT::f32,
66629 MVT::f32, 7/*#Ops*/, 0, 4, 5, 6, 7, 8, 3,
66681 /*140834*/ OPC_CheckType, MVT::f32,
66686 MVT::f32, 7/*#Ops*/, 1, 0, 4, 5, 6, 7, 8,
66700 /*140870*/ OPC_CheckType, MVT::f32,
66705 MVT::f32, 7/*#Ops*/, 3, 0, 4, 5, 6, 7, 8,
66721 /*140908*/ OPC_CheckType, MVT::f32,
66726 MVT::f32, 7/*#Ops*/, 2, 3, 4, 5, 6, 7, 8,
66800 /*141066*/ /*SwitchType*/ 19, MVT::f32,// ->141087
66805 MVT::f32, 7/*#Ops*/, 2, 4, 5, 6, 7, 8, 3,
66815 /*141097*/ OPC_SwitchType /*2 cases */, 38, MVT::f32,// ->141138
66819 MVT::f32, 3/*#Ops*/, 1, 0, 2,
66825 MVT::f32, 3/*#Ops*/, 0, 1, 2,
66831 MVT::f32, 3/*#Ops*/, 1, 0, 2,
67781 /*143122*/ OPC_CheckType, MVT::f32,
67786 MVT::f32, 7/*#Ops*/, 1, 0, 4, 5, 6, 7, 8,
67800 /*143158*/ OPC_CheckType, MVT::f32,
67805 MVT::f32, 7/*#Ops*/, 3, 0, 4, 5, 6, 7, 8,
67821 /*143196*/ OPC_CheckType, MVT::f32,
67826 MVT::f32, 7/*#Ops*/, 2, 3, 4, 5, 6, 7, 8,
67903 /*143349*/ OPC_CheckType, MVT::f32,
67908 MVT::f32, 7/*#Ops*/, 0, 1, 4, 5, 6, 7, 8,
67922 /*143385*/ OPC_CheckType, MVT::f32,
67927 MVT::f32, 7/*#Ops*/, 0, 4, 5, 6, 7, 8, 3,
67979 /*143493*/ OPC_CheckType, MVT::f32,
67984 MVT::f32, 7/*#Ops*/, 1, 0, 4, 5, 6, 7, 8,
67998 /*143529*/ OPC_CheckType, MVT::f32,
68003 MVT::f32, 7/*#Ops*/, 3, 0, 4, 5, 6, 7, 8,
68019 /*143567*/ OPC_CheckType, MVT::f32,
68024 MVT::f32, 7/*#Ops*/, 2, 3, 4, 5, 6, 7, 8,
68098 /*143725*/ /*SwitchType*/ 19, MVT::f32,// ->143746
68103 MVT::f32, 7/*#Ops*/, 2, 4, 5, 6, 7, 8, 3,
68113 /*143756*/ OPC_SwitchType /*2 cases */, 38, MVT::f32,// ->143797
68117 MVT::f32, 3/*#Ops*/, 1, 0, 2,
68123 MVT::f32, 3/*#Ops*/, 0, 1, 2,
68129 MVT::f32, 3/*#Ops*/, 1, 0, 2,
69079 /*145781*/ OPC_CheckType, MVT::f32,
69084 MVT::f32, 7/*#Ops*/, 1, 0, 4, 5, 6, 7, 8,
69098 /*145817*/ OPC_CheckType, MVT::f32,
69103 MVT::f32, 7/*#Ops*/, 3, 0, 4, 5, 6, 7, 8,
69119 /*145855*/ OPC_CheckType, MVT::f32,
69124 MVT::f32, 7/*#Ops*/, 2, 3, 4, 5, 6, 7, 8,
69201 /*146008*/ OPC_CheckType, MVT::f32,
69206 MVT::f32, 7/*#Ops*/, 0, 1, 4, 5, 6, 7, 8,
69220 /*146044*/ OPC_CheckType, MVT::f32,
69225 MVT::f32, 7/*#Ops*/, 0, 4, 5, 6, 7, 8, 3,
69277 /*146152*/ OPC_CheckType, MVT::f32,
69282 MVT::f32, 7/*#Ops*/, 1, 0, 4, 5, 6, 7, 8,
69296 /*146188*/ OPC_CheckType, MVT::f32,
69301 MVT::f32, 7/*#Ops*/, 3, 0, 4, 5, 6, 7, 8,
69317 /*146226*/ OPC_CheckType, MVT::f32,
69322 MVT::f32, 7/*#Ops*/, 2, 3, 4, 5, 6, 7, 8,
69396 /*146384*/ /*SwitchType*/ 19, MVT::f32,// ->146405
69401 MVT::f32, 7/*#Ops*/, 2, 4, 5, 6, 7, 8, 3,
69411 /*146415*/ OPC_SwitchType /*2 cases */, 38, MVT::f32,// ->146456
69415 MVT::f32, 3/*#Ops*/, 1, 0, 2,
69421 MVT::f32, 3/*#Ops*/, 0, 1, 2,
69427 MVT::f32, 3/*#Ops*/, 1, 0, 2,
70374 /*148440*/ OPC_SwitchType /*2 cases */, 70, MVT::f32,// ->148513
70380 MVT::f32, 5/*#Ops*/, 2, 3, 4, 5, 6,
70388 MVT::f32, 0/*#Ops*/, // Results = #7
70390 MVT::f32, 6/*#Ops*/, 7, 2, 3, 4, 5, 6,
70398 MVT::f32, 0/*#Ops*/, // Results = #7
70400 MVT::f32, 6/*#Ops*/, 7, 2, 3, 4, 5, 6,
70438 /*148592*/ OPC_SwitchType /*2 cases */, 70, MVT::f32,// ->148665
70444 MVT::f32, 5/*#Ops*/, 2, 3, 4, 5, 6,
70452 MVT::f32, 0/*#Ops*/, // Results = #7
70454 MVT::f32, 6/*#Ops*/, 7, 2, 3, 4, 5, 6,
70462 MVT::f32, 0/*#Ops*/, // Results = #7
70464 MVT::f32, 6/*#Ops*/, 7, 2, 3, 4, 5, 6,
70504 /*148746*/ OPC_SwitchType /*2 cases */, 46, MVT::f32,// ->148795
70508 MVT::f32, 1/*#Ops*/, 0,
70514 MVT::f32, 0/*#Ops*/, // Results = #1
70516 MVT::f32, 2/*#Ops*/, 1, 0,
70522 MVT::f32, 0/*#Ops*/, // Results = #1
70524 MVT::f32, 2/*#Ops*/, 1, 0,
70555 /*148847*/ OPC_SwitchType /*2 cases */, 46, MVT::f32,// ->148896
70559 MVT::f32, 1/*#Ops*/, 0,
70565 MVT::f32, 0/*#Ops*/, // Results = #1
70567 MVT::f32, 2/*#Ops*/, 1, 0,
70573 MVT::f32, 0/*#Ops*/, // Results = #1
70575 MVT::f32, 2/*#Ops*/, 1, 0,
71030 /*149841*/ OPC_CheckType, MVT::f32,
71035 MVT::f32, 5/*#Ops*/, 2, 3, 4, 5, 6,
71042 /*149866*/ OPC_CheckType, MVT::f32,
71047 MVT::f32, 2/*#Ops*/, 0, 1,
71053 MVT::f32, 1/*#Ops*/, 0,
71059 MVT::f32, 0/*#Ops*/, // Results = #1
71061 MVT::f32, 2/*#Ops*/, 1, 0,
71067 MVT::f32, 0/*#Ops*/, // Results = #1
71069 MVT::f32, 2/*#Ops*/, 1, 0,
71075 /*149931*/ OPC_SwitchType /*2 cases */, 13, MVT::f32,// ->149947
71079 MVT::f32, 2/*#Ops*/, 0, 1,
71250 /*150288*/ OPC_CheckChild0Type, MVT::f32,
71328 /*150433*/ OPC_SwitchType /*2 cases */, 59, MVT::f32,// ->150495
71334 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
71342 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
71350 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
71383 /*150559*/ OPC_SwitchType /*2 cases */, 35, MVT::f32,// ->150597
71387 MVT::f32, 2/*#Ops*/, 0, 1,
71393 MVT::f32, 2/*#Ops*/, 0, 1,
71399 MVT::f32, 2/*#Ops*/, 0, 1,
71705 /*151235*/ OPC_SwitchType /*2 cases */, 59, MVT::f32,// ->151297
71711 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
71719 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
71727 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
71760 /*151361*/ OPC_SwitchType /*2 cases */, 35, MVT::f32,// ->151399
71764 MVT::f32, 2/*#Ops*/, 0, 1,
71770 MVT::f32, 2/*#Ops*/, 0, 1,
71776 MVT::f32, 2/*#Ops*/, 0, 1,
72082 /*152037*/ OPC_SwitchType /*2 cases */, 59, MVT::f32,// ->152099
72088 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
72096 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
72104 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
72146 /*152177*/ OPC_SwitchType /*2 cases */, 59, MVT::f32,// ->152239
72152 MVT::f32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
72160 MVT::f32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
72168 MVT::f32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
72203 /*152307*/ OPC_SwitchType /*2 cases */, 35, MVT::f32,// ->152345
72207 MVT::f32, 2/*#Ops*/, 0, 1,
72213 MVT::f32, 2/*#Ops*/, 0, 1,
72219 MVT::f32, 2/*#Ops*/, 0, 1,
72719 /*153415*/ OPC_SwitchType /*2 cases */, 59, MVT::f32,// ->153477
72725 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
72733 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
72741 MVT::f32, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
72783 /*153555*/ OPC_SwitchType /*2 cases */, 59, MVT::f32,// ->153617
72789 MVT::f32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
72797 MVT::f32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
72805 MVT::f32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
72840 /*153685*/ OPC_SwitchType /*2 cases */, 35, MVT::f32,// ->153723
72844 MVT::f32, 2/*#Ops*/, 0, 1,
72850 MVT::f32, 2/*#Ops*/, 0, 1,
72856 MVT::f32, 2/*#Ops*/, 0, 1,
73354 /*154791*/ OPC_SwitchType /*2 cases */, 70, MVT::f32,// ->154864
73360 MVT::f32, 5/*#Ops*/, 2, 3, 4, 5, 6,
73368 MVT::f32, 0/*#Ops*/, // Results = #7
73370 MVT::f32, 6/*#Ops*/, 7, 2, 3, 4, 5, 6,
73378 MVT::f32, 0/*#Ops*/, // Results = #7
73380 MVT::f32, 6/*#Ops*/, 7, 2, 3, 4, 5, 6,
73417 /*154940*/ OPC_SwitchType /*3 cases */, 57, MVT::f32,// ->155000
73421 MVT::f32, MVT::i16, 1/*#Ops*/, 0,
73427 MVT::f32, 1/*#Ops*/, 0,
73433 MVT::f32, 0/*#Ops*/, // Results = #1
73435 MVT::f32, 2/*#Ops*/, 1, 0,
73441 MVT::f32, 0/*#Ops*/, // Results = #1
73443 MVT::f32, 2/*#Ops*/, 1, 0,
73765 /*155641*/ OPC_CheckType, MVT::f32,
73771 MVT::f32, 5/*#Ops*/, 2, 3, 4, 5, 6,
73779 MVT::f32, 0/*#Ops*/, // Results = #7
73781 MVT::f32, 6/*#Ops*/, 7, 2, 3, 4, 5, 6,
73787 /*155690*/ OPC_CheckType, MVT::f32,
73791 MVT::f32, 1/*#Ops*/, 0,
73797 MVT::f32, 0/*#Ops*/, // Results = #1
73799 MVT::f32, 2/*#Ops*/, 1, 0,
73876 /*155858*/ OPC_CheckType, MVT::f32,
73882 MVT::f32, 5/*#Ops*/, 2, 3, 4, 5, 6,
73890 MVT::f32, 0/*#Ops*/, // Results = #7
73892 MVT::f32, 6/*#Ops*/, 7, 2, 3, 4, 5, 6,
73898 /*155907*/ OPC_CheckType, MVT::f32,
73902 MVT::f32, 1/*#Ops*/, 0,
73908 MVT::f32, 0/*#Ops*/, // Results = #1
73910 MVT::f32, 2/*#Ops*/, 1, 0,
74459 /*156979*/ OPC_SwitchType /*2 cases */, 24, MVT::f32,// ->157006
74464 MVT::f32, 0/*#Ops*/, // Results = #7
74466 MVT::f32, 6/*#Ops*/, 7, 2, 3, 4, 5, 6,
74483 /*157038*/ OPC_SwitchType /*2 cases */, 24, MVT::f32,// ->157065
74488 MVT::f32, 0/*#Ops*/, // Results = #7
74490 MVT::f32, 6/*#Ops*/, 7, 2, 3, 4, 5, 6,
74509 /*157099*/ OPC_SwitchType /*2 cases */, 16, MVT::f32,// ->157118
74512 MVT::f32, 0/*#Ops*/, // Results = #1
74514 MVT::f32, 2/*#Ops*/, 1, 0,
74528 /*157140*/ OPC_SwitchType /*2 cases */, 16, MVT::f32,// ->157159
74531 MVT::f32, 0/*#Ops*/, // Results = #1
74533 MVT::f32, 2/*#Ops*/, 1, 0,
74939 /*158049*/ OPC_SwitchType /*3 cases */, 65, MVT::f32,// ->158117
74946 MVT::f32, MVT::i16, 5/*#Ops*/, 2, 3, 4, 5, 6,
74955 MVT::f32, MVT::i16, 5/*#Ops*/, 2, 3, 4, 5, 6,
74964 MVT::f32, MVT::i16, 5/*#Ops*/, 2, 3, 4, 5, 6,
75028 /*158252*/ OPC_SwitchType /*3 cases */, 18, MVT::f32,// ->158273
75033 MVT::f32, MVT::i16, 5/*#Ops*/, 2, 3, 4, 5, 6,
75081 /*158372*/ OPC_SwitchType /*4 cases */, 12, MVT::f32,// ->158387
75084 MVT::f32, 4/*#Ops*/, 1, 0, 2, 3,
75114 /*158442*/ OPC_SwitchType /*4 cases */, 12, MVT::f32,// ->158457
75117 MVT::f32, 4/*#Ops*/, 1, 0, 2, 3,
75147 /*158512*/ OPC_SwitchType /*4 cases */, 12, MVT::f32,// ->158527
75150 MVT::f32, 4/*#Ops*/, 1, 0, 2, 3,
75180 /*158582*/ OPC_SwitchType /*4 cases */, 12, MVT::f32,// ->158597
75183 MVT::f32, 4/*#Ops*/, 1, 0, 2, 3,
75210 /*158651*/ OPC_CheckChild0Type, MVT::f32,
75213 /*158656*/ OPC_CheckType, MVT::f32,
75226 MVT::f32, 2/*#Ops*/, 5, 6,
75241 MVT::f32, 2/*#Ops*/, 5, 6,
75248 /*158750*/ OPC_CheckType, MVT::f32,
75260 MVT::f32, 2/*#Ops*/, 4, 5,
75274 MVT::f32, 2/*#Ops*/, 4, 5,
75280 /*158837*/ OPC_SwitchType /*4 cases */, 89, MVT::f32,// ->158929
75285 MVT::f32, MVT::i16, 0/*#Ops*/,
75292 MVT::f32, MVT::i16, 0/*#Ops*/,
75300 MVT::f32, 0/*#Ops*/,
75306 MVT::f32, 0/*#Ops*/,
75314 MVT::f32, MVT::i16, 0/*#Ops*/, // Results = #0 #1
75316 MVT::f32, MVT::i16, 1/*#Ops*/, 0,
75323 MVT::f32, MVT::i16, 0/*#Ops*/, // Results = #0 #1
75325 MVT::f32, MVT::i16, 1/*#Ops*/, 0,
75426 /*159109*/ OPC_SwitchType /*3 cases */, 10, MVT::f32,// ->159122
75429 MVT::f32, MVT::i16, 1/*#Ops*/, 0,
75446 /*159149*/ OPC_SwitchType /*3 cases */, 10, MVT::f32,// ->159162
75449 MVT::f32, MVT::i16, 1/*#Ops*/, 0,
75466 /*159189*/ OPC_SwitchType /*3 cases */, 10, MVT::f32,// ->159202
75469 MVT::f32, MVT::i16, 1/*#Ops*/, 0,
75486 /*159229*/ OPC_SwitchType /*3 cases */, 10, MVT::f32,// ->159242
75489 MVT::f32, MVT::i16, 1/*#Ops*/, 0,
141540 /*290225*/ OPC_CheckChild0Type, MVT::f32,
143443 /*293819*/ OPC_CheckChild0Type, MVT::f32,
156618 /*318885*/ OPC_CheckChild0Type, MVT::f32,
157895 /*321213*/ OPC_CheckChild0Type, MVT::f32,
174556 /*354202*/ OPC_CheckChild0Type, MVT::f32,
175890 /*356735*/ OPC_CheckChild0Type, MVT::f32,
200229 /*405047*/ OPC_CheckChild0Type, MVT::f32,
200590 /*405859*/ OPC_CheckChild0Type, MVT::f32,
200661 /*405993*/ /*SwitchType*/ 32, MVT::f32,// ->406027
200725 /*406125*/ OPC_CheckChild0Type, MVT::f32,
232129 /*473365*/ OPC_CheckType, MVT::f32,
232164 /*473436*/ OPC_CheckType, MVT::f32,
232199 /*473505*/ OPC_CheckType, MVT::f32,
232234 /*473578*/ OPC_CheckType, MVT::f32,
232268 /*473649*/ OPC_CheckType, MVT::f32,
232294 /*473705*/ OPC_CheckType, MVT::f32,
232330 /*473774*/ OPC_CheckType, MVT::f32,
232364 /*473843*/ OPC_CheckType, MVT::f32,
232398 /*473912*/ OPC_CheckType, MVT::f32,
232432 /*473981*/ OPC_CheckType, MVT::f32,
232469 /*474056*/ OPC_CheckType, MVT::f32,
232504 /*474127*/ OPC_CheckType, MVT::f32,
232539 /*474196*/ OPC_CheckType, MVT::f32,
232574 /*474269*/ OPC_CheckType, MVT::f32,
232608 /*474340*/ OPC_CheckType, MVT::f32,
232634 /*474396*/ OPC_CheckType, MVT::f32,
232670 /*474465*/ OPC_CheckType, MVT::f32,
232704 /*474534*/ OPC_CheckType, MVT::f32,
232738 /*474603*/ OPC_CheckType, MVT::f32,
232772 /*474672*/ OPC_CheckType, MVT::f32,
232809 /*474747*/ OPC_CheckType, MVT::f32,
232844 /*474818*/ OPC_CheckType, MVT::f32,
232879 /*474887*/ OPC_CheckType, MVT::f32,
232914 /*474960*/ OPC_CheckType, MVT::f32,
232948 /*475031*/ OPC_CheckType, MVT::f32,
232974 /*475087*/ OPC_CheckType, MVT::f32,
233010 /*475156*/ OPC_CheckType, MVT::f32,
233044 /*475225*/ OPC_CheckType, MVT::f32,
233078 /*475294*/ OPC_CheckType, MVT::f32,
233112 /*475363*/ OPC_CheckType, MVT::f32,
233149 /*475438*/ OPC_CheckType, MVT::f32,
233184 /*475509*/ OPC_CheckType, MVT::f32,
233219 /*475578*/ OPC_CheckType, MVT::f32,
233254 /*475651*/ OPC_CheckType, MVT::f32,
233288 /*475722*/ OPC_CheckType, MVT::f32,
233314 /*475778*/ OPC_CheckType, MVT::f32,
233350 /*475847*/ OPC_CheckType, MVT::f32,
233384 /*475916*/ OPC_CheckType, MVT::f32,
233418 /*475985*/ OPC_CheckType, MVT::f32,
233452 /*476054*/ OPC_CheckType, MVT::f32,
233487 /*476127*/ OPC_CheckType, MVT::f32,
233499 /*476152*/ OPC_CheckType, MVT::f32,
233532 /*476219*/ OPC_CheckType, MVT::f32,
233544 /*476244*/ OPC_CheckType, MVT::f32,
233580 /*476316*/ OPC_CheckType, MVT::f32,
233592 /*476341*/ OPC_CheckType, MVT::f32,
233627 /*476414*/ OPC_CheckType, MVT::f32,
233639 /*476439*/ OPC_CheckType, MVT::f32,
233672 /*476506*/ OPC_CheckType, MVT::f32,
233684 /*476531*/ OPC_CheckType, MVT::f32,
233720 /*476603*/ OPC_CheckType, MVT::f32,
233732 /*476628*/ OPC_CheckType, MVT::f32,
233772 /*476706*/ OPC_CheckType, MVT::f32,
233806 /*476774*/ OPC_CheckType, MVT::f32,
233837 /*476840*/ OPC_CheckType, MVT::f32,
233870 /*476908*/ OPC_CheckType, MVT::f32,
233905 /*476984*/ OPC_CheckType, MVT::f32,
233936 /*477050*/ OPC_CheckType, MVT::f32,
233969 /*477118*/ OPC_CheckType, MVT::f32,
234004 /*477194*/ OPC_CheckType, MVT::f32,
234035 /*477260*/ OPC_CheckType, MVT::f32,
234068 /*477328*/ OPC_CheckType, MVT::f32,
234103 /*477404*/ OPC_CheckType, MVT::f32,
234134 /*477470*/ OPC_CheckType, MVT::f32,
234167 /*477538*/ OPC_CheckType, MVT::f32,
234206 /*477617*/ OPC_CheckType, MVT::f32,
234236 /*477677*/ OPC_CheckType, MVT::f32,
234263 /*477736*/ OPC_CheckType, MVT::f32,
234292 /*477797*/ OPC_CheckType, MVT::f32,
234323 /*477865*/ OPC_CheckType, MVT::f32,
234350 /*477924*/ OPC_CheckType, MVT::f32,
234379 /*477985*/ OPC_CheckType, MVT::f32,
234410 /*478053*/ OPC_CheckType, MVT::f32,
234437 /*478112*/ OPC_CheckType, MVT::f32,
234466 /*478173*/ OPC_CheckType, MVT::f32,
234497 /*478241*/ OPC_CheckType, MVT::f32,
234524 /*478300*/ OPC_CheckType, MVT::f32,
234553 /*478361*/ OPC_CheckType, MVT::f32,
234587 /*478434*/ OPC_CheckType, MVT::f32,
234617 /*478498*/ OPC_CheckType, MVT::f32,
234649 /*478564*/ OPC_CheckType, MVT::f32,
234683 /*478638*/ OPC_CheckType, MVT::f32,
234713 /*478702*/ OPC_CheckType, MVT::f32,
234745 /*478768*/ OPC_CheckType, MVT::f32,
234779 /*478842*/ OPC_CheckType, MVT::f32,
234809 /*478906*/ OPC_CheckType, MVT::f32,
234841 /*478972*/ OPC_CheckType, MVT::f32,
234875 /*479046*/ OPC_CheckType, MVT::f32,
234905 /*479110*/ OPC_CheckType, MVT::f32,
234937 /*479176*/ OPC_CheckType, MVT::f32,
234969 /*479245*/ OPC_CheckType, MVT::f32,
235010 /*479329*/ OPC_CheckType, MVT::f32,
235054 /*479418*/ OPC_CheckType, MVT::f32,
235097 /*479508*/ OPC_CheckType, MVT::f32,
235138 /*479592*/ OPC_CheckType, MVT::f32,
235182 /*479681*/ OPC_CheckType, MVT::f32,
235227 /*479773*/ OPC_CheckType, MVT::f32,
235256 /*479831*/ OPC_CheckType, MVT::f32,
235285 /*479890*/ OPC_CheckType, MVT::f32,
235311 /*479945*/ OPC_CheckType, MVT::f32,
235341 /*480004*/ OPC_CheckType, MVT::f32,
235370 /*480062*/ OPC_CheckType, MVT::f32,
235399 /*480122*/ OPC_CheckType, MVT::f32,
235440 /*480215*/ OPC_CheckType, MVT::f32,
235460 /*480260*/ OPC_CheckType, MVT::f32,
235480 /*480305*/ OPC_CheckType, MVT::f32,
235500 /*480350*/ OPC_CheckType, MVT::f32,
235533 /*480416*/ OPC_CheckType, MVT::f32,
235562 /*480474*/ OPC_CheckType, MVT::f32,
235591 /*480533*/ OPC_CheckType, MVT::f32,
235617 /*480588*/ OPC_CheckType, MVT::f32,
235647 /*480647*/ OPC_CheckType, MVT::f32,
235676 /*480705*/ OPC_CheckType, MVT::f32,
235705 /*480765*/ OPC_CheckType, MVT::f32,
235746 /*480858*/ OPC_CheckType, MVT::f32,
235766 /*480903*/ OPC_CheckType, MVT::f32,
235786 /*480948*/ OPC_CheckType, MVT::f32,
235806 /*480993*/ OPC_CheckType, MVT::f32,
235839 /*481059*/ OPC_CheckType, MVT::f32,
235868 /*481117*/ OPC_CheckType, MVT::f32,
235897 /*481176*/ OPC_CheckType, MVT::f32,
235923 /*481231*/ OPC_CheckType, MVT::f32,
235953 /*481290*/ OPC_CheckType, MVT::f32,
235982 /*481348*/ OPC_CheckType, MVT::f32,
236011 /*481408*/ OPC_CheckType, MVT::f32,
236052 /*481501*/ OPC_CheckType, MVT::f32,
236072 /*481546*/ OPC_CheckType, MVT::f32,
236092 /*481591*/ OPC_CheckType, MVT::f32,
236112 /*481636*/ OPC_CheckType, MVT::f32,
236145 /*481702*/ OPC_CheckType, MVT::f32,
236174 /*481760*/ OPC_CheckType, MVT::f32,
236203 /*481819*/ OPC_CheckType, MVT::f32,
236229 /*481874*/ OPC_CheckType, MVT::f32,
236259 /*481933*/ OPC_CheckType, MVT::f32,
236288 /*481991*/ OPC_CheckType, MVT::f32,
236317 /*482051*/ OPC_CheckType, MVT::f32,
236358 /*482144*/ OPC_CheckType, MVT::f32,
236378 /*482189*/ OPC_CheckType, MVT::f32,
236398 /*482234*/ OPC_CheckType, MVT::f32,
236418 /*482279*/ OPC_CheckType, MVT::f32,
236445 /*482336*/ OPC_CheckType, MVT::f32,
236476 /*482404*/ OPC_CheckType, MVT::f32,
236516 /*482487*/ OPC_CheckType, MVT::f32,
236529 /*482514*/ OPC_CheckType, MVT::f32,
236640 /*482736*/ OPC_CheckType, MVT::f32,
236663 /*482781*/ OPC_CheckType, MVT::f32,
236683 /*482820*/ OPC_CheckType, MVT::f32,
236706 /*482871*/ OPC_CheckType, MVT::f32,
236734 /*482933*/ OPC_CheckType, MVT::f32,
236747 /*482961*/ OPC_CheckType, MVT::f32,
236775 /*483024*/ OPC_CheckType, MVT::f32,
236798 /*483069*/ OPC_CheckType, MVT::f32,
236818 /*483108*/ OPC_CheckType, MVT::f32,
236841 /*483159*/ OPC_CheckType, MVT::f32,
236869 /*483221*/ OPC_CheckType, MVT::f32,
236882 /*483249*/ OPC_CheckType, MVT::f32,
236912 /*483315*/ OPC_CheckType, MVT::f32,
236938 /*483372*/ OPC_CheckType, MVT::f32,
236966 /*483431*/ OPC_CheckType, MVT::f32,
236996 /*483497*/ OPC_CheckType, MVT::f32,
237022 /*483554*/ OPC_CheckType, MVT::f32,
237050 /*483613*/ OPC_CheckType, MVT::f32,
237080 /*483679*/ OPC_CheckType, MVT::f32,
237106 /*483736*/ OPC_CheckType, MVT::f32,
237134 /*483795*/ OPC_CheckType, MVT::f32,
237164 /*483861*/ OPC_CheckType, MVT::f32,
237190 /*483918*/ OPC_CheckType, MVT::f32,
237218 /*483977*/ OPC_CheckType, MVT::f32,
237241 /*484028*/ OPC_CheckType, MVT::f32,
237253 /*484054*/ OPC_CheckType, MVT::f32,
237282 /*484117*/ OPC_CheckType, MVT::f32,
237307 /*484172*/ OPC_CheckType, MVT::f32,
237334 /*484229*/ OPC_CheckType, MVT::f32,
237363 /*484293*/ OPC_CheckType, MVT::f32,
237388 /*484348*/ OPC_CheckType, MVT::f32,
237415 /*484405*/ OPC_CheckType, MVT::f32,
237444 /*484469*/ OPC_CheckType, MVT::f32,
237469 /*484524*/ OPC_CheckType, MVT::f32,
237496 /*484581*/ OPC_CheckType, MVT::f32,
237525 /*484645*/ OPC_CheckType, MVT::f32,
237550 /*484700*/ OPC_CheckType, MVT::f32,
237577 /*484757*/ OPC_CheckType, MVT::f32,
237627 /*484859*/ OPC_CheckType, MVT::f32,
237657 /*484914*/ OPC_CheckType, MVT::f32,
237695 /*484997*/ OPC_CheckType, MVT::f32,
237734 /*485083*/ OPC_CheckType, MVT::f32,
237773 /*485171*/ OPC_CheckType, MVT::f32,
237811 /*485254*/ OPC_CheckType, MVT::f32,
237850 /*485340*/ OPC_CheckType, MVT::f32,
237891 /*485432*/ OPC_CheckType, MVT::f32,
237912 /*485480*/ OPC_CheckType, MVT::f32,
237933 /*485528*/ OPC_CheckType, MVT::f32,
237954 /*485576*/ OPC_CheckType, MVT::f32,
237977 /*485626*/ OPC_CheckType, MVT::f32,
238016 /*485721*/ OPC_CheckType, MVT::f32,
238037 /*485769*/ OPC_CheckType, MVT::f32,
238058 /*485817*/ OPC_CheckType, MVT::f32,
238079 /*485865*/ OPC_CheckType, MVT::f32,
238102 /*485915*/ OPC_CheckType, MVT::f32,
238141 /*486010*/ OPC_CheckType, MVT::f32,
238162 /*486058*/ OPC_CheckType, MVT::f32,
238183 /*486106*/ OPC_CheckType, MVT::f32,
238204 /*486154*/ OPC_CheckType, MVT::f32,
238227 /*486204*/ OPC_CheckType, MVT::f32,
238266 /*486299*/ OPC_CheckType, MVT::f32,
238287 /*486347*/ OPC_CheckType, MVT::f32,
238308 /*486395*/ OPC_CheckType, MVT::f32,
238329 /*486443*/ OPC_CheckType, MVT::f32,
238352 /*486493*/ OPC_CheckType, MVT::f32,
238383 /*486572*/ OPC_CheckType, MVT::f32,
238433 /*486660*/ OPC_CheckType, MVT::f32,
245182 /*500811*/ OPC_CheckType, MVT::f32,
253775 if (cast<MemSDNode>(N)->getMemoryVT() != MVT::f32) return false;
254185 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f32;
254304 if (cast<LoadSDNode>(N)->getMemoryVT().getScalarType() != MVT::f32) return false;
gen/lib/Target/X86/X86GenFastISel.inc 341 if (RetVT.SimpleTy != MVT::f32)
452 case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0, Op0IsKill);
845 if (RetVT.SimpleTy != MVT::f32)
870 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
880 if (RetVT.SimpleTy != MVT::f32)
905 case MVT::f32: return fastEmit_ISD_FCOS_MVT_f32_r(RetVT, Op0, Op0IsKill);
915 if (RetVT.SimpleTy != MVT::f32)
940 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
981 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill);
991 if (RetVT.SimpleTy != MVT::f32)
1110 case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
1165 case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
1174 if (RetVT.SimpleTy != MVT::f32)
1199 case MVT::f32: return fastEmit_ISD_FSIN_MVT_f32_r(RetVT, Op0, Op0IsKill);
1209 if (RetVT.SimpleTy != MVT::f32)
1312 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
1820 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill);
1842 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(Op0, Op0IsKill);
4040 if (RetVT.SimpleTy != MVT::f32)
4071 case MVT::f32: return fastEmit_X86ISD_FRCP_MVT_f32_r(RetVT, Op0, Op0IsKill);
4081 if (RetVT.SimpleTy != MVT::f32)
4112 case MVT::f32: return fastEmit_X86ISD_FRSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
6426 if (RetVT.SimpleTy != MVT::f32)
6541 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
6557 if (RetVT.SimpleTy != MVT::f32)
6672 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
6688 if (RetVT.SimpleTy != MVT::f32)
6803 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
6819 if (RetVT.SimpleTy != MVT::f32)
6934 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
9534 case MVT::f32: return fastEmit_X86ISD_CMP_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
9888 if (RetVT.SimpleTy != MVT::f32)
9991 case MVT::f32: return fastEmit_X86ISD_FMAX_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
10006 if (RetVT.SimpleTy != MVT::f32)
10109 case MVT::f32: return fastEmit_X86ISD_FMAXC_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
10220 if (RetVT.SimpleTy != MVT::f32)
10323 case MVT::f32: return fastEmit_X86ISD_FMIN_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
10338 if (RetVT.SimpleTy != MVT::f32)
10441 case MVT::f32: return fastEmit_X86ISD_FMINC_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/X86/X86GenRegisterInfo.inc 4476 /* 8 */ MVT::f80, MVT::f64, MVT::f32, MVT::Other,
include/llvm/CodeGen/SelectionDAG.h 1384 case MVT::f32: return APFloat::IEEEsingle();
include/llvm/Support/MachineValueType.h 535 case nxv16f32: return f32;
713 case f32 :
869 return MVT::f32;
972 case MVT::f32:
1047 case MVT::f32:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp12722 if ((VT == MVT::f32 && ExponentC->getValueAPF().isExactlyValue(1.0f/3.0f)) ||
16070 case MVT::f32:
20272 if (VT.getScalarType() != MVT::f32 && VT.getScalarType() != MVT::f64)
20411 if (VT.getScalarType() != MVT::f32 && VT.getScalarType() != MVT::f64)
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 302 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
314 while (SVT != MVT::f32 && SVT != MVT::f16) {
439 if (CFP->getValueType(0) == MVT::f32 &&
2129 case MVT::f32: LC = Call_F32; break;
2170 case MVT::f32: LC = Call_F32; break;
2251 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2285 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2436 if (DestVT == MVT::f32)
2438 MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2444 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
3133 if (Node->getValueType(0) != MVT::f32) {
3138 DAG.getNode(ISD::FP16_TO_FP, dl, MVT::f32, Node->getOperand(0));
3149 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) {
3152 SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
4035 if (Node->getValueType(0) == MVT::f32) {
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 36 VT == MVT::f32 ? Call_F32 :
484 if (FloatVT == MVT::f32 || FloatVT == MVT::f64 || FloatVT == MVT::f128) {
511 if (Op.getValueType() == MVT::f16 && N->getValueType(0) != MVT::f32) {
512 Op = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), MVT::f32, Op);
513 if (getTypeAction(MVT::f32) == TargetLowering::TypeSoftenFloat)
537 EVT MidVT = TLI.getTypeToTransformTo(*DAG.getContext(), MVT::f32);
544 if (N->getValueType(0) == MVT::f32)
548 RTLIB::Libcall LC = RTLIB::getFPEXT(MVT::f32, N->getValueType(0));
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 2591 if (VT == MVT::f32)
2619 if (VT == MVT::f32)
4043 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 1341 if (EltVT == MVT::f32)
4313 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32)
4404 else if (VT == MVT::i32 && C->getValueType(0) == MVT::f32)
5676 else if (VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
5680 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 4869 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
4886 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
4893 MVT::f32);
4904 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4905 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4922 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4924 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4926 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4927 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4938 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4940 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4942 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4943 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4945 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4946 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4959 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4961 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4963 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4964 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4966 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4967 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4969 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4970 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4972 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4973 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4975 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4976 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4982 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4990 if (Op.getValueType() == MVT::f32 &&
4999 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
5000 DAG.getConstantFP(numbers::log2ef, dl, MVT::f32));
5014 if (Op.getValueType() == MVT::f32 &&
5021 DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
5022 DAG.getConstantFP(numbers::ln2f, dl, MVT::f32));
5037 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5039 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5041 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5042 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5054 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5056 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5058 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5059 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5061 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5062 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5064 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5065 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
5079 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5081 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5083 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5084 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5086 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5087 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5089 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5090 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
5092 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
5093 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
5095 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
5096 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
5100 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
5113 if (Op.getValueType() == MVT::f32 &&
5133 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5135 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5137 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5138 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5150 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5152 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5154 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5155 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5157 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5158 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5160 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5161 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
5176 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5178 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5180 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5181 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5183 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5184 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5186 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5187 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
5189 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
5190 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
5192 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
5193 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
5197 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
5210 if (Op.getValueType() == MVT::f32 &&
5216 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
5232 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5234 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5236 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5237 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5248 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5250 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
5252 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5253 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
5255 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5256 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
5269 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5271 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
5273 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5274 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
5276 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5277 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
5279 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5280 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
5282 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
5283 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
5287 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
5298 if (Op.getValueType() == MVT::f32 &&
5311 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
5311 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
5326 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
lib/CodeGen/SelectionDAG/TargetLowering.cpp 280 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128)
289 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
295 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
301 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
307 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
313 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
319 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
324 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
329 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
335 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
338 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
343 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
346 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
355 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
360 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
365 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
370 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
5887 if (SrcVT != MVT::f32 || DstVT != MVT::i64)
6046 if (DstVT.getScalarType() == MVT::f32) {
lib/CodeGen/TargetLoweringBase.cpp 215 if (RetVT == MVT::f32)
217 } else if (OpVT == MVT::f32) {
241 if (OpVT == MVT::f32)
251 } else if (RetVT == MVT::f32) {
278 if (OpVT == MVT::f32) {
320 if (OpVT == MVT::f32) {
363 if (RetVT == MVT::f32)
374 if (RetVT == MVT::f32)
385 if (RetVT == MVT::f32)
403 if (RetVT == MVT::f32)
414 if (RetVT == MVT::f32)
425 if (RetVT == MVT::f32)
759 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
765 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
1242 if (!isTypeLegal(MVT::f32)) {
1243 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1244 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1245 TransformToType[MVT::f32] = MVT::i32;
1246 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1253 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1254 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1255 TransformToType[MVT::f16] = MVT::f32;
1841 assert(VT.getScalarType() == MVT::f32 &&
lib/CodeGen/ValueTypes.cpp 130 case MVT::f32: return "f32";
277 case MVT::f32: return Type::getFloatTy(Context);
458 case Type::FloatTyID: return MVT(MVT::f32);
lib/Target/AArch64/AArch64CallingConvention.cpp 95 else if (LocVT.SimpleTy == MVT::f32 || LocVT.is32BitVector())
lib/Target/AArch64/AArch64FastISel.cpp 338 case MVT::f32:
403 if (VT != MVT::f32 && VT != MVT::f64)
556 if (VT != MVT::f32 && VT != MVT::f64)
1501 case MVT::f32:
1520 if (RetVT != MVT::f32 && RetVT != MVT::f64)
1885 case MVT::f32:
2159 case MVT::f32: Opc = OpcTable[Idx][4]; break;
2731 case MVT::f32:
2913 assert((DestVT == MVT::f32 || DestVT == MVT::f64) &&
2935 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri;
2937 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri;
2940 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri;
2942 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;
3037 } else if (VT == MVT::f32) {
3575 if (RetVT != MVT::f32 && RetVT != MVT::f64)
3628 case MVT::f32:
4849 if (RetVT == MVT::f32 && SrcVT == MVT::i32)
4853 else if (RetVT == MVT::i32 && SrcVT == MVT::f32)
4865 case MVT::f32: RC = &AArch64::FPR32RegClass; break;
4890 case MVT::f32:
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 1207 } else if (VT == MVT::f32) {
lib/Target/AArch64/AArch64ISelLowering.cpp 139 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
197 setOperationAction(ISD::SETCC, MVT::f32, Custom);
205 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
210 setOperationAction(ISD::SELECT, MVT::f32, Custom);
215 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
224 setOperationAction(ISD::FREM, MVT::f32, Expand);
273 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
349 setOperationAction(ISD::FSIN, MVT::f32, Expand);
351 setOperationAction(ISD::FCOS, MVT::f32, Expand);
353 setOperationAction(ISD::FPOW, MVT::f32, Expand);
356 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
473 for (MVT Ty : {MVT::f32, MVT::f64}) {
522 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
525 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
531 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
539 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
546 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
547 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
551 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
565 setIndexedLoadAction(im, MVT::f32, Legal);
572 setIndexedStoreAction(im, MVT::f32, Legal);
1611 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS);
1612 RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS);
1613 VT = MVT::f32;
1712 LHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, LHS);
1713 RHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, RHS);
2446 MVT NewVT = MVT::getVectorVT(MVT::f32, NumElts);
2485 DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Op.getOperand(0)));
2543 DAG.getNode(Op.getOpcode(), dl, MVT::f32, Op.getOperand(0)),
2607 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
3213 else if (RegVT == MVT::f32)
4791 assert(LHS.getValueType() == MVT::f16 || LHS.getValueType() == MVT::f32 ||
4841 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
4877 if (VT == MVT::f32)
4983 assert(LHS.getValueType() == MVT::f16 || LHS.getValueType() == MVT::f32 ||
5035 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS);
5036 RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS);
5160 assert(LHS.getValueType() == MVT::f16 || LHS.getValueType() == MVT::f32 ||
5717 else if (VT == MVT::f32)
5727 if (!IsLegal && (VT == MVT::f64 || VT == MVT::f32)) {
5755 VT == MVT::f32 || VT == MVT::v1f32 ||
6790 VT.getVectorElementType() == MVT::f32)
6809 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
6916 if (EltType == MVT::i32 || EltType == MVT::f32)
7101 case MVT::f32:
7718 assert ((EltTy == MVT::f16 || EltTy == MVT::f32 || EltTy == MVT::f64) &&
9195 case MVT::f32:
9529 if (VT != MVT::f32 && VT != MVT::f64)
11936 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
lib/Target/AArch64/AArch64ISelLowering.h 532 return VT == MVT::f32 || VT == MVT::f64;
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 1101 assert(VT == MVT::f32 || VT == MVT::f64);
1117 assert(VT == MVT::f32 || VT == MVT::f64);
2087 if (VT != MVT::f32 || (!Subtarget->hasMadMixInsts() &&
2124 MVT::f32, Ops);
2415 if (In.getValueType() == MVT::f32)
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 70 setOperationAction(ISD::LOAD, MVT::f32, Promote);
71 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
152 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
160 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
170 setOperationAction(ISD::STORE, MVT::f32, Promote);
171 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
216 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
225 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
239 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
250 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
251 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
252 setOperationAction(ISD::FPOW, MVT::f32, Legal);
253 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
254 setOperationAction(ISD::FABS, MVT::f32, Legal);
255 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
256 setOperationAction(ISD::FRINT, MVT::f32, Legal);
257 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
258 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
259 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
261 setOperationAction(ISD::FROUND, MVT::f32, Custom);
264 setOperationAction(ISD::FLOG, MVT::f32, Custom);
265 setOperationAction(ISD::FLOG10, MVT::f32, Custom);
266 setOperationAction(ISD::FEXP, MVT::f32, Custom);
269 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
272 setOperationAction(ISD::FREM, MVT::f32, Custom);
303 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom);
628 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64 ||
635 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
747 return VT == MVT::f32 || VT == MVT::f64 ||
753 return VT == MVT::f32 || VT == MVT::f64 ||
1533 MVT FltVT = MVT::f32;
1674 SDValue Cvt_Lo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Lo);
1675 SDValue Cvt_Hi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Hi);
1676 SDValue Mad1 = DAG.getNode(FMAD, DL, MVT::f32, Cvt_Hi,
1677 DAG.getConstantFP(APInt(32, 0x4f800000).bitsToFloat(), DL, MVT::f32),
1679 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, DL, MVT::f32, Mad1);
1680 SDValue Mul1 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Rcp,
1681 DAG.getConstantFP(APInt(32, 0x5f7ffffc).bitsToFloat(), DL, MVT::f32));
1682 SDValue Mul2 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Mul1,
1683 DAG.getConstantFP(APInt(32, 0x2f800000).bitsToFloat(), DL, MVT::f32));
1684 SDValue Trunc = DAG.getNode(ISD::FTRUNC, DL, MVT::f32, Mul2);
1685 SDValue Mad2 = DAG.getNode(FMAD, DL, MVT::f32, Trunc,
1686 DAG.getConstantFP(APInt(32, 0xcf800000).bitsToFloat(), DL, MVT::f32),
2250 if (VT == MVT::f32 || VT == MVT::f16)
2424 *DAG.getContext(), MVT::f32);
2465 R = DAG.getNode(ISD::BITCAST, SL, MVT::f32, R);
2470 SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R);
2471 return DAG.getSelect(SL, MVT::f32, DAG.getSExtOrTrunc(S, SL, SetCCVT), RNeg, R);
2509 SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src);
2517 if (DestVT == MVT::f32)
2536 SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src);
2544 if (DestVT == MVT::f32)
2585 if (N0.getValueType() == MVT::f32)
2689 SDValue FPExtend = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);
2712 SDValue FPExtend = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);
3575 if (VT == MVT::f32 && Subtarget->hasFminFmaxLegacy()) {
4361 if (VT == MVT::f32) {
4377 if (VT == MVT::f32) {
lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp 397 if (SLT == MVT::f32 || SLT == MVT::f16)
415 if ((SLT == MVT::f32 && !ST->hasFP32Denormals()) ||
431 if (SLT == MVT::f32 || SLT == MVT::f16) {
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp 267 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f32);
400 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f32);
427 return isSCSrcB32() || isLiteralImm(MVT::f32) || isExpr();
465 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f32);
497 return isVCSrcF32() || isLiteralImm(MVT::f32) || isExpr();
525 return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::f32);
549 return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f32);
573 return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f32);
597 return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f32);
621 return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f32);
633 return isLiteralImm(MVT::f32);
1654 return isSDWAOperand(MVT::f32);
lib/Target/AMDGPU/R600ISelLowering.cpp 58 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass);
122 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
123 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
124 setCondCodeAction(ISD::SETLT, MVT::f32, Expand);
125 setCondCodeAction(ISD::SETLE, MVT::f32, Expand);
126 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
127 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
128 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
129 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
130 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
131 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
132 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
133 setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
140 setOperationAction(ISD::FCOS, MVT::f32, Custom);
141 setOperationAction(ISD::FSIN, MVT::f32, Custom);
147 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
150 setOperationAction(ISD::FSUB, MVT::f32, Expand);
157 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
161 setOperationAction(ISD::SETCC, MVT::f32, Expand);
168 setOperationAction(ISD::SELECT, MVT::f32, Expand);
222 setOperationAction(ISD::FMA, MVT::f32, Expand);
229 setOperationAction(ISD::FMAD, MVT::f32, Legal);
233 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
571 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
573 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
575 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
577 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
579 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
581 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
583 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
585 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
588 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args);
766 DAG.getConstantFP(0.15915494309, DL, MVT::f32)),
767 DAG.getConstantFP(0.5, DL, MVT::f32)));
781 DAG.getConstantFP(-0.5, DL, MVT::f32)));
786 DAG.getConstantFP(numbers::pif, DL, MVT::f32));
887 Op, DAG.getConstantFP(1.0f, DL, MVT::f32),
897 Op, DAG.getConstantFP(-1.0f, DL, MVT::f32),
951 if (VT == MVT::f32) {
1061 if (CompareVT == MVT::f32) {
1709 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1712 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1879 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
1880 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
2153 Src = DAG.getRegister(R600::ALU_CONST, MVT::f32);
lib/Target/AMDGPU/SIISelLowering.cpp 121 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
202 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
229 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
368 setOperationAction(ISD::FMAD, MVT::f32, Legal);
372 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
399 setOperationAction(ISD::FMINNUM, MVT::f32, Custom);
400 setOperationAction(ISD::FMAXNUM, MVT::f32, Custom);
408 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal);
409 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal);
427 setOperationAction(ISD::FSIN, MVT::f32, Custom);
428 setOperationAction(ISD::FCOS, MVT::f32, Custom);
429 setOperationAction(ISD::FDIV, MVT::f32, Custom);
674 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
768 DestVT.getScalarType() == MVT::f32 && !Subtarget->hasFP32Denormals() &&
3920 case MVT::f32: {
4234 Src0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0);
4235 Src1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1);
5160 Type = MVT::f32;
5180 if (Elt.getValueType() != MVT::f32)
5181 Elt = DAG.getBitcast(MVT::f32, Elt);
5185 VecElts[i] = DAG.getUNDEF(MVT::f32);
5541 EVT::getVectorVT(*DAG.getContext(), MVT::f32, NumVDataDwords)
5542 : MVT::f32;
5666 LoadVT.getScalarType() == MVT::f32) &&
5880 ISD::INTRINSIC_WO_CHAIN, DL, MVT::f32,
5898 return DAG.getNode(AMDGPUISD::INTERP_P1LV_F16, DL, MVT::f32, Ops);
5911 return DAG.getNode(AMDGPUISD::INTERP_P1LL_F16, DL, MVT::f32, Ops);
6804 SDValue Undef = DAG.getUNDEF(MVT::f32);
6809 DAG.getNode(ISD::BITCAST, DL, MVT::f32, Src0),
6810 DAG.getNode(ISD::BITCAST, DL, MVT::f32, Src1),
7525 if (!Unsafe && VT == MVT::f32 && Subtarget->hasFP32Denormals())
7529 if (Unsafe || VT == MVT::f32 || VT == MVT::f16) {
7617 SDValue CvtSrc0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0);
7618 SDValue CvtSrc1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1);
7620 SDValue RcpSrc1 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, CvtSrc1);
7621 SDValue Quot = DAG.getNode(ISD::FMUL, SL, MVT::f32, CvtSrc0, RcpSrc1);
7635 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
7638 const SDValue K0 = DAG.getConstantFP(K0Val, SL, MVT::f32);
7641 const SDValue K1 = DAG.getConstantFP(K1Val, SL, MVT::f32);
7643 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
7646 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
7650 SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One);
7653 r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3);
7656 SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1);
7658 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
7660 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
7684 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
7686 SDVTList ScaleVT = DAG.getVTList(MVT::f32, MVT::i1);
7694 SDValue ApproxRcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32,
7696 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f32,
7731 SDValue Fma0 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0,
7734 SDValue Fma1 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, Fma0, ApproxRcp,
7737 SDValue Mul = getFPBinOp(DAG, ISD::FMUL, SL, MVT::f32, NumeratorScaled,
7740 SDValue Fma2 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, Mul,
7743 SDValue Fma3 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, Fma2, Fma1, Mul, Fma2);
7745 SDValue Fma4 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, Fma3,
7773 SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f32,
7776 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f32, Fmas, RHS, LHS);
7849 if (VT == MVT::f32)
8007 if (ScalarVT != MVT::f32)
8704 if (VT == MVT::f32 && (N0.getOpcode() == ISD::UINT_TO_FP ||
9092 if (VT == MVT::f32 || (VT == MVT::f16 && Subtarget->hasMed3_16())) {
9129 (VT == MVT::i32 || VT == MVT::f32 ||
9173 (VT == MVT::f32 || VT == MVT::f64 ||
9413 if (((VT == MVT::f32 && !Subtarget->hasFP32Denormals()) ||
9700 if (!Subtarget->hasDot2Insts() || VT != MVT::f32)
9762 return DAG.getNode(AMDGPUISD::FDOT2, SL, MVT::f32, Vec1, Vec2, FMAAcc,
9833 if (VT != MVT::f32 && VT != MVT::f64 && (Subtarget->has16BitInsts() &&
9890 MVT::f32, Srl);
10882 case MVT::f32:
lib/Target/ARM/ARMCallingConv.cpp 214 case MVT::f32:
lib/Target/ARM/ARMFastISel.cpp 838 case MVT::f32:
876 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64)
971 case MVT::f32:
1010 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1110 case MVT::f32:
1386 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1397 case MVT::f32:
1566 unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
1602 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1928 case MVT::f32:
lib/Target/ARM/ARMISelDAGToDAG.cpp 3546 assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
lib/Target/ARM/ARMISelLowering.cpp 693 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
696 setAllExpand(MVT::f32);
725 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
966 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
976 setOperationAction(ISD::FP_EXTEND, MVT::f32, Custom);
979 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
985 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
990 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
991 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
1174 for (auto &VT : {MVT::f32, MVT::f64})
1273 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1276 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1279 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1293 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1299 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1300 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1303 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1305 setOperationAction(ISD::FREM, MVT::f32, Expand);
1309 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
1312 setOperationAction(ISD::FPOW, MVT::f32, Expand);
1316 setOperationAction(ISD::FMA, MVT::f32, Expand);
1329 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
1330 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
1338 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1343 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1344 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1345 setOperationAction(ISD::FROUND, MVT::f32, Legal);
1346 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1347 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1348 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1349 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1350 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1393 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);
1394 setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal);
1483 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
2765 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
4056 else if (RegVT == MVT::f32)
4870 if (VT == MVT::f32)
4998 TrueVal.getValueType() == MVT::f32 ||
5027 TrueVal.getValueType() == MVT::f32 ||
5066 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
5145 if (LHS.getValueType() == MVT::f32) {
5333 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
5384 if (VT.getVectorElementType() == MVT::f32)
5460 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
5467 if (SrcVT == MVT::f32) {
5473 } else if (VT == MVT::f32)
5489 if (VT == MVT::f32) {
5491 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
5510 if (VT == MVT::f32) {
5513 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
5668 if (SrcVT == MVT::f32 && DstVT == MVT::i32) {
5676 Op.getValueType() != MVT::f32)
6536 case MVT::f32:
6566 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
6597 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
6614 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
7244 assert(FVT == MVT::f32 || FVT == MVT::f16);
7245 MVT IVT = (FVT == MVT::f32) ? MVT::i32 : MVT::i16;
7637 VT.getVectorElementType() == MVT::f32)
9107 SDValue Callee = DAG.getExternalSymbol(Ty == MVT::f32 ? "powf" : "pow",
12702 assert(EltVT == MVT::f32 && "Unexpected type!");
14565 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
14909 case MVT::f32:
14967 case MVT::f32:
15696 if (VT == MVT::f32)
15706 if (VT == MVT::f32)
15716 if (VT == MVT::f32 || VT == MVT::i32)
16124 SrcVal = DAG.getNode(ISD::FP_EXTEND, Loc, MVT::f32, SrcVal);
16127 LC = RTLIB::getFPEXT(MVT::f16, MVT::f32);
16131 makeLibCall(DAG, LC, MVT::f32, SrcVal, CallOptions, Loc).first;
16141 LC = RTLIB::getFPEXT(MVT::f32, MVT::f64);
16230 if (VT == MVT::f32)
lib/Target/ARM/ARMTargetTransformInfo.cpp 297 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 },
298 { ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 },
301 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 },
302 { ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 },
305 { ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 },
306 { ISD::FP_TO_UINT, MVT::i16, MVT::f32, 2 },
309 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 2 },
310 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 2 },
313 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 10 },
314 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 10 },
327 { ISD::SINT_TO_FP, MVT::f32, MVT::i1, 2 },
328 { ISD::UINT_TO_FP, MVT::f32, MVT::i1, 2 },
331 { ISD::SINT_TO_FP, MVT::f32, MVT::i8, 2 },
332 { ISD::UINT_TO_FP, MVT::f32, MVT::i8, 2 },
335 { ISD::SINT_TO_FP, MVT::f32, MVT::i16, 2 },
336 { ISD::UINT_TO_FP, MVT::f32, MVT::i16, 2 },
339 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 2 },
340 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 2 },
343 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 10 },
344 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 10 },
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 95 case MVT::f32:
485 case MVT::f32:
702 if (N->getValueType(0) == MVT::f32) {
704 ReplaceNode(N, CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::f32, V));
lib/Target/Hexagon/HexagonISelLowering.cpp 555 VT == MVT::i64 || VT == MVT::f32 || VT == MVT::f64 ||
1277 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1292 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
1396 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1399 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1530 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1531 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1548 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64, MVT::f32, MVT::f64,
3008 case MVT::f32:
lib/Target/Hexagon/HexagonInstrInfo.cpp 1988 } else if (VT == MVT::i32 || VT == MVT::f32) {
2649 case MVT::f32:
lib/Target/Mips/MipsCallLowering.cpp 156 } else if (VT == MVT::f32 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
274 } else if (VT == MVT::f32 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
lib/Target/Mips/MipsFastISel.cpp 393 if (VT == MVT::f32) {
776 case MVT::f32:
829 case MVT::f32:
1003 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
1036 } else if (VT == MVT::f32) {
1082 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1118 if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1129 unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32;
1162 if (ArgVT == MVT::f32) {
1171 if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
1172 if (ArgVT == MVT::f32) {
1182 if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1419 case MVT::f32:
lib/Target/Mips/MipsISelLowering.cpp 324 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
335 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
338 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
353 setOperationAction(ISD::SELECT, MVT::f32, Custom);
356 setOperationAction(ISD::SETCC, MVT::f32, Custom);
359 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
364 setOperationAction(ISD::FABS, MVT::f32, Custom);
403 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
409 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
436 setOperationAction(ISD::FSIN, MVT::f32, Expand);
438 setOperationAction(ISD::FCOS, MVT::f32, Expand);
440 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
442 setOperationAction(ISD::FPOW, MVT::f32, Expand);
444 setOperationAction(ISD::FLOG, MVT::f32, Expand);
445 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
446 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
447 setOperationAction(ISD::FEXP, MVT::f32, Expand);
448 setOperationAction(ISD::FMA, MVT::f32, Expand);
450 setOperationAction(ISD::FREM, MVT::f32, Expand);
454 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
455 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
2214 SDValue X = (TyX == MVT::f32) ?
2218 SDValue Y = (TyY == MVT::f32) ?
2241 if (TyX == MVT::f32)
2315 SDValue X = (Op.getValueType() == MVT::f32)
2332 if (Op.getValueType() == MVT::f32)
2333 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
2807 } else if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2824 if (ValVT == MVT::f32) {
3157 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3536 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3928 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
3981 else if (VT == MVT::f32)
4153 if (VT != MVT::f32 && VT != MVT::f64)
lib/Target/Mips/MipsSEISelLowering.cpp 171 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
250 setOperationAction(ISD::SETCC, MVT::f32, Legal);
251 setOperationAction(ISD::SELECT, MVT::f32, Legal);
252 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
262 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
263 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand);
264 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
265 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp 829 case MVT::f32:
lib/Target/NVPTX/NVPTXISelLowering.cpp 379 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
396 for (MVT VT : {MVT::f16, MVT::v2f16, MVT::f32, MVT::f64, MVT::i1, MVT::i8,
449 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
451 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
460 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
462 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
476 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
551 setOperationAction(Op, MVT::f32, Legal);
558 setOperationAction(ISD::FROUND, MVT::f32, Custom);
565 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
574 setOperationAction(Op, MVT::f32, Legal);
1225 if (VT == MVT::f32)
1233 if (VT == MVT::f32)
2080 if (VT == MVT::f32)
4369 if (VT == MVT::f32 || VT == MVT::f64) {
lib/Target/PowerPC/PPCFastISel.cpp 472 (VT == MVT::f32 ? (HasSPE ? &PPC::GPRCRegClass : &PPC::F4RCRegClass) :
500 case MVT::f32:
649 case MVT::f32:
872 case MVT::f32:
963 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
981 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1070 if (DstVT != MVT::f32 && DstVT != MVT::f64)
1091 if (DstVT == MVT::f32)
1114 if (DstVT == MVT::f32 && !PPCSubTarget->hasFPCVT())
1136 if (DstVT == MVT::f32)
1208 if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1473 if (ArgVT == MVT::f32 || ArgVT == MVT::f64) {
1582 RetVT != MVT::i32 && RetVT != MVT::i64 && RetVT != MVT::f32 &&
1995 if (VT != MVT::f32 && VT != MVT::f64)
2005 RC = ((VT == MVT::f32) ? &PPC::GPRCRegClass : &PPC::SPERCRegClass);
2007 RC = ((VT == MVT::f32) ? &PPC::F4RCRegClass : &PPC::F8RCRegClass);
2014 MachineMemOperand::MOLoad, (VT == MVT::f32) ? 4 : 8, Align);
2019 Opc = ((VT == MVT::f32) ? PPC::SPELWZ : PPC::EVLDD);
2021 Opc = ((VT == MVT::f32) ? PPC::LFS : PPC::LFD);
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 3773 } else if (LHS.getValueType() == MVT::f32) {
4497 case MVT::f32: Opcode = PPC::LFSU; break;
4536 case MVT::f32: Opcode = PPC::LFSUX; break;
4899 else if (N->getValueType(0) == MVT::f32) {
lib/Target/PowerPC/PPCISelLowering.cpp 148 addRegisterClass(MVT::f32, &PPC::GPRCRegClass);
151 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
169 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
183 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
185 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
277 setOperationAction(ISD::FSIN , MVT::f32, Expand);
278 setOperationAction(ISD::FCOS , MVT::f32, Expand);
279 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
280 setOperationAction(ISD::FREM , MVT::f32, Expand);
281 setOperationAction(ISD::FPOW , MVT::f32, Expand);
284 setOperationAction(ISD::FMA , MVT::f32, Expand);
287 setOperationAction(ISD::FMA , MVT::f32, Legal);
301 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
305 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
308 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
317 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
318 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
319 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
320 setOperationAction(ISD::FROUND, MVT::f32, Legal);
355 setOperationAction(ISD::SELECT, MVT::f32, Expand);
360 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
388 setOperationAction(ISD::BITCAST, MVT::f32, Legal);
393 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
482 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
484 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
487 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
489 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
491 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
493 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
495 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
497 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
553 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal);
555 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal);
792 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
908 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal);
910 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
2178 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
3370 if (ArgVT == MVT::f32 || ArgVT == MVT::f64 ||
3492 case MVT::f32:
3931 case MVT::f32:
3939 if (ObjectVT == MVT::f32)
3962 if (ObjectVT == MVT::f32) {
4171 case MVT::f32:
4334 case MVT::f32:
4346 if (ObjectVT == MVT::f32)
5794 case MVT::f32:
6058 case MVT::f32:
6089 if (Arg.getValueType() != MVT::f32) {
6128 if (Arg.getValueType() == MVT::f32 &&
6146 ArgOffset += (Arg.getValueType() == MVT::f32 &&
6547 case MVT::f32:
6589 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
6759 case MVT::f32:
7274 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
7277 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
7287 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
7296 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
7310 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
7313 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
7320 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
7326 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
7332 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
7338 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
7350 if (Src.getValueType() == MVT::f32)
7414 if (Src.getValueType() == MVT::f32)
7604 assert((Op.getValueType() == MVT::f32 ||
7611 bool SinglePrec = Op.getValueType() == MVT::f32;
7620 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
7624 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
7733 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
7752 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
7757 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
7758 ? MVT::f32
7773 if (Op.getValueType() == MVT::f32 &&
7875 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
7877 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
7948 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
7949 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP,
11650 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
11671 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
12684 MVT::f32, In.getOperand(0),
13028 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
13057 return DAG.getNode(ConvOp, dl, DstDouble ? MVT::f64 : MVT::f32, Ext);
13059 return DAG.getNode(ConvOp, dl, DstDouble ? MVT::f64 : MVT::f32, Ld);
13075 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
13080 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
13081 ? MVT::f32
13090 if (Src.getValueType() == MVT::f32) {
13105 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
13107 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
13569 Bitcast->getValueType(0) != MVT::f32)
13572 Bitcast2->getValueType(0) != MVT::f32)
13592 SDValue FloatLoad = DAG.getLoad(MVT::f32, dl, LD->getChain(), BasePtr,
13599 MVT::f32, dl, SDValue(FloatLoad.getNode(), 1), AddPtr,
14326 if (VT == MVT::f32 || VT == MVT::i32)
14331 if (VT == MVT::f32 || VT == MVT::i32)
14360 if (VT == MVT::f32 && Subtarget.hasP8Vector())
14953 case MVT::f32:
15091 case MVT::f32:
15445 return VT == MVT::f32 || VT == MVT::f64 ||
lib/Target/PowerPC/PPCISelLowering.h 863 if (VT != MVT::f32 && VT != MVT::f64)
lib/Target/RISCV/RISCVISelLowering.cpp 71 addRegisterClass(MVT::f32, &RISCV::FPR32RegClass);
153 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
154 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
156 setCondCodeAction(CC, MVT::f32, Expand);
157 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
158 setOperationAction(ISD::SELECT, MVT::f32, Custom);
159 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
161 setOperationAction(Op, MVT::f32, Expand);
162 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
163 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
177 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
178 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
325 return (VT == MVT::f32 && Subtarget.hasStdExtF()) ||
400 if (Op.getValueType() != MVT::f32 || Op0.getValueType() != MVT::i32)
403 SDValue FPConv = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, NewOp0);
913 if (Op0.getValueType() != MVT::f32)
1492 if (UseGPRForF32 && ValVT == MVT::f32) {
1575 if (ValVT == MVT::f32 && !UseGPRForF32)
1610 if (ValVT == MVT::f32 || ValVT == MVT::f64) {
1675 if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) {
1676 Val = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, Val);
1702 case MVT::f32:
1730 if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) {
1825 if (LocVT == MVT::f32) {
1849 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
2565 if (Subtarget.hasStdExtF() && VT == MVT::f32)
2892 if (ABI == RISCVABI::ABI_LP64 && (Type == MVT::f32))
lib/Target/Sparc/SparcISelLowering.cpp 109 assert((LocVT == MVT::f32 || LocVT == MVT::f128
125 else if (LocVT == MVT::f32 && Offset < 16*8)
141 if (LocVT == MVT::f32)
157 if (LocVT == MVT::f32 && Offset < 16*8) {
451 if (VA.getLocVT() == MVT::f32)
452 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
510 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
903 if (VA.getLocVT() != MVT::f32) {
1295 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && !CLI.CS)
1424 addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
1470 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1479 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1480 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1520 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
1525 setOperationAction(ISD::SELECT, MVT::f32, Expand);
1530 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1539 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1544 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1626 setOperationAction(ISD::FSIN , MVT::f32, Expand);
1627 setOperationAction(ISD::FCOS , MVT::f32, Expand);
1628 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1629 setOperationAction(ISD::FREM , MVT::f32, Expand);
1630 setOperationAction(ISD::FMA , MVT::f32, Expand);
1638 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1641 setOperationAction(ISD::FPOW , MVT::f32, Expand);
1746 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
1791 setOperationAction(ISD::FDIV, MVT::f32, Promote);
1792 setOperationAction(ISD::FSQRT, MVT::f32, Promote);
1796 setOperationAction(ISD::FMUL, MVT::f32, Promote);
2304 if (Op.getOperand(0).getValueType() == MVT::f32)
2322 if (Op.getValueType() == MVT::f32)
2352 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
2366 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
2705 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32,
2707 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32,
2711 Lo32 = DAG.getNode(opcode, dl, MVT::f32, Lo32);
2713 Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32);
3268 if (VT == MVT::f32 || VT == MVT::i32)
3277 if (VT == MVT::f32 || VT == MVT::i32)
3311 if (VT == MVT::f32 || VT == MVT::Other) {
lib/Target/SystemZ/SystemZISelLowering.cpp 87 addRegisterClass(MVT::f32, &SystemZ::VR32BitRegClass);
90 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
529 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
530 setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal);
531 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
532 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);
557 for (auto VT : { MVT::f32, MVT::f64, MVT::f128,
565 setOperationAction(ISD::FMA, MVT::f32, Legal);
584 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f32, Expand);
589 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
590 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
597 setOperationAction(ISD::BITCAST, MVT::f32, Custom);
653 case MVT::f32:
1103 if (VT == MVT::f32)
1128 if (VT == MVT::f32)
1138 if (VT == MVT::f32)
1336 case MVT::f32:
1368 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
1541 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
3123 if (InVT == MVT::i32 && ResVT == MVT::f32) {
3137 DL, MVT::f32, Out64);
3139 if (InVT == MVT::f32 && ResVT == MVT::i32) {
5749 if (N->getValueType(0) == MVT::f32 &&
5766 OtherRound.getValueType() == MVT::f32) {
5771 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(U), MVT::f32,
5776 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op0), MVT::f32,
lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp 139 case MVT::f32:
lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp 60 for (MVT T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64, MVT::v16i8, MVT::v8i16,
lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp 156 return MVT::f32;
lib/Target/WebAssembly/WebAssemblyFastISel.cpp 130 case MVT::f32:
135 return MVT::f32;
673 case MVT::f32:
784 case MVT::f32:
920 case MVT::f32:
1189 case MVT::f32:
1243 case MVT::f32:
1323 case MVT::f32:
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 56 addRegisterClass(MVT::f32, &WebAssembly::F32RegClass);
84 for (auto T : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
220 for (auto T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64})
232 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
233 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
lib/Target/X86/X86FastISel.cpp 161 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
302 if (VT == MVT::f32 && !X86ScalarSSEf32)
348 case MVT::f32:
516 case MVT::f32:
1350 case MVT::f32:
2155 !((Subtarget->hasSSE1() && RetVT == MVT::f32) ||
2208 (RetVT == MVT::f32) ? X86::VCMPSSZrr : X86::VCMPSDZrr;
2221 (RetVT == MVT::f32) ? X86::VMOVSSZrrk : X86::VMOVSDZrrk;
2239 (RetVT == MVT::f32) ? X86::VCMPSSrr : X86::VCMPSDrr;
2241 (RetVT == MVT::f32) ? X86::VBLENDVPSrr : X86::VBLENDVPDrr;
2260 case MVT::f32: Opc = &OpcTable[0][0]; break;
2290 case MVT::f32: Opc = Subtarget->hasAVX512() ? X86::CMOV_FR32X
2523 return X86SelectFPExtOrFPTrunc(I, Opc, TLI.getRegClassFor(MVT::f32));
2827 case MVT::f32: Opc = SqrtOpc[AVXLevel][0]; break;
3102 case MVT::f32:
3138 case MVT::f32: LLVM_FALLTHROUGH;
3559 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
3582 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
3588 Opc = ResVT == MVT::f32 ? X86::MOVSSrm_alt : X86::MOVSDrm_alt;
3749 case MVT::f32:
3901 case MVT::f32:
lib/Target/X86/X86ISelLowering.cpp 195 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
198 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
201 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
289 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
320 for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128,
331 setOperationAction(ISD::FREM , MVT::f32 , Expand);
374 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
375 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
386 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
390 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
415 for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128 }) {
518 addRegisterClass(MVT::f32, Subtarget.hasAVX512() ? &X86::FR32XRegClass
527 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
529 for (auto VT : { MVT::f32, MVT::f64 }) {
556 addRegisterClass(MVT::f32, &X86::FR32RegClass);
561 setOperationAction(ISD::FABS , MVT::f32, Custom);
564 setOperationAction(ISD::FNEG , MVT::f32, Custom);
572 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
575 setOperationAction(ISD::FSIN , MVT::f32, Expand);
576 setOperationAction(ISD::FCOS , MVT::f32, Expand);
577 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
589 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
591 for (auto VT : { MVT::f32, MVT::f64 }) {
603 if (isTypeLegal(MVT::f32)) {
604 if (UseX87 && (getRegClassFor(MVT::f32) == &X86::RFP32RegClass)) {
625 setOperationAction(ISD::FMA, MVT::f32, Expand);
690 if (isTypeLegal(MVT::f32)) {
691 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
692 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
705 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f32, Expand);
708 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
714 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
1031 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
1182 for (auto VT : { MVT::f32, MVT::f64, MVT::v4f32, MVT::v8f32,
1812 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1833 if (isOperationExpand(Op, MVT::f32))
1834 setOperationAction(Op, MVT::f32, Promote);
2134 if (VT == MVT::f32)
2267 case MVT::f32: case MVT::f64:
2525 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2849 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64 || CopyVT == MVT::f128) &&
3242 else if (RegVT == MVT::f32)
5417 } else if (EltVT == MVT::f32) {
7680 if (PVT != MVT::i32 && PVT != MVT::f32)
9710 if (EltVT == MVT::i32 || EltVT == MVT::f32 || EltVT == MVT::f64 ||
10910 if (EltVT == MVT::f32 || EltVT == MVT::f64) {
12322 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
12324 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
17294 if (VT == MVT::f32) {
17311 return DAG.getBitcast(MVT::f32, Extract);
17589 if ((Subtarget.hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
17616 (EltVT == MVT::i32 || EltVT == MVT::f32 || EltVT == MVT::f64 ||
17643 if (EltVT == MVT::f32) {
18337 (VT != MVT::f32 && VT != MVT::f64))
18828 if (Subtarget.is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
18888 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
18912 if (TheVT != MVT::f32 && TheVT != MVT::f64 && TheVT != MVT::f80) {
19733 assert((Op.getValueType() == MVT::f32 || Op.getValueType() == MVT::f64) &&
19757 assert((VT == MVT::f64 || VT == MVT::f32 || VT == MVT::f128 ||
19817 assert((VT == MVT::f64 || VT == MVT::f32 || VT == MVT::f128 ||
19873 assert((OpVT == MVT::f32 || OpVT == MVT::f64) &&
19877 MVT VecVT = (OpVT == MVT::f32 ? MVT::v4f32 : MVT::v2f64);
20244 if ((VT == MVT::f32 && Subtarget.hasSSE1()) ||
20274 if ((VT == MVT::f32 && Subtarget.hasSSE1()) ||
20281 if (VT == MVT::f32 && Enabled == ReciprocalEstimate::Unspecified)
20639 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
21215 (Subtarget.hasSSE1() && VT == MVT::f32)) &&
21249 MVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
21254 MVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
21269 if ((VT == MVT::f64 || VT == MVT::f32) && Subtarget.hasAVX512()) {
28184 (SrcVT == MVT::f32 || SrcVT == MVT::f64)) {
29113 case MVT::f32:
32008 ShuffleVT = (AllowIntDomain ? MVT::i32 : MVT::f32);
32255 ShuffleVT = MVT::getVectorVT(MVT::f32, MaskVT.getSizeInBits() / 32);
33703 SDValue Load = DAG.getLoad(MVT::f32, DL, MemIntr->getChain(),
33987 VT.getVectorElementType() != MVT::f32 &&
35666 if (!((Subtarget.hasSSE1() && VT == MVT::f32) ||
36183 if (OpVT != MVT::f32 && OpVT != MVT::f64)
36195 if (VT != MVT::f32 && VT != MVT::f64)
36839 (Subtarget.hasSSE1() && VT.getScalarType() == MVT::f32))) {
36990 Cond.getOpcode() == ISD::SETCC && (VT == MVT::f32 || VT == MVT::f64)) {
38671 if (VT == MVT::f32 || VT == MVT::f64) {
38733 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
38866 !((Subtarget.hasSSE1() && N00Type == MVT::f32) ||
41559 if (Arg.getOpcode() == ISD::FMUL && (SVT == MVT::f32 || SVT == MVT::f64) &&
41615 !(SVT == MVT::f32 || SVT == MVT::f64) || !LegalOperations)
41655 !(SVT == MVT::f32 || SVT == MVT::f64) || !LegalOperations)
41818 if (!((VT == MVT::f32 && Subtarget.hasSSE1()) ||
41920 if (!((Subtarget.hasSSE1() && VT == MVT::f32) ||
42422 SVT != MVT::i64 && SVT != MVT::f32 && SVT != MVT::f64)
42502 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) || !Subtarget.hasAnyFMA())
45826 if (VT == MVT::i32 || VT == MVT::f32)
45839 if (VT == MVT::i32 || VT == MVT::f32)
45854 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget.is64Bit())
45868 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
45887 case MVT::f32:
46087 if (VT == MVT::f32 || VT == MVT::i32)
lib/Target/X86/X86ISelLowering.h 839 return VT == MVT::f32 || VT == MVT::f64 || VT.isVector();
1113 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
1144 return (EltVT == MVT::f32 || EltVT == MVT::f64) && Index == 0;
lib/Target/X86/X86InstrInfo.cpp 5982 case MVT::f32:
lib/Target/X86/X86TargetTransformInfo.cpp 185 { ISD::FDIV, MVT::f32, 18 }, // divss
203 { ISD::FDIV, MVT::f32, 17 }, // divss
701 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/
738 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/
752 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/
757 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/
762 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/
766 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/
831 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/
836 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/
839 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/
848 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/
851 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/
854 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/
1393 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 },
1582 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 },
1831 { ISD::SETCC, MVT::f32, 1 },
1988 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/
2025 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/
2033 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss
2039 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss
2047 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/
2103 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/
utils/TableGen/CodeGenTarget.cpp 72 case MVT::f32: return "MVT::f32";
utils/TableGen/IntrinsicEmitter.cpp 248 case MVT::f32: return Sig.push_back(IIT_F32);