reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

 6290     it = Inst.insert(it, MCOperand::createImm(0)); // no modifiers for src2
 6292     Inst.insert(it, Inst.getOperand(0)); // src2 = dst
 6922     Inst.insert(it, Inst.getOperand(0)); // src2 = dst

lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

   85     MI.insert(I, Op);
  395           MI.insert(MI.begin() + VAddr0Idx + 1 + i,

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

 9898         Inst.insert(Inst.begin(),
 9928     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
 9929     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
 9939     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
 9940     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));

lib/Target/ARM/Disassembler/ARMDisassembler.cpp

  737       MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
  742   MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
  833     CCI = MI.insert(CCI, MCOperand::createImm(CC));
  836       MI.insert(CCI, MCOperand::createReg(0));
  838       MI.insert(CCI, MCOperand::createReg(ARM::CPSR));
  850     VCCI = MI.insert(VCCI, MCOperand::createImm(VCC));
  853       MI.insert(VCCI, MCOperand::createReg(0));
  855       MI.insert(VCCI, MCOperand::createReg(ARM::P0));
  861       MI.insert(VCCI, MI.getOperand(TiedOp));

lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp

  281     MI.insert(MI.begin() + 1,
  285     MI.insert(MI.begin() + 2,
  451     MI.insert(MI.begin() + 1,

lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

  221     Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));
  244     Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));