reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
6480 Inst.addOperand(Inst.getOperand(TiedResOpnd));
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 3803 Inst.addOperand(Inst.getOperand(TiedResOpnd));
gen/lib/Target/ARM/ARMGenAsmMatcher.inc 4364 Inst.addOperand(Inst.getOperand(TiedResOpnd));
gen/lib/Target/AVR/AVRGenAsmMatcher.inc 513 Inst.addOperand(Inst.getOperand(TiedResOpnd));
gen/lib/Target/BPF/BPFGenAsmMatcher.inc 285 Inst.addOperand(Inst.getOperand(TiedResOpnd));
gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc 2562 Inst.addOperand(Inst.getOperand(TiedResOpnd));
gen/lib/Target/Lanai/LanaiGenAsmMatcher.inc 361 Inst.addOperand(Inst.getOperand(TiedResOpnd));
gen/lib/Target/MSP430/MSP430GenAsmMatcher.inc 346 Inst.addOperand(Inst.getOperand(TiedResOpnd));
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 1342 Inst.addOperand(Inst.getOperand(TiedResOpnd));
gen/lib/Target/PowerPC/PPCGenAsmMatcher.inc 2098 Inst.addOperand(Inst.getOperand(TiedResOpnd));
gen/lib/Target/RISCV/RISCVGenAsmMatcher.inc 967 Inst.addOperand(Inst.getOperand(TiedResOpnd));
gen/lib/Target/Sparc/SparcGenAsmMatcher.inc 1586 Inst.addOperand(Inst.getOperand(TiedResOpnd));
gen/lib/Target/SystemZ/SystemZGenAsmMatcher.inc 1359 Inst.addOperand(Inst.getOperand(TiedResOpnd));
gen/lib/Target/WebAssembly/WebAssemblyGenAsmMatcher.inc 176 Inst.addOperand(Inst.getOperand(TiedResOpnd));
gen/lib/Target/X86/X86GenAsmMatcher.inc 4957 Inst.addOperand(Inst.getOperand(TiedResOpnd));
lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp 269 const MCOperand &Op = Inst.getOperand(OpIdx);
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp3914 if (Inst.getOperand(0).getReg() != Prefix.getDstReg()) 3920 if (Inst.getOperand(i).isReg() && 3922 isMatchingOrAlias(Prefix.getDstReg(), Inst.getOperand(i).getReg())) 3934 if (Inst.getOperand(i).isReg() && 3935 PPRRegClass.contains(Inst.getOperand(i).getReg())) { 3947 if (Inst.getOperand(PgIdx).getReg() != Prefix.getPgReg()) 3967 unsigned Rt = Inst.getOperand(1).getReg(); 3968 unsigned Rt2 = Inst.getOperand(2).getReg(); 3969 unsigned Rn = Inst.getOperand(3).getReg(); 3984 unsigned Rt = Inst.getOperand(0).getReg(); 3985 unsigned Rt2 = Inst.getOperand(1).getReg(); 3997 unsigned Rt = Inst.getOperand(1).getReg(); 3998 unsigned Rt2 = Inst.getOperand(2).getReg(); 4013 unsigned Rt = Inst.getOperand(1).getReg(); 4014 unsigned Rt2 = Inst.getOperand(2).getReg(); 4015 unsigned Rn = Inst.getOperand(3).getReg(); 4046 unsigned Rt = Inst.getOperand(1).getReg(); 4047 unsigned Rn = Inst.getOperand(2).getReg(); 4065 unsigned Rt = Inst.getOperand(1).getReg(); 4066 unsigned Rn = Inst.getOperand(2).getReg(); 4080 unsigned Rs = Inst.getOperand(0).getReg(); 4081 unsigned Rt = Inst.getOperand(1).getReg(); 4082 unsigned Rn = Inst.getOperand(2).getReg(); 4093 unsigned Rs = Inst.getOperand(0).getReg(); 4094 unsigned Rt1 = Inst.getOperand(1).getReg(); 4095 unsigned Rt2 = Inst.getOperand(2).getReg(); 4096 unsigned Rn = Inst.getOperand(3).getReg(); 4120 if (Inst.getOperand(2).isExpr()) { 4121 const MCExpr *Expr = Inst.getOperand(2).getExpr();lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
1022 Inst.addOperand(Inst.getOperand(0));
lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp100 EncodedInst |= MCRI.getEncodingValue(MI.getOperand(0).getReg()); // reg 129 MCRI.getEncodingValue(MI.getOperand(1).getReg()) << 5; // Rn 130 EncodedInst |= MCRI.getEncodingValue(MI.getOperand(0).getReg()); // Rdlib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
2677 const auto &Op = Inst.getOperand(OpNum); 4832 Inst.getOperand(OperandIdx[1]) = Inst.getOperand(OperandIdx[2]); 4832 Inst.getOperand(OperandIdx[1]) = Inst.getOperand(OperandIdx[2]); 4833 Inst.getOperand(OperandIdx[2]).setReg(AMDGPU::NoRegister); 4834 Inst.getOperand(OperandIdx[3]).setReg(AMDGPU::NoRegister); 4838 if (Inst.getOperand(OperandIdx[i]).getReg() != AMDGPU::NoRegister) { 6174 unsigned OpSel = Inst.getOperand(OpSelIdx).getImm(); 6178 uint32_t ModVal = Inst.getOperand(ModIdx).getImm(); 6179 Inst.getOperand(ModIdx).setImm(ModVal | SISrcMods::DST_OP_SEL); 6292 Inst.insert(it, Inst.getOperand(0)); // src2 = dst 6313 Inst.addOperand(Inst.getOperand(0)); 6344 unsigned OpSel = Inst.getOperand(OpSelIdx).getImm(); 6350 OpSelHi = Inst.getOperand(OpSelHiIdx).getImm(); 6355 NegLo = Inst.getOperand(NegLoIdx).getImm(); 6356 NegHi = Inst.getOperand(NegHiIdx).getImm(); 6380 Inst.getOperand(ModIdx).setImm(Inst.getOperand(ModIdx).getImm() | ModVal); 6380 Inst.getOperand(ModIdx).setImm(Inst.getOperand(ModIdx).getImm() | ModVal); 6694 Inst.addOperand(Inst.getOperand(TiedTo)); 6922 Inst.insert(it, Inst.getOperand(0)); // src2 = dstlib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
415 !MI.getOperand(VDstIn_Idx).isReg() || 416 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 416 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 418 MI.erase(&MI.getOperand(VDstIn_Idx)); 420 MCOperand::createReg(MI.getOperand(Tied).getReg()), 507 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 528 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 531 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 537 if (MI.getOperand(TFEIdx).getImm()) 554 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 570 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 584 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 588 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 593 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0);lib/Target/ARM/AsmParser/ARMAsmParser.cpp
2368 RegNum = Inst.getOperand(TiedOp).getReg(); 5563 Inst.addOperand(Inst.getOperand(0)); 7229 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(RtIndex).getReg()); 7230 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(RtIndex + 1).getReg()); 7264 unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg()); 7309 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm()); 7323 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 7329 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 7339 if (Inst.getOperand(i).getImm() != ARMCC::AL) 7356 unsigned Pred = Inst.getOperand(findFirstVectorPredOperandIdx(MCID)).getImm(); 7370 Inst.getOperand(findFirstVectorPredOperandIdx(MCID)).getImm() != 7380 unsigned Cond = Inst.getOperand(0).getImm(); 7381 unsigned Mask = Inst.getOperand(1).getImm(); 7413 const unsigned RmReg = Inst.getOperand(0).getReg(); 7454 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 7455 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); 7487 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 7488 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); 7531 const unsigned Qd = MRI->getEncodingValue(Inst.getOperand(QdIdx).getReg()); 7532 const unsigned Qm = MRI->getEncodingValue(Inst.getOperand(QmIdx).getReg()); 7548 unsigned LSB = Inst.getOperand(2).getImm(); 7549 unsigned Widthm1 = Inst.getOperand(3).getImm(); 7563 unsigned Rn = Inst.getOperand(0).getReg(); 7594 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 7612 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 7683 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(), 7704 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 7704 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 7718 if (Inst.getOperand(0).getReg() == ARM::SP && 7719 Inst.getOperand(1).getReg() != ARM::SP) 7779 unsigned Imm8 = Inst.getOperand(0).getImm(); 7780 unsigned Pred = Inst.getOperand(1).getImm(); 7798 (Inst.getOperand(0).isImm() && Inst.getOperand(0).getImm() == 0)) 7798 (Inst.getOperand(0).isImm() && Inst.getOperand(0).getImm() == 0)) 7815 (Inst.getOperand(0).isImm() && Inst.getOperand(0).getImm() == 0)) 7815 (Inst.getOperand(0).isImm() && Inst.getOperand(0).getImm() == 0)) 7823 assert(Inst.getOperand(0).isImm() == Inst.getOperand(2).isImm() && 7823 assert(Inst.getOperand(0).isImm() == Inst.getOperand(2).isImm() && 7827 if (Inst.getOperand(0).isImm() && Inst.getOperand(2).isImm()) { 7827 if (Inst.getOperand(0).isImm() && Inst.getOperand(2).isImm()) { 7828 int Diff = Inst.getOperand(2).getImm() - Inst.getOperand(0).getImm(); 7828 int Diff = Inst.getOperand(2).getImm() - Inst.getOperand(0).getImm(); 7838 if (Inst.getOperand(i).isReg() && 7840 Inst.getOperand(i).getReg())) { 7854 unsigned Option = Inst.getOperand(0).getImm(); 7855 unsigned Pred = Inst.getOperand(1).getImm(); 7870 const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(2).getReg()); 7871 const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(3).getReg()); 7879 const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 7880 const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 8236 TmpInst.addOperand(Inst.getOperand(0)); 8237 TmpInst.addOperand(Inst.getOperand(1)); 8240 unsigned imm = ~Inst.getOperand(2).getImm() & (imm16 ? 0xffff : 0xffffffff); 8243 TmpInst.addOperand(Inst.getOperand(3)); 8244 TmpInst.addOperand(Inst.getOperand(4)); 8256 TmpInst.addOperand(Inst.getOperand(0)); 8257 TmpInst.addOperand(Inst.getOperand(1)); 8258 TmpInst.addOperand(Inst.getOperand(1)); 8261 TmpInst.addOperand(Inst.getOperand(2)); 8262 TmpInst.addOperand(Inst.getOperand(3)); 8274 TmpInst.addOperand(Inst.getOperand(1)); 8275 TmpInst.addOperand(Inst.getOperand(0)); 8276 TmpInst.addOperand(Inst.getOperand(1)); 8279 TmpInst.addOperand(Inst.getOperand(2)); 8280 TmpInst.addOperand(Inst.getOperand(3)); 8286 if (Inst.getOperand(1).getReg() != ARM::PC || 8287 Inst.getOperand(5).getReg() != 0 || 8288 !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm())) 8288 !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm())) 8292 TmpInst.addOperand(Inst.getOperand(0)); 8293 if (Inst.getOperand(2).isImm()) { 8296 unsigned Enc = Inst.getOperand(2).getImm(); 8305 const MCExpr *OpExpr = Inst.getOperand(2).getExpr(); 8316 TmpInst.addOperand(Inst.getOperand(3)); 8317 TmpInst.addOperand(Inst.getOperand(4)); 8324 if (Inst.getOperand(1).getImm() > 0 && 8325 Inst.getOperand(1).getImm() <= 0xff && 8363 Inst.getOperand(0).getReg() != ARM::PC && 8364 Inst.getOperand(0).getReg() != ARM::SP) { 8406 TmpInst.addOperand(Inst.getOperand(0)); // Rt 8408 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 8409 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 8420 TmpInst.addOperand(Inst.getOperand(0)); // Rt 8424 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 8425 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 8438 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8439 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8440 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8441 TmpInst.addOperand(Inst.getOperand(4)); // Rm 8442 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8443 TmpInst.addOperand(Inst.getOperand(1)); // lane 8444 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 8445 TmpInst.addOperand(Inst.getOperand(6)); 8460 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8461 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8462 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8463 TmpInst.addOperand(Inst.getOperand(4)); // Rm 8464 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8465 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8467 TmpInst.addOperand(Inst.getOperand(1)); // lane 8468 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 8469 TmpInst.addOperand(Inst.getOperand(6)); 8484 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8485 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8486 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8487 TmpInst.addOperand(Inst.getOperand(4)); // Rm 8488 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8489 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8491 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8493 TmpInst.addOperand(Inst.getOperand(1)); // lane 8494 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 8495 TmpInst.addOperand(Inst.getOperand(6)); 8510 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8511 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8512 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8513 TmpInst.addOperand(Inst.getOperand(4)); // Rm 8514 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8515 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8517 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8519 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8521 TmpInst.addOperand(Inst.getOperand(1)); // lane 8522 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 8523 TmpInst.addOperand(Inst.getOperand(6)); 8536 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8537 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8538 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8540 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8541 TmpInst.addOperand(Inst.getOperand(1)); // lane 8542 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8543 TmpInst.addOperand(Inst.getOperand(5)); 8558 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8559 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8560 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8562 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8563 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8565 TmpInst.addOperand(Inst.getOperand(1)); // lane 8566 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8567 TmpInst.addOperand(Inst.getOperand(5)); 8582 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8583 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8584 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8586 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8587 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8589 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8591 TmpInst.addOperand(Inst.getOperand(1)); // lane 8592 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8593 TmpInst.addOperand(Inst.getOperand(5)); 8608 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8609 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8610 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8612 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8613 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8615 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8617 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8619 TmpInst.addOperand(Inst.getOperand(1)); // lane 8620 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8621 TmpInst.addOperand(Inst.getOperand(5)); 8634 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8635 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8636 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8637 TmpInst.addOperand(Inst.getOperand(1)); // lane 8638 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8639 TmpInst.addOperand(Inst.getOperand(5)); 8654 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8655 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8656 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8657 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8659 TmpInst.addOperand(Inst.getOperand(1)); // lane 8660 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8661 TmpInst.addOperand(Inst.getOperand(5)); 8676 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8677 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8678 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8679 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8681 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8683 TmpInst.addOperand(Inst.getOperand(1)); // lane 8684 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8685 TmpInst.addOperand(Inst.getOperand(5)); 8700 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8701 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8702 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8703 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8705 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8707 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8709 TmpInst.addOperand(Inst.getOperand(1)); // lane 8710 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8711 TmpInst.addOperand(Inst.getOperand(5)); 8725 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8726 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8727 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8728 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8729 TmpInst.addOperand(Inst.getOperand(4)); // Rm 8730 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8731 TmpInst.addOperand(Inst.getOperand(1)); // lane 8732 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 8733 TmpInst.addOperand(Inst.getOperand(6)); 8748 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8749 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8751 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8752 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8753 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8754 TmpInst.addOperand(Inst.getOperand(4)); // Rm 8755 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8756 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8758 TmpInst.addOperand(Inst.getOperand(1)); // lane 8759 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 8760 TmpInst.addOperand(Inst.getOperand(6)); 8775 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8776 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8778 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8780 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8781 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8782 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8783 TmpInst.addOperand(Inst.getOperand(4)); // Rm 8784 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8785 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8787 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8789 TmpInst.addOperand(Inst.getOperand(1)); // lane 8790 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 8791 TmpInst.addOperand(Inst.getOperand(6)); 8806 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8807 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8809 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8811 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8813 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8814 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8815 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8816 TmpInst.addOperand(Inst.getOperand(4)); // Rm 8817 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8818 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8820 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8822 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8824 TmpInst.addOperand(Inst.getOperand(1)); // lane 8825 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 8826 TmpInst.addOperand(Inst.getOperand(6)); 8839 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8840 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8841 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8842 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8844 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8845 TmpInst.addOperand(Inst.getOperand(1)); // lane 8846 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8847 TmpInst.addOperand(Inst.getOperand(5)); 8862 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8863 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8865 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8866 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8867 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8869 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8870 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8872 TmpInst.addOperand(Inst.getOperand(1)); // lane 8873 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8874 TmpInst.addOperand(Inst.getOperand(5)); 8889 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8890 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8892 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8894 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8895 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8896 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8898 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8899 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8901 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8903 TmpInst.addOperand(Inst.getOperand(1)); // lane 8904 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8905 TmpInst.addOperand(Inst.getOperand(5)); 8920 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8921 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8923 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8925 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8927 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8928 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8929 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8931 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8932 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8934 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8936 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8938 TmpInst.addOperand(Inst.getOperand(1)); // lane 8939 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8940 TmpInst.addOperand(Inst.getOperand(5)); 8953 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8954 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8955 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8956 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8957 TmpInst.addOperand(Inst.getOperand(1)); // lane 8958 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8959 TmpInst.addOperand(Inst.getOperand(5)); 8974 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8975 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8977 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8978 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8979 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8980 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8982 TmpInst.addOperand(Inst.getOperand(1)); // lane 8983 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8984 TmpInst.addOperand(Inst.getOperand(5)); 8999 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9000 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9002 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9004 TmpInst.addOperand(Inst.getOperand(2)); // Rn 9005 TmpInst.addOperand(Inst.getOperand(3)); // alignment 9006 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 9007 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9009 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9011 TmpInst.addOperand(Inst.getOperand(1)); // lane 9012 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9013 TmpInst.addOperand(Inst.getOperand(5)); 9028 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9029 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9031 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9033 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9035 TmpInst.addOperand(Inst.getOperand(2)); // Rn 9036 TmpInst.addOperand(Inst.getOperand(3)); // alignment 9037 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 9038 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9040 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9042 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9044 TmpInst.addOperand(Inst.getOperand(1)); // lane 9045 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9046 TmpInst.addOperand(Inst.getOperand(5)); 9061 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9062 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9064 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9066 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9067 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9068 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9069 TmpInst.addOperand(Inst.getOperand(4)); 9083 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9084 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9086 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9088 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9089 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9090 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9092 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9093 TmpInst.addOperand(Inst.getOperand(4)); 9107 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9108 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9110 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9112 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9113 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9114 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9115 TmpInst.addOperand(Inst.getOperand(3)); // Rm 9116 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9117 TmpInst.addOperand(Inst.getOperand(5)); 9132 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9133 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9135 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9137 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9138 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9139 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9140 TmpInst.addOperand(Inst.getOperand(4)); 9154 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9155 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9157 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9159 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9160 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9161 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9163 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9164 TmpInst.addOperand(Inst.getOperand(4)); 9178 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9179 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9181 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9183 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9184 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9185 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9186 TmpInst.addOperand(Inst.getOperand(3)); // Rm 9187 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9188 TmpInst.addOperand(Inst.getOperand(5)); 9203 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9204 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9206 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9208 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9210 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9211 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9212 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9213 TmpInst.addOperand(Inst.getOperand(4)); 9227 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9228 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9230 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9232 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9234 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9235 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9236 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9238 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9239 TmpInst.addOperand(Inst.getOperand(4)); 9253 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9254 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9256 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9258 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9260 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9261 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9262 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9263 TmpInst.addOperand(Inst.getOperand(3)); // Rm 9264 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9265 TmpInst.addOperand(Inst.getOperand(5)); 9280 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9281 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9283 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9285 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9287 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9288 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9289 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9290 TmpInst.addOperand(Inst.getOperand(4)); 9304 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9305 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9307 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9309 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9311 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9312 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9313 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9315 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9316 TmpInst.addOperand(Inst.getOperand(4)); 9330 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9331 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9333 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9335 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9337 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9338 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9339 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9340 TmpInst.addOperand(Inst.getOperand(3)); // Rm 9341 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9342 TmpInst.addOperand(Inst.getOperand(5)); 9357 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9358 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9359 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9360 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9362 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9364 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9365 TmpInst.addOperand(Inst.getOperand(4)); 9379 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9380 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9381 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9383 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9384 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9386 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9388 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9389 TmpInst.addOperand(Inst.getOperand(4)); 9403 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9404 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9405 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9406 TmpInst.addOperand(Inst.getOperand(3)); // Rm 9407 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9408 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9410 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9412 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9413 TmpInst.addOperand(Inst.getOperand(5)); 9428 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9429 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9430 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9431 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9433 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9435 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9437 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9438 TmpInst.addOperand(Inst.getOperand(4)); 9452 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9453 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9454 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9456 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9457 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9459 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9461 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9463 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9464 TmpInst.addOperand(Inst.getOperand(4)); 9478 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9479 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9480 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9481 TmpInst.addOperand(Inst.getOperand(3)); // Rm 9482 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9483 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9485 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9487 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9489 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9490 TmpInst.addOperand(Inst.getOperand(5)); 9499 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 9500 isARMLowRegister(Inst.getOperand(1).getReg()) && 9501 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 9513 TmpInst.addOperand(Inst.getOperand(0)); 9514 TmpInst.addOperand(Inst.getOperand(5)); 9515 TmpInst.addOperand(Inst.getOperand(1)); 9516 TmpInst.addOperand(Inst.getOperand(2)); 9517 TmpInst.addOperand(Inst.getOperand(3)); 9518 TmpInst.addOperand(Inst.getOperand(4)); 9531 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 9532 isARMLowRegister(Inst.getOperand(1).getReg()) && 9533 isARMLowRegister(Inst.getOperand(2).getReg()) && 9534 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 9534 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 9540 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { 9548 TmpInst.addOperand(Inst.getOperand(0)); // Rd 9552 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9553 TmpInst.addOperand(Inst.getOperand(2)); // Rm 9554 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9555 TmpInst.addOperand(Inst.getOperand(5)); 9568 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 9569 isARMLowRegister(Inst.getOperand(1).getReg()) && 9575 unsigned Shift = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); 9576 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); 9601 TmpInst.addOperand(Inst.getOperand(0)); // Rd 9605 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9608 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9609 TmpInst.addOperand(Inst.getOperand(4)); 9632 TmpInst.addOperand(Inst.getOperand(0)); // Rd 9633 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9634 TmpInst.addOperand(Inst.getOperand(2)); // Rm 9636 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9637 TmpInst.addOperand(Inst.getOperand(4)); 9638 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 9655 unsigned Amt = Inst.getOperand(2).getImm(); 9663 TmpInst.addOperand(Inst.getOperand(0)); // Rd 9664 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9667 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9668 TmpInst.addOperand(Inst.getOperand(4)); 9669 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 9677 TmpInst.addOperand(Inst.getOperand(0)); // Rd 9678 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9680 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 9681 TmpInst.addOperand(Inst.getOperand(3)); 9682 TmpInst.addOperand(Inst.getOperand(4)); // cc_out 9693 TmpInst.addOperand(Inst.getOperand(4)); // Rt 9694 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 9695 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9697 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 9698 TmpInst.addOperand(Inst.getOperand(3)); 9709 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 9710 TmpInst.addOperand(Inst.getOperand(4)); // Rt 9711 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9713 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 9714 TmpInst.addOperand(Inst.getOperand(3)); 9725 TmpInst.addOperand(Inst.getOperand(4)); // Rt 9726 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 9727 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9730 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 9731 TmpInst.addOperand(Inst.getOperand(3)); 9743 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 9744 TmpInst.addOperand(Inst.getOperand(4)); // Rt 9745 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 9747 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 9748 TmpInst.addOperand(Inst.getOperand(3)); 9756 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 9765 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 9775 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 9785 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 9796 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 9796 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 9797 !isARMLowRegister(Inst.getOperand(0).getReg()) || 9798 (Inst.getOperand(2).isImm() && 9799 (unsigned)Inst.getOperand(2).getImm() > 255) || 9800 Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) || 9806 TmpInst.addOperand(Inst.getOperand(0)); 9807 TmpInst.addOperand(Inst.getOperand(5)); 9808 TmpInst.addOperand(Inst.getOperand(0)); 9809 TmpInst.addOperand(Inst.getOperand(2)); 9810 TmpInst.addOperand(Inst.getOperand(3)); 9811 TmpInst.addOperand(Inst.getOperand(4)); 9822 auto DestReg = Inst.getOperand(0).getReg(); 9823 bool Transform = DestReg == Inst.getOperand(1).getReg(); 9824 if (!Transform && DestReg == Inst.getOperand(2).getReg()) { 9829 Inst.getOperand(5).getReg() != 0 || 9834 TmpInst.addOperand(Inst.getOperand(0)); 9835 TmpInst.addOperand(Inst.getOperand(0)); 9836 TmpInst.addOperand(Inst.getOperand(Swap ? 1 : 2)); 9837 TmpInst.addOperand(Inst.getOperand(3)); 9838 TmpInst.addOperand(Inst.getOperand(4)); 9845 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 9845 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 9853 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) { 9860 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){ 9867 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) { 9874 if (Inst.getOperand(1).getImm() == ARMCC::AL) { 9884 unsigned Rn = Inst.getOperand(0).getReg(); 9899 MCOperand::createReg(Inst.getOperand(0).getReg())); 9908 unsigned Rn = Inst.getOperand(0).getReg(); 9946 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 9947 (Inst.getOperand(1).isImm() && 9948 (unsigned)Inst.getOperand(1).getImm() <= 255) && 9949 Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 9954 TmpInst.addOperand(Inst.getOperand(0)); 9955 TmpInst.addOperand(Inst.getOperand(4)); 9956 TmpInst.addOperand(Inst.getOperand(1)); 9957 TmpInst.addOperand(Inst.getOperand(2)); 9958 TmpInst.addOperand(Inst.getOperand(3)); 9967 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 9968 isARMLowRegister(Inst.getOperand(1).getReg()) && 9969 Inst.getOperand(2).getImm() == ARMCC::AL && 9970 Inst.getOperand(4).getReg() == ARM::CPSR && 9974 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); 9975 TmpInst.addOperand(Inst.getOperand(0)); 9976 TmpInst.addOperand(Inst.getOperand(1)); 9977 TmpInst.addOperand(Inst.getOperand(2)); 9978 TmpInst.addOperand(Inst.getOperand(3)); 9990 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 9991 isARMLowRegister(Inst.getOperand(1).getReg()) && 9992 Inst.getOperand(2).getImm() == 0 && 10005 TmpInst.addOperand(Inst.getOperand(0)); 10006 TmpInst.addOperand(Inst.getOperand(1)); 10007 TmpInst.addOperand(Inst.getOperand(3)); 10008 TmpInst.addOperand(Inst.getOperand(4)); 10015 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); 10019 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { 10023 TmpInst.addOperand(Inst.getOperand(0)); 10024 TmpInst.addOperand(Inst.getOperand(1)); 10025 TmpInst.addOperand(Inst.getOperand(3)); 10026 TmpInst.addOperand(Inst.getOperand(4)); 10027 TmpInst.addOperand(Inst.getOperand(5)); 10040 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); 10053 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 && 10057 TmpInst.addOperand(Inst.getOperand(0)); 10058 TmpInst.addOperand(Inst.getOperand(1)); 10059 TmpInst.addOperand(Inst.getOperand(2)); 10060 TmpInst.addOperand(Inst.getOperand(4)); 10061 TmpInst.addOperand(Inst.getOperand(5)); 10062 TmpInst.addOperand(Inst.getOperand(6)); 10073 startExplicitITBlock(ARMCC::CondCodes(Inst.getOperand(0).getImm()), 10074 Inst.getOperand(1).getImm()); 10084 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 10085 isARMLowRegister(Inst.getOperand(2).getReg())) && 10086 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 10086 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 10087 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 10101 TmpInst.addOperand(Inst.getOperand(0)); 10102 TmpInst.addOperand(Inst.getOperand(5)); 10103 TmpInst.addOperand(Inst.getOperand(1)); 10104 TmpInst.addOperand(Inst.getOperand(2)); 10105 TmpInst.addOperand(Inst.getOperand(3)); 10106 TmpInst.addOperand(Inst.getOperand(4)); 10119 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 10120 isARMLowRegister(Inst.getOperand(2).getReg())) && 10121 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() || 10121 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() || 10122 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) && 10122 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) && 10123 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 10135 TmpInst.addOperand(Inst.getOperand(0)); 10136 TmpInst.addOperand(Inst.getOperand(5)); 10137 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) { 10137 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) { 10138 TmpInst.addOperand(Inst.getOperand(1)); 10139 TmpInst.addOperand(Inst.getOperand(2)); 10141 TmpInst.addOperand(Inst.getOperand(2)); 10142 TmpInst.addOperand(Inst.getOperand(1)); 10144 TmpInst.addOperand(Inst.getOperand(3)); 10145 TmpInst.addOperand(Inst.getOperand(4)); 10174 MCOperand &MO = Inst.getOperand(0); 10200 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) 10204 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && 10207 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && 10211 if (Opc == ARM::tLSLri && Inst.getOperand(3).getImm() == 0 && inITBlock()) 10217 isARMLowRegister(Inst.getOperand(1).getReg()) && 10218 isARMLowRegister(Inst.getOperand(2).getReg())) 10222 isARMLowRegister(Inst.getOperand(0).getReg()) && 10223 isARMLowRegister(Inst.getOperand(1).getReg())) 10233 if (Inst.getOperand(0).getReg() == ARM::SP && 10234 Inst.getOperand(1).getReg() == ARM::SP) 10237 if (Inst.getOperand(4).getReg() == ARM::CPSR && 10238 (Inst.getOperand(0).getReg() == ARM::SP || 10239 Inst.getOperand(1).getReg() == ARM::SP)) 10259 if (Inst.getOperand(0).isReg() && Inst.getOperand(0).getReg() == ARM::SP && 10259 if (Inst.getOperand(0).isReg() && Inst.getOperand(0).getReg() == ARM::SP && 10270 const auto &Op = Inst.getOperand(I); 10340 (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx()) 10364 (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx()) 10391 (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())lib/Target/ARM/Disassembler/ARMDisassembler.cpp
602 if (MI.getOperand(0).getReg() == ARM::SP && 603 MI.getOperand(1).getReg() != ARM::SP) 790 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 861 MI.insert(VCCI, MI.getOperand(TiedOp)); 957 unsigned Firstcond = MI.getOperand(0).getImm(); 958 unsigned Mask = MI.getOperand(1).getImm(); 991 unsigned Mask = MI.getOperand(0).getImm(); 1529 WritebackReg = Inst.getOperand(0).getReg(); 5937 uint64_t LocImm = Inst.getOperand(0).getImm();lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
40 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) && 40 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) && 41 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && 41 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && 44 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) { 44 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) { 45 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) { 45 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) { 46 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) { 46 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) { 53 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) { 53 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) { 60 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 && 60 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 && 61 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) { 61 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) { 71 if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() && 72 MI.getOperand(1).getImm() != 8) { 88 assert(MI.getOperand(OI).isReg() && "expected register"); 89 if (MI.getOperand(OI).getReg() == ARM::SP || 90 MI.getOperand(OI).getReg() == ARM::PC) { 106 assert(MI.getOperand(OI).isReg() && "expected register"); 107 switch (MI.getOperand(OI).getReg()) {lib/Target/BPF/Disassembler/BPFDisassembler.cpp
200 auto& Op = Instr.getOperand(1); 210 auto Op = Instr.getOperand(0);lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
1304 MCOperand &Rx = Inst.getOperand(0); 1305 MCOperand &Ry = Inst.getOperand(1); 1315 MCOperand Reg = Inst.getOperand(0); 1316 MCOperand S27 = Inst.getOperand(1); 1335 MCOperand &Ry = Inst.getOperand(0); 1336 MCOperand &src = Inst.getOperand(2); 1343 MCOperand &MO = Inst.getOperand(2); 1353 MCOperand &MO = Inst.getOperand(2); 1360 MCOperand &Pd = Inst.getOperand(0); 1361 MCOperand &Rt = Inst.getOperand(1); 1379 MCOperand &MO = Inst.getOperand(1); 1394 MCOperand &MO = Inst.getOperand(2); 1410 MCOperand &MO = Inst.getOperand(2); 1427 MCOperand &MO = Inst.getOperand(1); 1447 MCOperand &MO_1 = Inst.getOperand(1); 1448 MCOperand &MO_0 = Inst.getOperand(0); 1546 MCOperand &Rdd = Inst.getOperand(0); 1547 MCOperand &MO = Inst.getOperand(1); 1558 MCOperand &Rdd = Inst.getOperand(0); 1559 MCOperand &MO = Inst.getOperand(1); 1583 MCOperand &Rdd = Inst.getOperand(0); 1584 MCOperand &MO1 = Inst.getOperand(1); 1585 MCOperand &MO2 = Inst.getOperand(2); 1598 MCOperand &Rdd = Inst.getOperand(0); 1599 MCOperand &MO1 = Inst.getOperand(1); 1606 MCOperand &MO2 = Inst.getOperand(2); 1617 MCOperand &Rx = Inst.getOperand(0); 1618 MCOperand &Rs = Inst.getOperand(2); 1619 MCOperand &Imm4 = Inst.getOperand(3); 1620 MCOperand &Imm6 = Inst.getOperand(4); 1637 MCOperand &Rx = Inst.getOperand(0); 1638 MCOperand &Rs = Inst.getOperand(2); 1639 MCOperand &Imm4 = Inst.getOperand(3); 1640 MCOperand &Imm6 = Inst.getOperand(4); 1657 MCOperand &Rx = Inst.getOperand(0); 1658 MCOperand &Rs = Inst.getOperand(2); 1659 MCOperand &Imm4 = Inst.getOperand(3); 1660 MCOperand &Imm6 = Inst.getOperand(4); 1680 MCOperand &Rd = Inst.getOperand(0); 1681 MCOperand &Rs = Inst.getOperand(1); 1682 MCOperand &Imm = Inst.getOperand(2); 1705 MCOperand &Imm = Inst.getOperand(2); 1713 MCOperand &Rd = Inst.getOperand(0); 1714 MCOperand &Rs = Inst.getOperand(1); 1723 MCOperand &Rd = Inst.getOperand(0); 1724 MCOperand &Rs = Inst.getOperand(1); 1734 MCOperand &Rdd = Inst.getOperand(0); 1735 MCOperand &Rss = Inst.getOperand(1); 1736 MCOperand &Imm = Inst.getOperand(2); 1766 MCOperand &Rs = Inst.getOperand(1); 1783 MCOperand &Rs = Inst.getOperand(1); 1800 MCOperand &Rt = Inst.getOperand(2); 1818 MCOperand &Rxx = Inst.getOperand(0); 1819 MCOperand &Rss = Inst.getOperand(2); 1820 MCOperand &Rt = Inst.getOperand(3); 1843 MCOperand &Rt = Inst.getOperand(2); 1860 MCOperand &Imm = Inst.getOperand(2); 1878 MCOperand &Rdd = Inst.getOperand(0); 1879 MCOperand &Rss = Inst.getOperand(1); 1880 MCOperand &Imm = Inst.getOperand(2); 1911 MCOperand &Rd = Inst.getOperand(0); 1912 MCOperand &Rs = Inst.getOperand(1); 1922 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr())) 1926 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr())) 1930 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr())) 1934 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr())) 1938 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr())) 1942 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr())) 1946 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr())) 1950 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr())) 1954 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr())) 1958 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr())) 1962 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr())) 1966 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr())) 1970 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr())) 1974 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
204 if (MI.getOperand(0).getReg() == Hexagon::R29) { 211 if (MI.getOperand(0).getReg() == Hexagon::D15 && 212 MI.getOperand(1).getReg() == Hexagon::R30) { 219 if (MI.getOperand(0).getReg() == Hexagon::D15 && 220 MI.getOperand(1).getReg() == Hexagon::R30) { 227 if (MI.getOperand(0).getReg() == Hexagon::D15 && 228 MI.getOperand(2).getReg() == Hexagon::R30) { 235 if (MI.getOperand(0).getReg() == Hexagon::D15 && 236 MI.getOperand(2).getReg() == Hexagon::R30) { 243 if (MI.getOperand(0).getReg() == Hexagon::D15 && 244 MI.getOperand(2).getReg() == Hexagon::R30) { 251 if (MI.getOperand(0).getReg() == Hexagon::D15 && 252 MI.getOperand(2).getReg() == Hexagon::R30) { 259 if (MI.getOperand(0).getReg() == Hexagon::D15 && 260 MI.getOperand(2).getReg() == Hexagon::R30) { 267 if (MI.getOperand(0).getReg() == Hexagon::D15 && 268 MI.getOperand(2).getReg() == Hexagon::R30) { 460 MCOperand &MCO = MI.getOperand(OpIndex); 513 ? *MI.getOperand(1).getInst()lib/Target/Hexagon/HexagonAsmPrinter.cpp
252 T.addOperand(Inst.getOperand(i)); 255 MCOperand &ImmOp = Inst.getOperand(i); 279 MCOperand Reg = Inst.getOperand(0); 280 MCOperand S16 = Inst.getOperand(1); 328 const MCOperand &Imm = MappedInst.getOperand(1); 335 MCOperand &Reg = MappedInst.getOperand(0); 346 MCOperand &Imm = MappedInst.getOperand(1); 351 MCOperand &Reg = MappedInst.getOperand(0); 364 MCOperand &Ps = Inst.getOperand(1); 374 MCOperand &Rt = Inst.getOperand(3); 385 MCOperand &Rt = Inst.getOperand(2); 397 MCOperand &Rt = Inst.getOperand(2); 409 MCOperand &Rs = Inst.getOperand(1); 425 MCOperand &MO = MappedInst.getOperand(2); 434 TmpInst.addOperand(MappedInst.getOperand(0)); 435 TmpInst.addOperand(MappedInst.getOperand(1)); 440 TmpInst.addOperand(MappedInst.getOperand(0)); 441 TmpInst.addOperand(MappedInst.getOperand(1)); 452 MCOperand &MO2 = MappedInst.getOperand(2); 461 TmpInst.addOperand(MappedInst.getOperand(0)); 462 MCOperand &MO1 = MappedInst.getOperand(1); 476 TmpInst.addOperand(MappedInst.getOperand(0)); 477 TmpInst.addOperand(MappedInst.getOperand(1)); 488 MCOperand &MO = Inst.getOperand(2); 497 TmpInst.addOperand(MappedInst.getOperand(0)); 498 TmpInst.addOperand(MappedInst.getOperand(1)); 503 TmpInst.addOperand(MappedInst.getOperand(0)); 504 TmpInst.addOperand(MappedInst.getOperand(1)); 516 MCOperand &Rdd = MappedInst.getOperand(0); 517 MCOperand &MO = MappedInst.getOperand(1); 539 MCOperand &MO = MappedInst.getOperand(1); 551 MCOperand &MO = MappedInst.getOperand(2); 565 MCOperand &MO = MappedInst.getOperand(2); 578 MCOperand &Imm = MappedInst.getOperand(2); 594 MCOperand &Rt = Inst.getOperand(1); 607 assert(Inst.getOperand(0).isReg() && 611 TmpInst.addOperand(Inst.getOperand(0)); 612 TmpInst.addOperand(Inst.getOperand(0)); 613 TmpInst.addOperand(Inst.getOperand(0)); 620 assert (Inst.getOperand(0).isReg() && 624 TmpInst.addOperand(Inst.getOperand(0)); 625 TmpInst.addOperand(Inst.getOperand(0)); 626 TmpInst.addOperand(Inst.getOperand(0));lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
846 *MCB.getOperand(Candidate.packetIndexJ).getInst(), 847 *MCB.getOperand(Candidate.packetIndexI).getInst()); 849 MCB.getOperand(Candidate.packetIndexI).setInst(Duplex); 855 MCOperand &Operand = MCI.getOperand(0); 861 MCOperand &Operand = MCI.getOperand(0); 868 MCOperand &Operand = MCI.getOperand(0);lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp
52 BundleFlags = MCB.getOperand(0).getImm(); 76 BundleFlags = MCB.getOperand(0).getImm();lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp
112 if (Instr.getOperand(2).isReg()) { 113 Instr.getOperand(2).setReg(Lanai::R0); 115 if (Instr.getOperand(2).isImm()) 116 Instr.getOperand(2).setImm(0);lib/Target/Mips/AsmParser/MipsAsmParser.cpp
1736 return !Inst.getOperand(0).isReg(); 1808 Offset = Inst.getOperand(2); 1838 Offset = Inst.getOperand(1); 1854 Offset = Inst.getOperand(2); 1867 Offset = Inst.getOperand(1); 1878 Offset = Inst.getOperand(1); 1891 Offset = Inst.getOperand(1); 1925 Opnd = Inst.getOperand(1); 1935 Inst.getOperand(1).setImm(Imm - 32); 1942 Opnd = Inst.getOperand(2); 1968 if (Inst.getOperand(2).getImm() == 0) { 1969 if (Inst.getOperand(1).getReg() == Mips::ZERO || 1970 Inst.getOperand(1).getReg() == Mips::ZERO_64) 1995 if (Inst.getOperand(SecondOp).getReg() == Mips::ZERO || 1996 Inst.getOperand(SecondOp).getReg() == Mips::ZERO_64) { 1997 if (Inst.getOperand(FirstOp).getReg() == Mips::ZERO || 1998 Inst.getOperand(FirstOp).getReg() == Mips::ZERO_64) 2013 BInst.addOperand(Inst.getOperand(0)); 2023 const MCExpr *JalExpr = Inst.getOperand(0).getExpr(); 2036 if (expandLoadAddress(Mips::T9, Mips::NoRegister, Inst.getOperand(0), 2076 MCOperand &Op = Inst.getOperand(i); 2110 MCOperand &Op = Inst.getOperand(i); 2113 MCOperand &DstReg = Inst.getOperand(0); 2114 MCOperand &BaseReg = Inst.getOperand(1); 2139 Opnd = Inst.getOperand(0); 2149 Opnd = Inst.getOperand(2); 2157 Opnd = Inst.getOperand(1); 2165 Opnd = Inst.getOperand(2); 2174 Opnd = Inst.getOperand(2); 2184 Opnd = Inst.getOperand(2); 2193 Opnd = Inst.getOperand(2); 2203 Opnd = Inst.getOperand(2); 2213 Opnd = Inst.getOperand(2); 2221 Opnd = Inst.getOperand(1); 2230 if (Inst.getOperand(0).getReg() == Mips::RA) 2235 unsigned R0 = Inst.getOperand(0).getReg(); 2236 unsigned R1 = Inst.getOperand(1).getReg(); 2315 assert(Inst.getOperand(0).isReg() && "expected register operand kind"); 2316 assert((Inst.getOperand(1).isImm() || Inst.getOperand(1).isExpr()) && 2316 assert((Inst.getOperand(1).isImm() || Inst.getOperand(1).isExpr()) && 2319 return expandLoadAddress(Inst.getOperand(0).getReg(), Mips::NoRegister, 2320 Inst.getOperand(1), 2327 assert(Inst.getOperand(0).isReg() && "expected register operand kind"); 2328 assert(Inst.getOperand(1).isReg() && "expected register operand kind"); 2329 assert((Inst.getOperand(2).isImm() || Inst.getOperand(2).isExpr()) && 2329 assert((Inst.getOperand(2).isImm() || Inst.getOperand(2).isExpr()) && 2332 return expandLoadAddress(Inst.getOperand(0).getReg(), 2333 Inst.getOperand(1).getReg(), Inst.getOperand(2), 2333 Inst.getOperand(1).getReg(), Inst.getOperand(2), 2463 if (isInt<16>(Inst.getOperand(2).getImm())) { 2469 if (isInt<16>(Inst.getOperand(2).getImm())) { 2478 if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() && 2479 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) { 2479 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) { 2480 int64_t ImmValue = Inst.getOperand(2).getImm(); 2490 if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() && 2491 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) { 2491 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) { 2492 int64_t ImmValue = Inst.getOperand(2).getImm(); 2559 const MCOperand FirstRegOp = Inst.getOperand(0); 2582 const MCOperand SecondRegOp = Inst.getOperand(1); 2780 const MCOperand &ImmOp = Inst.getOperand(1); 2782 const MCOperand &DstRegOp = Inst.getOperand(0); 3281 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && 3281 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && 3284 unsigned FirstReg = Inst.getOperand(0).getReg(); 3285 uint64_t ImmOp64 = Inst.getOperand(1).getImm(); 3298 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && 3298 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && 3301 unsigned FirstReg = Inst.getOperand(0).getReg(); 3302 uint64_t ImmOp64 = Inst.getOperand(1).getImm(); 3352 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && 3352 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && 3355 unsigned FirstReg = Inst.getOperand(0).getReg(); 3356 uint64_t ImmOp64 = Inst.getOperand(1).getImm(); 3417 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && 3417 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && 3420 unsigned FirstReg = Inst.getOperand(0).getReg(); 3421 uint64_t ImmOp64 = Inst.getOperand(1).getImm(); 3493 MCOperand Offset = Inst.getOperand(0); 3533 const MCOperand &DstRegOp = Inst.getOperand(0); 3536 const MCOperand &ImmOp = Inst.getOperand(1); 3539 const MCOperand &MemOffsetOp = Inst.getOperand(2); 3598 const MCOperand &DstRegOp = Inst.getOperand(0); 3600 const MCOperand &BaseRegOp = Inst.getOperand(1); 3624 const MCOperand &BaseRegOp = Inst.getOperand(2); 3626 const MCOperand &ExprOp = Inst.getOperand(3); 3641 const MCOperand &OffsetOp = Inst.getOperand(2); 3722 assert(Inst.getOperand(OpNum - 1).isImm() && 3723 Inst.getOperand(OpNum - 2).isReg() && 3724 Inst.getOperand(OpNum - 3).isReg() && "Invalid instruction operand."); 3726 if (OpNum < 8 && Inst.getOperand(OpNum - 1).getImm() <= 60 && 3727 Inst.getOperand(OpNum - 1).getImm() >= 0 && 3728 (Inst.getOperand(OpNum - 2).getReg() == Mips::SP || 3729 Inst.getOperand(OpNum - 2).getReg() == Mips::SP_64) && 3730 (Inst.getOperand(OpNum - 3).getReg() == Mips::RA || 3731 Inst.getOperand(OpNum - 3).getReg() == Mips::RA_64)) { 3750 unsigned SrcReg = Inst.getOperand(0).getReg(); 3751 const MCOperand &TrgOp = Inst.getOperand(1); 3752 const MCExpr *OffsetExpr = Inst.getOperand(2).getExpr(); 4022 const MCOperand &RdRegOp = Inst.getOperand(0); 4026 const MCOperand &RsRegOp = Inst.getOperand(1); 4033 const MCOperand &RtOp = Inst.getOperand(2); 4192 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && 4192 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && 4193 Inst.getOperand(2).isReg() && "Invalid instruction operand."); 4195 unsigned FirstReg = Inst.getOperand(0).getReg(); 4196 unsigned SecondReg = Inst.getOperand(1).getReg(); 4197 unsigned ThirdReg = Inst.getOperand(2).getReg(); 4231 const MCOperand &DstRegOp = Inst.getOperand(0); 4233 const MCOperand &SrcRegOp = Inst.getOperand(1); 4235 const MCOperand &OffsetImmOp = Inst.getOperand(2); 4283 const MCOperand &DstRegOp = Inst.getOperand(0); 4285 const MCOperand &SrcRegOp = Inst.getOperand(1); 4287 const MCOperand &OffsetImmOp = Inst.getOperand(2); 4334 const MCOperand &DstRegOp = Inst.getOperand(0); 4336 const MCOperand &SrcRegOp = Inst.getOperand(1); 4338 const MCOperand &OffsetImmOp = Inst.getOperand(2); 4388 assert(Inst.getOperand(0).isReg() && 4389 Inst.getOperand(1).isReg() && 4390 Inst.getOperand(2).isReg() && "Invalid instruction operand."); 4392 unsigned DstReg = Inst.getOperand(0).getReg(); 4393 unsigned SrcReg = Inst.getOperand(1).getReg(); 4394 unsigned OpReg = Inst.getOperand(2).getReg(); 4422 assert(Inst.getOperand(0).isReg() && 4423 Inst.getOperand(1).isReg() && 4424 Inst.getOperand(2).isImm() && "Invalid instruction operand."); 4426 unsigned DstReg = Inst.getOperand(0).getReg(); 4427 unsigned SrcReg = Inst.getOperand(1).getReg(); 4428 int64_t ImmValue = Inst.getOperand(2).getImm(); 4478 assert(Inst.getOperand(0).isReg() && 4479 Inst.getOperand(1).isReg() && 4480 Inst.getOperand(2).isImm() && "Invalid instruction operand."); 4482 unsigned DstReg = Inst.getOperand(0).getReg(); 4483 unsigned SrcReg = Inst.getOperand(1).getReg(); 4485 int64_t ImmValue = Inst.getOperand(2).getImm(); 4526 assert(Inst.getOperand(0).isReg() && 4527 Inst.getOperand(1).isReg() && 4528 Inst.getOperand(2).isImm() && "Invalid instruction operand."); 4532 unsigned DstReg = Inst.getOperand(0).getReg(); 4533 unsigned SrcReg = Inst.getOperand(1).getReg(); 4534 int64_t ImmValue = Inst.getOperand(2).getImm(); 4631 unsigned DReg = Inst.getOperand(0).getReg(); 4632 unsigned SReg = Inst.getOperand(1).getReg(); 4633 unsigned TReg = Inst.getOperand(2).getReg(); 4694 unsigned DReg = Inst.getOperand(0).getReg(); 4695 unsigned SReg = Inst.getOperand(1).getReg(); 4696 int64_t ImmValue = Inst.getOperand(2).getImm(); 4756 unsigned DReg = Inst.getOperand(0).getReg(); 4757 unsigned SReg = Inst.getOperand(1).getReg(); 4758 unsigned TReg = Inst.getOperand(2).getReg(); 4819 unsigned DReg = Inst.getOperand(0).getReg(); 4820 unsigned SReg = Inst.getOperand(1).getReg(); 4821 int64_t ImmValue = Inst.getOperand(2).getImm() % 64; 4912 unsigned FirstRegOp = Inst.getOperand(0).getReg(); 4913 unsigned SecondRegOp = Inst.getOperand(1).getReg(); 4929 unsigned DstReg = Inst.getOperand(0).getReg(); 4930 unsigned SrcReg = Inst.getOperand(1).getReg(); 4931 int32_t ImmValue = Inst.getOperand(2).getImm(); 4952 unsigned DstReg = Inst.getOperand(0).getReg(); 4953 unsigned SrcReg = Inst.getOperand(1).getReg(); 4954 unsigned TmpReg = Inst.getOperand(2).getReg(); 4994 unsigned DstReg = Inst.getOperand(0).getReg(); 4995 unsigned SrcReg = Inst.getOperand(1).getReg(); 4996 unsigned TmpReg = Inst.getOperand(2).getReg(); 5029 unsigned DstReg = Inst.getOperand(0).getReg(); 5030 unsigned SrcReg = Inst.getOperand(1).getReg(); 5031 unsigned TmpReg = Inst.getOperand(2).getReg(); 5055 unsigned FirstReg = Inst.getOperand(0).getReg(); 5057 unsigned BaseReg = Inst.getOperand(1).getReg(); 5063 assert(Inst.getOperand(2).isImm() && 5066 MCOperand &FirstOffset = Inst.getOperand(2); 5102 unsigned FirstReg = Inst.getOperand(0).getReg(); 5104 unsigned BaseReg = Inst.getOperand(1).getReg(); 5110 assert(Inst.getOperand(2).isImm() && 5113 MCOperand &FirstOffset = Inst.getOperand(2); 5134 assert(Inst.getOperand(0).isReg() && 5135 Inst.getOperand(1).isReg() && 5136 Inst.getOperand(2).isReg() && "Invalid instruction operand."); 5138 unsigned DstReg = Inst.getOperand(0).getReg(); 5139 unsigned SrcReg = Inst.getOperand(1).getReg(); 5140 unsigned OpReg = Inst.getOperand(2).getReg(); 5160 assert(Inst.getOperand(0).isReg() && 5161 Inst.getOperand(1).isReg() && 5162 Inst.getOperand(2).isImm() && "Invalid instruction operand."); 5164 unsigned DstReg = Inst.getOperand(0).getReg(); 5165 unsigned SrcReg = Inst.getOperand(1).getReg(); 5166 int64_t Imm = Inst.getOperand(2).getImm(); 5216 switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) { 5230 switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) { 5244 switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) { 5267 switch (Inst.getOperand(IsMFTC1 ? 1 : 0).getReg()) { 5306 switch (Inst.getOperand(IsMFTC0 ? 1 : 0).getReg()) { 5360 sel = Inst.getOperand(2).getImm(); 5366 rd = Inst.getOperand(IsMFTR ? 1 : 0).getReg(); 5404 unsigned Op0 = IsMFTR ? Inst.getOperand(0).getReg() : rd; 5407 : (Inst.getOpcode() != Mips::MTTDSP ? Inst.getOperand(1).getReg() 5408 : Inst.getOperand(0).getReg()); 5435 if (Inst.getOperand(1).getReg() == Mips::ZERO || 5436 Inst.getOperand(1).getReg() == Mips::ZERO_64) 5447 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) 5447 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) 5451 if (Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) 5451 if (Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) 5455 if (Inst.getOperand(0).getImm() != 0 && !hasMips32()) 5462 if (Inst.getOperand(2).getImm() != 0 && !hasMips32()) 5489 if (Inst.getOperand(0).getReg() == Mips::ZERO || 5490 Inst.getOperand(0).getReg() == Mips::ZERO_64) 5505 if (Inst.getOperand(0).getReg() == Mips::ZERO || 5506 Inst.getOperand(0).getReg() == Mips::ZERO_64) 5508 if (Inst.getOperand(1).getReg() == Mips::ZERO || 5509 Inst.getOperand(1).getReg() == Mips::ZERO_64) 5511 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) 5511 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) 5515 assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() && 5515 assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() && 5517 const signed Pos = Inst.getOperand(2).getImm(); 5518 const signed Size = Inst.getOperand(3).getImm(); 5525 assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() && 5525 assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() && 5527 const signed Pos = Inst.getOperand(2).getImm(); 5528 const signed Size = Inst.getOperand(3).getImm(); 5534 assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() && 5534 assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() && 5536 const signed Pos = Inst.getOperand(2).getImm(); 5537 const signed Size = Inst.getOperand(3).getImm(); 5544 assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() && 5544 assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() && 5546 const signed Pos = Inst.getOperand(2).getImm(); 5547 const signed Size = Inst.getOperand(3).getImm(); 5556 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) 5556 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) 5563 (Inst.getOperand(0).getReg() != Mips::FCC0) && !hasEightFccRegisters())lib/Target/Mips/Disassembler/MipsDisassembler.cpp
2368 int Pos = Inst.getOperand(2).getImm();
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp62 assert(Inst.getOperand(2).isImm()); 64 int64_t Shift = Inst.getOperand(2).getImm(); 70 Inst.getOperand(2).setImm(Shift); 95 unsigned RegOp0 = Inst.getOperand(0).getReg(); 96 unsigned RegOp1 = Inst.getOperand(1).getReg(); 116 Inst.getOperand(0).setReg(RegOp1); 117 Inst.getOperand(1).setReg(RegOp0);lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
725 TmpInst.addOperand(Inst.getOperand(0)); 726 TmpInst.addOperand(Inst.getOperand(1)); 734 TmpInst.addOperand(Inst.getOperand(2)); 735 TmpInst.addOperand(Inst.getOperand(0)); 736 TmpInst.addOperand(Inst.getOperand(1)); 744 TmpInst.addOperand(Inst.getOperand(2)); 745 TmpInst.addOperand(Inst.getOperand(0)); 746 TmpInst.addOperand(Inst.getOperand(1)); 762 TmpInst.addOperand(Inst.getOperand(0)); 763 TmpInst.addOperand(Inst.getOperand(1)); 770 TmpInst.addOperand(Inst.getOperand(0)); 771 TmpInst.addOperand(Inst.getOperand(2)); 772 TmpInst.addOperand(Inst.getOperand(1)); 779 TmpInst.addOperand(Inst.getOperand(0)); 780 TmpInst.addOperand(Inst.getOperand(1)); 781 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 788 TmpInst.addOperand(Inst.getOperand(0)); 789 TmpInst.addOperand(Inst.getOperand(1)); 790 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 797 TmpInst.addOperand(Inst.getOperand(0)); 798 TmpInst.addOperand(Inst.getOperand(1)); 799 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 806 TmpInst.addOperand(Inst.getOperand(0)); 807 TmpInst.addOperand(Inst.getOperand(1)); 808 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 815 int64_t N = Inst.getOperand(2).getImm(); 816 int64_t B = Inst.getOperand(3).getImm(); 818 TmpInst.addOperand(Inst.getOperand(0)); 819 TmpInst.addOperand(Inst.getOperand(1)); 829 int64_t N = Inst.getOperand(2).getImm(); 830 int64_t B = Inst.getOperand(3).getImm(); 832 TmpInst.addOperand(Inst.getOperand(0)); 833 TmpInst.addOperand(Inst.getOperand(1)); 843 int64_t N = Inst.getOperand(2).getImm(); 844 int64_t B = Inst.getOperand(3).getImm(); 846 TmpInst.addOperand(Inst.getOperand(0)); 847 TmpInst.addOperand(Inst.getOperand(0)); 848 TmpInst.addOperand(Inst.getOperand(1)); 858 int64_t N = Inst.getOperand(2).getImm(); 859 int64_t B = Inst.getOperand(3).getImm(); 861 TmpInst.addOperand(Inst.getOperand(0)); 862 TmpInst.addOperand(Inst.getOperand(0)); 863 TmpInst.addOperand(Inst.getOperand(1)); 873 int64_t N = Inst.getOperand(2).getImm(); 875 TmpInst.addOperand(Inst.getOperand(0)); 876 TmpInst.addOperand(Inst.getOperand(1)); 886 int64_t N = Inst.getOperand(2).getImm(); 888 TmpInst.addOperand(Inst.getOperand(0)); 889 TmpInst.addOperand(Inst.getOperand(1)); 899 int64_t N = Inst.getOperand(2).getImm(); 901 TmpInst.addOperand(Inst.getOperand(0)); 902 TmpInst.addOperand(Inst.getOperand(1)); 912 int64_t N = Inst.getOperand(2).getImm(); 914 TmpInst.addOperand(Inst.getOperand(0)); 915 TmpInst.addOperand(Inst.getOperand(1)); 925 int64_t B = Inst.getOperand(2).getImm(); 926 int64_t N = Inst.getOperand(3).getImm(); 928 TmpInst.addOperand(Inst.getOperand(0)); 929 TmpInst.addOperand(Inst.getOperand(1)); 939 int64_t N = Inst.getOperand(2).getImm(); 940 int64_t B = Inst.getOperand(3).getImm(); 942 TmpInst.addOperand(Inst.getOperand(0)); 943 TmpInst.addOperand(Inst.getOperand(1)); 952 int64_t N = Inst.getOperand(2).getImm(); 953 int64_t B = Inst.getOperand(3).getImm(); 955 TmpInst.addOperand(Inst.getOperand(0)); 956 TmpInst.addOperand(Inst.getOperand(1)); 965 int64_t N = Inst.getOperand(2).getImm(); 966 int64_t B = Inst.getOperand(3).getImm(); 968 TmpInst.addOperand(Inst.getOperand(0)); 969 TmpInst.addOperand(Inst.getOperand(0)); 970 TmpInst.addOperand(Inst.getOperand(1)); 979 int64_t N = Inst.getOperand(2).getImm(); 981 TmpInst.addOperand(Inst.getOperand(0)); 982 TmpInst.addOperand(Inst.getOperand(1)); 991 int64_t N = Inst.getOperand(2).getImm(); 993 TmpInst.addOperand(Inst.getOperand(0)); 994 TmpInst.addOperand(Inst.getOperand(1)); 1002 int64_t N = Inst.getOperand(1).getImm(); 1004 TmpInst.addOperand(Inst.getOperand(0)); 1012 int64_t N = Inst.getOperand(2).getImm(); 1014 TmpInst.addOperand(Inst.getOperand(0)); 1015 TmpInst.addOperand(Inst.getOperand(1)); 1024 int64_t N = Inst.getOperand(2).getImm(); 1026 TmpInst.addOperand(Inst.getOperand(0)); 1027 TmpInst.addOperand(Inst.getOperand(1)); 1036 int64_t B = Inst.getOperand(2).getImm(); 1037 int64_t N = Inst.getOperand(3).getImm(); 1039 TmpInst.addOperand(Inst.getOperand(0)); 1040 TmpInst.addOperand(Inst.getOperand(1)); 1049 int64_t BM = Inst.getOperand(3).getImm(); 1055 TmpInst.addOperand(Inst.getOperand(0)); 1056 TmpInst.addOperand(Inst.getOperand(1)); 1057 TmpInst.addOperand(Inst.getOperand(2)); 1066 int64_t BM = Inst.getOperand(3).getImm(); 1072 TmpInst.addOperand(Inst.getOperand(0)); 1073 TmpInst.addOperand(Inst.getOperand(0)); // The tied operand. 1074 TmpInst.addOperand(Inst.getOperand(1)); 1075 TmpInst.addOperand(Inst.getOperand(2)); 1084 int64_t BM = Inst.getOperand(3).getImm(); 1090 TmpInst.addOperand(Inst.getOperand(0)); 1091 TmpInst.addOperand(Inst.getOperand(1)); 1092 TmpInst.addOperand(Inst.getOperand(2)); 1109 TmpInst.addOperand(Inst.getOperand(0)); 1110 TmpInst.addOperand(Inst.getOperand(1)); 1121 TmpInst.addOperand(Inst.getOperand(0)); 1122 TmpInst.addOperand(Inst.getOperand(1));lib/Target/PowerPC/PPCAsmPrinter.cpp
629 unsigned PICR = TmpInst.getOperand(0).getReg(); 659 const MCOperand TR = TmpInst.getOperand(1); 660 const MCOperand PICR = TmpInst.getOperand(0); 663 TmpInst.getOperand(1) = 665 TmpInst.getOperand(0) = TR; 666 TmpInst.getOperand(2) = PICR; 670 TmpInst.getOperand(0) = PICR; 671 TmpInst.getOperand(1) = TR; 672 TmpInst.getOperand(2) = PICR; 699 TmpInst.getOperand(1) = MCOperand::createExpr(Exp); 718 TmpInst.getOperand(1) = MCOperand::createExpr(Exp); 728 TmpInst.getOperand(1) = MCOperand::createExpr(Exp); 758 TmpInst.getOperand(1) = MCOperand::createExpr(Exp); 788 TmpInst.getOperand(2) = MCOperand::createExpr(Exp); 818 TmpInst.getOperand(1) = MCOperand::createExpr(Exp); 858 TmpInst.getOperand(2) = MCOperand::createExpr(Exp); 893 TmpInst.getOperand(1) = MCOperand::createExpr(Exp); 916 TmpInst.getOperand(2) = MCOperand::createExpr(Exp); 950 TmpInst.getOperand(1) = MCOperand::createExpr(Exp);lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
1651 MCOperand DestReg = Inst.getOperand(0); 1652 const MCExpr *Symbol = Inst.getOperand(1).getExpr(); 1668 MCOperand DestReg = Inst.getOperand(0); 1669 const MCExpr *Symbol = Inst.getOperand(1).getExpr(); 1691 MCOperand DestReg = Inst.getOperand(0); 1692 const MCExpr *Symbol = Inst.getOperand(1).getExpr(); 1706 MCOperand DestReg = Inst.getOperand(0); 1707 const MCExpr *Symbol = Inst.getOperand(1).getExpr(); 1722 MCOperand DestReg = Inst.getOperand(0); 1725 MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); 1726 const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); 1734 assert(Inst.getOperand(2).isReg() && "Unexpected second operand kind"); 1735 if (Inst.getOperand(2).getReg() != RISCV::X4) { 1753 Register Reg = Inst.getOperand(0).getReg(); 1754 const MCOperand &Op1 = Inst.getOperand(1); 1764 int64_t Imm = Inst.getOperand(1).getImm();lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
286 Inst.addOperand(Inst.getOperand(0)); 310 Inst.addOperand(Inst.getOperand(0));lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
508 MCOperand MCRegOp = Inst.getOperand(0); 509 MCOperand MCValOp = Inst.getOperand(1); 514 bool IsImm = Inst.getOperand(1).isImm();lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
797 auto &Op0 = Inst.getOperand(0);
lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp 336 auto &MO = OutMI.getOperand(I - 1);
lib/Target/X86/AsmParser/X86AsmParser.cpp2894 MRI->getEncodingValue(Inst.getOperand(0).getReg()) >= 8 || 2895 MRI->getEncodingValue(Inst.getOperand(1).getReg()) < 8) 2923 MRI->getEncodingValue(Inst.getOperand(0).getReg()) >= 8 || 2924 MRI->getEncodingValue(Inst.getOperand(2).getReg()) < 8) 2959 unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 2960 unsigned Mask = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 2962 MRI->getEncodingValue(Inst.getOperand(3 + X86::AddrIndexReg).getReg()); 2992 unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 2994 MRI->getEncodingValue(Inst.getOperand(4 + X86::AddrIndexReg).getReg()); 3018 unsigned Src2 = Inst.getOperand(Inst.getNumOperands() -lib/Target/X86/X86MCInstLower.cpp
294 assert(Inst.getOperand(0).isReg() && 295 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && 295 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && 296 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && 297 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) || 297 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) || 302 unsigned Reg = Inst.getOperand(0).getReg(); 307 MCOperand Saved = Inst.getOperand(ImmOp); 317 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg(); 317 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg(); 349 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg(); 349 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg(); 354 Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && 355 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && 356 Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && 357 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && 358 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && 359 (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) && 359 (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) && 363 unsigned Reg = Inst.getOperand(RegOp).getReg(); 371 if (Inst.getOperand(AddrOp).isExpr()) { 372 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr(); 379 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 || 380 Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 || 381 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0)) 385 MCOperand Saved = Inst.getOperand(AddrOp); 386 MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg); 481 assert(OutMI.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 && 500 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) && 501 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) { 525 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) && 526 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) { 569 if (OutMI.getOperand(OutMI.getNumOperands() - 1).getImm() == 0) { 635 OutMI.erase(&OutMI.getOperand(OutMI.getNumOperands() - 1)); 640 if (OutMI.getOperand(OutMI.getNumOperands() - 1).getImm() == 6) { 706 OutMI.erase(&OutMI.getOperand(OutMI.getNumOperands() - 1));tools/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
1189 const uint32_t imm16 = insn.getOperand(2).getImm(); 1192 dst = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1193 src = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); 1237 uint32_t imm16 = insn.getOperand(2).getImm(); 1245 src = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1246 base = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); 1305 src = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1306 base = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); 1307 imm = insn.getOperand(2).getImm(); 1356 dst = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1357 src = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); 1361 rt = m_reg_info->getEncodingValue(insn.getOperand(2).getReg()); 1392 rt = m_reg_info->getEncodingValue(insn.getOperand(2).getReg()); 1428 const uint32_t imm32 = insn.getOperand(1).getImm() << 16; 1433 rt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1443 const uint32_t imm9 = insn.getOperand(0).getImm(); 1470 const uint32_t imm4 = insn.getOperand(2).getImm(); 1474 base = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1502 uint32_t imm5 = insn.getOperand(2).getImm(); 1507 src = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1508 base = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); 1573 m_reg_info->getEncodingValue(insn.getOperand(num_operands - 2).getReg()); 1581 uint32_t offset = insn.getOperand(num_operands - 1).getImm(); 1602 src = m_reg_info->getEncodingValue(insn.getOperand(i).getReg()); 1644 uint32_t src = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1645 uint32_t base = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); 1646 uint32_t imm5 = insn.getOperand(2).getImm(); 1698 uint32_t imm = insn.getOperand(num_operands - 1) 1703 m_reg_info->getEncodingValue(insn.getOperand(num_operands - 2).getReg()); 1723 dst = m_reg_info->getEncodingValue(insn.getOperand(i).getReg()); 1752 int32_t imm5 = insn.getOperand(0).getImm(); 1808 rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1809 rt = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); 1810 offset = insn.getOperand(2).getImm(); 1858 rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1859 rt = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); 1860 offset = insn.getOperand(2).getImm(); 1937 rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1938 offset = insn.getOperand(1).getImm(); 2006 rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 2007 offset = insn.getOperand(1).getImm(); 2056 rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 2057 offset = insn.getOperand(1).getImm(); 2110 rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 2111 offset = insn.getOperand(1).getImm(); 2167 offset = insn.getOperand(0).getImm(); 2214 uint32_t rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 2215 int32_t offset = insn.getOperand(1).getImm(); 2295 uint32_t rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 2344 offset = insn.getOperand(0).getImm(); 2385 rt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 2386 rs = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); 2421 offset = insn.getOperand(0).getImm(); 2452 offset = insn.getOperand(0).getImm(); 2482 offset = insn.getOperand(0).getImm(); 2505 offset = insn.getOperand(0).getImm(); 2528 offset = insn.getOperand(0).getImm(); 2560 rt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 2561 rs = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); 2596 rt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 2597 offset = insn.getOperand(1).getImm(); 2633 rt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 2634 offset = insn.getOperand(1).getImm(); 2658 rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 2682 cc = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 2683 offset = insn.getOperand(1).getImm(); 2726 ft = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 2727 offset = insn.getOperand(1).getImm(); 2762 ft = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 2763 offset = insn.getOperand(1).getImm(); 2798 cc = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 2799 offset = insn.getOperand(1).getImm(); 2884 uint32_t wt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 2885 int32_t offset = insn.getOperand(1).getImm(); 2953 uint32_t wt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 2954 int32_t offset = insn.getOperand(1).getImm(); 2987 m_reg_info->getEncodingValue(insn.getOperand(num_operands - 2).getReg()); 2988 imm = insn.getOperand(num_operands - 1).getImm(); 3020 m_reg_info->getEncodingValue(insn.getOperand(num_operands - 2).getReg()); 3022 m_reg_info->getEncodingValue(insn.getOperand(num_operands - 1).getReg());tools/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
1081 const uint32_t imm16 = insn.getOperand(2).getImm(); 1084 dst = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1085 src = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); 1144 uint32_t imm16 = insn.getOperand(2).getImm(); 1149 src = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1150 base = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); 1202 src = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1203 base = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); 1204 imm = insn.getOperand(2).getImm(); 1246 const uint32_t imm32 = insn.getOperand(1).getImm() << 16; 1251 rt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1269 dst = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1270 src = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); 1274 rt = m_reg_info->getEncodingValue(insn.getOperand(2).getReg()); 1305 rt = m_reg_info->getEncodingValue(insn.getOperand(2).getReg()); 1348 rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1349 rt = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); 1350 offset = insn.getOperand(2).getImm(); 1400 rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1401 offset = insn.getOperand(1).getImm(); 1448 offset = insn.getOperand(0).getImm(); 1479 offset = insn.getOperand(0).getImm(); 1510 rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1511 offset = insn.getOperand(1).getImm(); 1578 rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1579 offset = insn.getOperand(1).getImm(); 1633 offset = insn.getOperand(0).getImm(); 1664 rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1665 rt = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); 1666 offset = insn.getOperand(2).getImm(); 1744 rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1745 offset = insn.getOperand(1).getImm(); 1805 offset = insn.getOperand(0).getImm(); 1829 offset = insn.getOperand(0).getImm(); 1861 rt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1862 rs = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); 1897 rt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1898 offset = insn.getOperand(1).getImm(); 1934 rt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1935 offset = insn.getOperand(1).getImm(); 1959 rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1990 cc = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 1991 offset = insn.getOperand(1).getImm(); 2036 ft = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 2037 offset = insn.getOperand(1).getImm(); 2072 ft = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 2073 offset = insn.getOperand(1).getImm(); 2108 cc = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 2109 offset = insn.getOperand(1).getImm(); 2195 uint32_t wt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 2196 int64_t offset = insn.getOperand(1).getImm(); 2264 uint32_t wt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); 2265 int64_t offset = insn.getOperand(1).getImm(); 2298 m_reg_info->getEncodingValue(insn.getOperand(num_operands - 2).getReg()); 2299 imm = insn.getOperand(num_operands - 1).getImm(); 2331 m_reg_info->getEncodingValue(insn.getOperand(num_operands - 2).getReg()); 2333 m_reg_info->getEncodingValue(insn.getOperand(num_operands - 1).getReg());unittests/ExecutionEngine/JITLink/JITLinkTestCommon.cpp
229 auto &Op = InstAndSize->first.getOperand(OpIdx);