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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc29713 class MCInst;
gen/lib/Target/X86/X86GenInstrInfo.inc80098 class MCInst;
include/llvm/CodeGen/AsmPrinter.h 64 class MCInst;
include/llvm/CodeGen/TargetInstrInfo.h 50 class MCInst;
include/llvm/MC/MCAsmBackend.h 30 class MCInst;
include/llvm/MC/MCCodeEmitter.h 15 class MCInst;
include/llvm/MC/MCCodePadder.h 22 class MCInst;
include/llvm/MC/MCDisassembler/MCDisassembler.h 21 class MCInst;
include/llvm/MC/MCDisassembler/MCSymbolizer.h 26 class MCInst;
include/llvm/MC/MCELFStreamer.h 21 class MCInst;
include/llvm/MC/MCInst.h 28 class MCInst;
include/llvm/MC/MCInstPrinter.h 18 class MCInst;
include/llvm/MC/MCInstrDesc.h 22 class MCInst;
include/llvm/MC/MCParser/MCTargetAsmParser.h 26 class MCInst;
include/llvm/MC/MCSchedule.h 28 class MCInst;
include/llvm/MC/MCStreamer.h 47 class MCInst;
include/llvm/MC/MCSubtargetInfo.h 29 class MCInst;
include/llvm/MC/MCWasmStreamer.h 24 class MCInst;
include/llvm/MC/MCWinCOFFStreamer.h 20 class MCInst;
lib/Target/AArch64/AArch64MCInstLower.h 19 class MCInst;
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h 31 class MCInst;
lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.h 22 class MCInst;
lib/Target/ARC/ARCMCInstLower.h 18 class MCInst;
lib/Target/ARM/ARM.h 35 class MCInst;
lib/Target/AVR/AVRMCInstLower.h 20 class MCInst;
lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h 30 class MCInst;
lib/Target/BPF/BPFMCInstLower.h 17 class MCInst;
lib/Target/Hexagon/HexagonAsmPrinter.h 25 class MCInst;
lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h 28 class MCInst;
lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h 28 class MCInst;
lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.h 15 class MCInst;
lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.h 24 class MCInst;
lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h 30 class MCInst;
lib/Target/Lanai/LanaiMCInstLower.h 17 class MCInst;
lib/Target/MSP430/MSP430MCInstLower.h 17 class MCInst;
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h 24 class MCInst;
lib/Target/Mips/MipsMCInstLower.h 21 class MCInst;
lib/Target/PowerPC/PPC.h 29 class MCInst;
lib/Target/RISCV/RISCV.h 27 class MCInst;
lib/Target/Sparc/Sparc.h 26 class MCInst;
lib/Target/SystemZ/SystemZMCInstLower.h 17 class MCInst;
lib/Target/X86/MCTargetDesc/X86InstComments.h 19 class MCInst;
lib/Target/XCore/XCoreMCInstLower.h 16 class MCInst;
tools/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h 20 class MCInst;
tools/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h 23 class MCInst;
References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
20 MCInst &Inst,
26 MCInst &Inst,
6461 convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
27404 MCInst &Inst,
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc 11 void AArch64InstPrinter::printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O) {
14801 bool AArch64InstPrinter::printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &OS) {
26780 const MCInst *MI, unsigned OpIdx,
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc 11 void AArch64AppleInstPrinter::printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O) {
15517 bool AArch64AppleInstPrinter::printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &OS) {
27496 const MCInst *MI, unsigned OpIdx,
gen/lib/Target/AArch64/AArch64GenDisassemblerTables.inc20641 static DecodeStatus decodeToMCInst(DecodeStatus S, unsigned Idx, InsnType insn, MCInst &MI,
25718 static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
25834 MCInst TmpMI;
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc29717 bool isExynosArithFast(const MCInst &MI);
29718 bool isExynosCheapAsMove(const MCInst &MI);
29719 bool isExynosLogicExFast(const MCInst &MI);
29720 bool isExynosLogicFast(const MCInst &MI);
29721 bool isExynosResetFast(const MCInst &MI);
29722 bool isExynosScaledAddr(const MCInst &MI);
29723 bool isCopyIdiom(const MCInst &MI);
29724 bool isZeroFPIdiom(const MCInst &MI);
29725 bool isZeroIdiom(const MCInst &MI);
29726 bool hasExtendedReg(const MCInst &MI);
29727 bool hasShiftedReg(const MCInst &MI);
29728 bool isScaledAddr(const MCInst &MI);
29741 bool isExynosArithFast(const MCInst &MI) {
29802 bool isExynosCheapAsMove(const MCInst &MI) {
29828 bool isExynosLogicExFast(const MCInst &MI) {
29885 bool isExynosLogicFast(const MCInst &MI) {
29936 bool isExynosResetFast(const MCInst &MI) {
29962 bool isExynosScaledAddr(const MCInst &MI) {
30018 bool isCopyIdiom(const MCInst &MI) {
30049 bool isZeroFPIdiom(const MCInst &MI) {
30069 bool isZeroIdiom(const MCInst &MI) {
30086 bool hasExtendedReg(const MCInst &MI) {
30106 bool hasShiftedReg(const MCInst &MI) {
30138 bool isScaledAddr(const MCInst &MI) {
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc 9 uint64_t AArch64MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
15936 const MCInst &Inst, const FeatureBitset &AvailableFeatures) const {
gen/lib/Target/AArch64/AArch64GenSubtargetInfo.inc13013 const MCInst *MI, unsigned CPUID) {
17773 const MCInst *MI, unsigned CPUID) const override {
17966 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
17973 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
22889 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
21 MCInst &Inst,
27 MCInst &Inst,
3777 convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
23922 MCInst &Inst,
gen/lib/Target/AMDGPU/AMDGPUGenAsmWriter.inc 11 void AMDGPUInstPrinter::printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O) {
gen/lib/Target/AMDGPU/AMDGPUGenDisassemblerTables.inc32905 static DecodeStatus decodeToMCInst(DecodeStatus S, unsigned Idx, InsnType insn, MCInst &MI,
41982 static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
42098 MCInst TmpMI;
gen/lib/Target/AMDGPU/AMDGPUGenMCCodeEmitter.inc 9 uint64_t AMDGPUMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
35089 const MCInst &Inst, const FeatureBitset &AvailableFeatures) const {
gen/lib/Target/AMDGPU/AMDGPUGenMCPseudoLowering.inc 15 MCInst TmpInst;
gen/lib/Target/AMDGPU/AMDGPUGenSubtargetInfo.inc 593 const MCInst *MI, unsigned CPUID) {
632 const MCInst *MI, unsigned CPUID) const override {
780 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
787 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
859 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/AMDGPU/R600GenAsmWriter.inc 11 void R600InstPrinter::printInstruction(const MCInst *MI, raw_ostream &O) {
gen/lib/Target/AMDGPU/R600GenMCCodeEmitter.inc 9 uint64_t R600MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
1795 const MCInst &Inst, const FeatureBitset &AvailableFeatures) const {
gen/lib/Target/AMDGPU/R600GenSubtargetInfo.inc 227 const MCInst *MI, unsigned CPUID) {
245 const MCInst *MI, unsigned CPUID) const override {
304 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
311 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
344 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/ARC/ARCGenAsmWriter.inc 11 void ARCInstPrinter::printInstruction(const MCInst *MI, raw_ostream &O) {
gen/lib/Target/ARC/ARCGenDisassemblerTables.inc 1021 static DecodeStatus decodeToMCInst(DecodeStatus S, unsigned Idx, InsnType insn, MCInst &MI,
1453 static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
1569 MCInst TmpMI;
gen/lib/Target/ARC/ARCGenSubtargetInfo.inc 75 const MCInst *MI, unsigned CPUID) {
93 const MCInst *MI, unsigned CPUID) const override {
130 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
137 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
167 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/ARM/ARMGenAsmMatcher.inc 15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
20 MCInst &Inst,
4345 convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
15075 MCInst &Inst,
gen/lib/Target/ARM/ARMGenAsmWriter.inc 11 void ARMInstPrinter::printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O) {
12059 bool ARMInstPrinter::printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &OS) {
12842 const MCInst *MI, unsigned OpIdx,
gen/lib/Target/ARM/ARMGenDisassemblerTables.inc16758 static DecodeStatus decodeToMCInst(DecodeStatus S, unsigned Idx, InsnType insn, MCInst &MI,
21760 static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
21876 MCInst TmpMI;
gen/lib/Target/ARM/ARMGenMCCodeEmitter.inc 9 uint64_t ARMMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
gen/lib/Target/ARM/ARMGenMCPseudoLowering.inc 15 MCInst TmpInst;
28 MCInst TmpInst;
53 MCInst TmpInst;
80 MCInst TmpInst;
97 MCInst TmpInst;
121 MCInst TmpInst;
154 MCInst TmpInst;
181 MCInst TmpInst;
194 MCInst TmpInst;
204 MCInst TmpInst;
221 MCInst TmpInst;
254 MCInst TmpInst;
281 MCInst TmpInst;
296 MCInst TmpInst;
311 MCInst TmpInst;
336 MCInst TmpInst;
353 MCInst TmpInst;
367 MCInst TmpInst;
382 MCInst TmpInst;
397 MCInst TmpInst;
419 MCInst TmpInst;
438 MCInst TmpInst;
453 MCInst TmpInst;
468 MCInst TmpInst;
gen/lib/Target/ARM/ARMGenSubtargetInfo.inc18302 const MCInst *MI, unsigned CPUID) {
19352 const MCInst *MI, unsigned CPUID) const override {
19566 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
19573 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
23256 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/AVR/AVRGenAsmMatcher.inc 15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
20 MCInst &Inst,
26 MCInst &Inst,
494 convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
1258 MCInst &Inst,
gen/lib/Target/AVR/AVRGenAsmWriter.inc 11 void AVRInstPrinter::printInstruction(const MCInst *MI, raw_ostream &O) {
1054 bool AVRInstPrinter::printAliasInstr(const MCInst *MI, raw_ostream &OS) {
1324 const MCInst *MI, unsigned OpIdx,
gen/lib/Target/AVR/AVRGenDisassemblerTables.inc 427 static DecodeStatus decodeToMCInst(DecodeStatus S, unsigned Idx, InsnType insn, MCInst &MI,
575 static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
691 MCInst TmpMI;
gen/lib/Target/AVR/AVRGenMCCodeEmitter.inc 9 uint64_t AVRMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
gen/lib/Target/AVR/AVRGenSubtargetInfo.inc 423 const MCInst *MI, unsigned CPUID) {
441 const MCInst *MI, unsigned CPUID) const override {
531 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
538 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
568 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/BPF/BPFGenAsmMatcher.inc 15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
20 MCInst &Inst,
26 MCInst &Inst,
266 convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
898 MCInst &Inst,
gen/lib/Target/BPF/BPFGenAsmWriter.inc 11 void BPFInstPrinter::printInstruction(const MCInst *MI, raw_ostream &O) {
gen/lib/Target/BPF/BPFGenDisassemblerTables.inc 332 static DecodeStatus decodeToMCInst(DecodeStatus S, unsigned Idx, InsnType insn, MCInst &MI,
512 static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
628 MCInst TmpMI;
gen/lib/Target/BPF/BPFGenMCCodeEmitter.inc 9 uint64_t BPFMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
659 const MCInst &Inst, const FeatureBitset &AvailableFeatures) const {
gen/lib/Target/BPF/BPFGenSubtargetInfo.inc 93 const MCInst *MI, unsigned CPUID) {
111 const MCInst *MI, unsigned CPUID) const override {
153 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
160 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
190 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc 15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
20 MCInst &Inst,
26 MCInst &Inst,
2543 convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
10244 MCInst &Inst,
gen/lib/Target/Hexagon/HexagonGenAsmWriter.inc 11 void HexagonInstPrinter::printInstruction(const MCInst *MI, raw_ostream &O) {
gen/lib/Target/Hexagon/HexagonGenDisassemblerTables.inc 8543 static DecodeStatus decodeToMCInst(DecodeStatus S, unsigned Idx, InsnType insn, MCInst &MI,
12199 static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
12315 MCInst TmpMI;
gen/lib/Target/Hexagon/HexagonGenMCCodeEmitter.inc 9 uint64_t HexagonMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
11653 const MCInst &Inst, const FeatureBitset &AvailableFeatures) const {
gen/lib/Target/Hexagon/HexagonGenSubtargetInfo.inc 4590 const MCInst *MI, unsigned CPUID) {
4608 const MCInst *MI, unsigned CPUID) const override {
4677 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
4684 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
4718 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/Lanai/LanaiGenAsmMatcher.inc 15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
20 MCInst &Inst,
26 MCInst &Inst,
342 convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
1042 MCInst &Inst,
gen/lib/Target/Lanai/LanaiGenAsmWriter.inc 11 void LanaiInstPrinter::printInstruction(const MCInst *MI, raw_ostream &O) {
899 bool LanaiInstPrinter::printAliasInstr(const MCInst *MI, raw_ostream &OS) {
998 const MCInst *MI, unsigned OpIdx,
gen/lib/Target/Lanai/LanaiGenDisassemblerTables.inc 312 static DecodeStatus decodeToMCInst(DecodeStatus S, unsigned Idx, InsnType insn, MCInst &MI,
453 static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
569 MCInst TmpMI;
gen/lib/Target/Lanai/LanaiGenMCCodeEmitter.inc 9 uint64_t LanaiMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
gen/lib/Target/Lanai/LanaiGenSubtargetInfo.inc 156 const MCInst *MI, unsigned CPUID) {
174 const MCInst *MI, unsigned CPUID) const override {
211 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
218 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
251 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/MSP430/MSP430GenAsmMatcher.inc 15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
20 MCInst &Inst,
26 MCInst &Inst,
327 convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
1100 MCInst &Inst,
gen/lib/Target/MSP430/MSP430GenAsmWriter.inc 11 void MSP430InstPrinter::printInstruction(const MCInst *MI, raw_ostream &O) {
767 bool MSP430InstPrinter::printAliasInstr(const MCInst *MI, raw_ostream &OS) {
1263 const MCInst *MI, unsigned OpIdx,
gen/lib/Target/MSP430/MSP430GenDisassemblerTables.inc 1042 static DecodeStatus decodeToMCInst(DecodeStatus S, unsigned Idx, InsnType insn, MCInst &MI,
1330 static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
1446 MCInst TmpMI;
gen/lib/Target/MSP430/MSP430GenMCCodeEmitter.inc 9 uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
gen/lib/Target/MSP430/MSP430GenSubtargetInfo.inc 154 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
161 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
191 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
20 MCInst &Inst,
26 MCInst &Inst,
1323 convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
8076 MCInst &Inst,
gen/lib/Target/Mips/MipsGenAsmWriter.inc 11 void MipsInstPrinter::printInstruction(const MCInst *MI, raw_ostream &O) {
7479 bool MipsInstPrinter::printAliasInstr(const MCInst *MI, raw_ostream &OS) {
9786 const MCInst *MI, unsigned OpIdx,
gen/lib/Target/Mips/MipsGenDisassemblerTables.inc 7623 static DecodeStatus decodeToMCInst(DecodeStatus S, unsigned Idx, InsnType insn, MCInst &MI,
10310 static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
10426 MCInst TmpMI;
gen/lib/Target/Mips/MipsGenMCCodeEmitter.inc 9 uint64_t MipsMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
gen/lib/Target/Mips/MipsGenMCPseudoLowering.inc 15 MCInst TmpInst;
31 MCInst TmpInst;
47 MCInst TmpInst;
63 MCInst TmpInst;
77 MCInst TmpInst;
89 MCInst TmpInst;
101 MCInst TmpInst;
120 MCInst TmpInst;
139 MCInst TmpInst;
158 MCInst TmpInst;
177 MCInst TmpInst;
196 MCInst TmpInst;
210 MCInst TmpInst;
226 MCInst TmpInst;
242 MCInst TmpInst;
254 MCInst TmpInst;
266 MCInst TmpInst;
278 MCInst TmpInst;
290 MCInst TmpInst;
300 MCInst TmpInst;
313 MCInst TmpInst;
329 MCInst TmpInst;
345 MCInst TmpInst;
361 MCInst TmpInst;
377 MCInst TmpInst;
393 MCInst TmpInst;
409 MCInst TmpInst;
422 MCInst TmpInst;
435 MCInst TmpInst;
448 MCInst TmpInst;
461 MCInst TmpInst;
474 MCInst TmpInst;
487 MCInst TmpInst;
500 MCInst TmpInst;
513 MCInst TmpInst;
526 MCInst TmpInst;
539 MCInst TmpInst;
549 MCInst TmpInst;
559 MCInst TmpInst;
571 MCInst TmpInst;
583 MCInst TmpInst;
593 MCInst TmpInst;
603 MCInst TmpInst;
613 MCInst TmpInst;
623 MCInst TmpInst;
633 MCInst TmpInst;
643 MCInst TmpInst;
656 MCInst TmpInst;
669 MCInst TmpInst;
682 MCInst TmpInst;
695 MCInst TmpInst;
708 MCInst TmpInst;
721 MCInst TmpInst;
734 MCInst TmpInst;
747 MCInst TmpInst;
760 MCInst TmpInst;
773 MCInst TmpInst;
786 MCInst TmpInst;
799 MCInst TmpInst;
815 MCInst TmpInst;
831 MCInst TmpInst;
844 MCInst TmpInst;
857 MCInst TmpInst;
870 MCInst TmpInst;
880 MCInst TmpInst;
892 MCInst TmpInst;
902 MCInst TmpInst;
912 MCInst TmpInst;
924 MCInst TmpInst;
934 MCInst TmpInst;
944 MCInst TmpInst;
954 MCInst TmpInst;
964 MCInst TmpInst;
974 MCInst TmpInst;
984 MCInst TmpInst;
994 MCInst TmpInst;
1004 MCInst TmpInst;
1015 MCInst TmpInst;
1026 MCInst TmpInst;
1039 MCInst TmpInst;
1055 MCInst TmpInst;
1071 MCInst TmpInst;
gen/lib/Target/Mips/MipsGenSubtargetInfo.inc 3750 const MCInst *MI, unsigned CPUID) {
3768 const MCInst *MI, unsigned CPUID) const override {
3857 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
3864 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
4056 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/NVPTX/NVPTXGenAsmWriter.inc 11 void NVPTXInstPrinter::printInstruction(const MCInst *MI, raw_ostream &O) {
gen/lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc 147 const MCInst *MI, unsigned CPUID) {
165 const MCInst *MI, unsigned CPUID) const override {
229 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
236 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
266 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/PowerPC/PPCGenAsmMatcher.inc 15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
20 MCInst &Inst,
26 MCInst &Inst,
2079 convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
7002 MCInst &Inst,
gen/lib/Target/PowerPC/PPCGenAsmWriter.inc 11 void PPCInstPrinter::printInstruction(const MCInst *MI, raw_ostream &O) {
6914 bool PPCInstPrinter::printAliasInstr(const MCInst *MI, raw_ostream &OS) {
11598 const MCInst *MI, unsigned OpIdx,
gen/lib/Target/PowerPC/PPCGenDisassemblerTables.inc 4786 static DecodeStatus decodeToMCInst(DecodeStatus S, unsigned Idx, InsnType insn, MCInst &MI,
6560 static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
6676 MCInst TmpMI;
gen/lib/Target/PowerPC/PPCGenMCCodeEmitter.inc 9 uint64_t PPCMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
6279 const MCInst &Inst, const FeatureBitset &AvailableFeatures) const {
gen/lib/Target/PowerPC/PPCGenSubtargetInfo.inc 8072 const MCInst *MI, unsigned CPUID) {
8090 const MCInst *MI, unsigned CPUID) const override {
8206 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
8213 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
8246 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/RISCV/RISCVGenAsmMatcher.inc 15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
20 MCInst &Inst,
26 MCInst &Inst,
948 convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
2391 MCInst &Inst,
gen/lib/Target/RISCV/RISCVGenAsmWriter.inc 11 void RISCVInstPrinter::printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O) {
1604 bool RISCVInstPrinter::printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &OS) {
2794 const MCInst *MI, unsigned OpIdx,
gen/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc 123 static bool compressInst(MCInst& OutInst,
124 const MCInst &MI,
956 static bool uncompressInst(MCInst& OutInst,
957 const MCInst &MI,
gen/lib/Target/RISCV/RISCVGenDisassemblerTables.inc 1161 static DecodeStatus decodeToMCInst(DecodeStatus S, unsigned Idx, InsnType insn, MCInst &MI,
1736 static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
1852 MCInst TmpMI;
gen/lib/Target/RISCV/RISCVGenMCCodeEmitter.inc 9 uint64_t RISCVMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
gen/lib/Target/RISCV/RISCVGenMCPseudoLowering.inc 15 MCInst TmpInst;
27 MCInst TmpInst;
42 MCInst TmpInst;
56 MCInst TmpInst;
69 MCInst TmpInst;
gen/lib/Target/RISCV/RISCVGenSubtargetInfo.inc 164 const MCInst *MI, unsigned CPUID) {
182 const MCInst *MI, unsigned CPUID) const override {
267 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
274 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
305 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/Sparc/SparcGenAsmMatcher.inc 15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
20 MCInst &Inst,
26 MCInst &Inst,
1567 convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
4135 MCInst &Inst,
gen/lib/Target/Sparc/SparcGenAsmWriter.inc 11 void SparcInstPrinter::printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O) {
1567 bool SparcInstPrinter::printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &OS) {
7644 const MCInst *MI, unsigned OpIdx,
gen/lib/Target/Sparc/SparcGenDisassemblerTables.inc 1782 static DecodeStatus decodeToMCInst(DecodeStatus S, unsigned Idx, InsnType insn, MCInst &MI,
2358 static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
2474 MCInst TmpMI;
gen/lib/Target/Sparc/SparcGenMCCodeEmitter.inc 9 uint64_t SparcMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
1747 const MCInst &Inst, const FeatureBitset &AvailableFeatures) const {
gen/lib/Target/Sparc/SparcGenSubtargetInfo.inc 447 const MCInst *MI, unsigned CPUID) {
465 const MCInst *MI, unsigned CPUID) const override {
523 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
530 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
563 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/SystemZ/SystemZGenAsmMatcher.inc 15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
20 MCInst &Inst,
26 MCInst &Inst,
1340 convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
5333 MCInst &Inst,
gen/lib/Target/SystemZ/SystemZGenAsmWriter.inc 11 void SystemZInstPrinter::printInstruction(const MCInst *MI, raw_ostream &O) {
gen/lib/Target/SystemZ/SystemZGenDisassemblerTables.inc 6951 static DecodeStatus decodeToMCInst(DecodeStatus S, unsigned Idx, InsnType insn, MCInst &MI,
10731 static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
10847 MCInst TmpMI;
gen/lib/Target/SystemZ/SystemZGenMCCodeEmitter.inc 9 uint64_t SystemZMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
8975 const MCInst &Inst, const FeatureBitset &AvailableFeatures) const {
gen/lib/Target/SystemZ/SystemZGenSubtargetInfo.inc 5076 const MCInst *MI, unsigned CPUID) {
5094 const MCInst *MI, unsigned CPUID) const override {
5168 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
5175 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
5205 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/WebAssembly/WebAssemblyGenAsmMatcher.inc 15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
20 MCInst &Inst,
26 MCInst &Inst,
157 convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
1102 MCInst &Inst,
gen/lib/Target/WebAssembly/WebAssemblyGenAsmWriter.inc 11 void WebAssemblyInstPrinter::printInstruction(const MCInst *MI, raw_ostream &O) {
gen/lib/Target/WebAssembly/WebAssemblyGenMCCodeEmitter.inc 9 uint64_t WebAssemblyMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
gen/lib/Target/WebAssembly/WebAssemblyGenSubtargetInfo.inc 105 const MCInst *MI, unsigned CPUID) {
123 const MCInst *MI, unsigned CPUID) const override {
172 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
179 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
209 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
gen/lib/Target/X86/X86GenAsmMatcher.inc 15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
20 MCInst &Inst,
26 MCInst &Inst,
4938 convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
36929 MCInst &Inst,
gen/lib/Target/X86/X86GenAsmWriter.inc 11 void X86ATTInstPrinter::printInstruction(const MCInst *MI, raw_ostream &O) {
48846 bool X86ATTInstPrinter::printAliasInstr(const MCInst *MI, raw_ostream &OS) {
48907 const MCInst *MI, unsigned OpIdx,
gen/lib/Target/X86/X86GenAsmWriter1.inc 11 void X86IntelInstPrinter::printInstruction(const MCInst *MI, raw_ostream &O) {
33172 bool X86IntelInstPrinter::printAliasInstr(const MCInst *MI, raw_ostream &OS) {
33233 const MCInst *MI, unsigned OpIdx,
gen/lib/Target/X86/X86GenInstrInfo.inc80102 bool isThreeOperandsLEA(const MCInst &MI);
80115 bool isThreeOperandsLEA(const MCInst &MI) {
gen/lib/Target/X86/X86GenSubtargetInfo.inc19920 const MCInst *MI, unsigned CPUID) {
21320 const MCInst *MI, unsigned CPUID) const override {
21491 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
21498 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
22913 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
23087 bool isZeroIdiom(const MCInst &MI, APInt &Mask, unsigned ProcessorID) const override;
23088 bool isDependencyBreaking(const MCInst &MI, APInt &Mask, unsigned ProcessorID) const override;
23089 bool isOptimizableRegisterMove(const MCInst &MI, unsigned ProcessorID) const override;
23096 bool X86MCInstrAnalysis::isZeroIdiom(const MCInst &MI, APInt &Mask, unsigned ProcessorID) const {
23183 bool X86MCInstrAnalysis::isDependencyBreaking(const MCInst &MI, APInt &Mask, unsigned ProcessorID) const {
23227 bool X86MCInstrAnalysis::isOptimizableRegisterMove(const MCInst &MI, unsigned ProcessorID) const {
gen/lib/Target/XCore/XCoreGenAsmWriter.inc 11 void XCoreInstPrinter::printInstruction(const MCInst *MI, raw_ostream &O) {
gen/lib/Target/XCore/XCoreGenDisassemblerTables.inc 641 static DecodeStatus decodeToMCInst(DecodeStatus S, unsigned Idx, InsnType insn, MCInst &MI,
802 static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
918 MCInst TmpMI;
gen/lib/Target/XCore/XCoreGenSubtargetInfo.inc 76 const MCInst *MI, unsigned CPUID) {
94 const MCInst *MI, unsigned CPUID) const override {
131 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
138 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
168 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
include/llvm/ADT/ArrayRef.h 43 using iterator = const T *;
44 using const_iterator = const T *;
50 const T *Data = nullptr;
66 /*implicit*/ ArrayRef(const T &OneElt)
70 /*implicit*/ ArrayRef(const T *data, size_t length)
74 ArrayRef(const T *begin, const T *end)
74 ArrayRef(const T *begin, const T *end)
81 /*implicit*/ ArrayRef(const SmallVectorTemplateCommon<T, U> &Vec)
87 /*implicit*/ ArrayRef(const std::vector<T, A> &Vec)
92 /*implicit*/ constexpr ArrayRef(const std::array<T, N> &Arr)
97 /*implicit*/ constexpr ArrayRef(const T (&Arr)[N]) : Data(Arr), Length(N) {}
100 /*implicit*/ ArrayRef(const std::initializer_list<T> &Vec)
145 const T *data() const { return Data; }
151 const T &front() const {
157 const T &back() const {
163 template <typename Allocator> ArrayRef<T> copy(Allocator &A) {
178 ArrayRef<T> slice(size_t N, size_t M) const {
184 ArrayRef<T> slice(size_t N) const { return slice(N, size() - N); }
187 ArrayRef<T> drop_front(size_t N = 1) const {
193 ArrayRef<T> drop_back(size_t N = 1) const {
200 template <class PredicateT> ArrayRef<T> drop_while(PredicateT Pred) const {
206 template <class PredicateT> ArrayRef<T> drop_until(PredicateT Pred) const {
211 ArrayRef<T> take_front(size_t N = 1) const {
218 ArrayRef<T> take_back(size_t N = 1) const {
226 template <class PredicateT> ArrayRef<T> take_while(PredicateT Pred) const {
232 template <class PredicateT> ArrayRef<T> take_until(PredicateT Pred) const {
239 const T &operator[](size_t Index) const {
249 typename std::enable_if<std::is_same<U, T>::value, ArrayRef<T>>::type &
257 typename std::enable_if<std::is_same<U, T>::value, ArrayRef<T>>::type &
263 std::vector<T> vec() const {
270 operator std::vector<T>() const {
include/llvm/ADT/SmallVector.h 75 AlignedCharArrayUnion<T> FirstEl;
114 using value_type = T;
115 using iterator = T *;
116 using const_iterator = const T *;
121 using reference = T &;
122 using const_reference = const T &;
123 using pointer = T *;
124 using const_pointer = const T *;
179 class SmallVectorTemplateBase : public SmallVectorTemplateCommon<T> {
183 static void destroy_range(T *S, T *E) {
183 static void destroy_range(T *S, T *E) {
211 void push_back(const T &Elt) {
214 ::new ((void*) this->end()) T(Elt);
218 void push_back(T &&Elt) {
240 T *NewElts = static_cast<T*>(llvm::safe_malloc(NewCapacity*sizeof(T)));
240 T *NewElts = static_cast<T*>(llvm::safe_malloc(NewCapacity*sizeof(T)));
315 class SmallVectorImpl : public SmallVectorTemplateBase<T> {
316 using SuperClass = SmallVectorTemplateBase<T>;
357 void resize(size_type N, const T &NV) {
374 LLVM_NODISCARD T pop_back_val() {
397 void append(size_type NumInputs, const T &Elt) {
405 void append(std::initializer_list<T> IL) {
412 void assign(size_type NumElts, const T &Elt) {
429 void assign(std::initializer_list<T> IL) {
467 iterator insert(iterator I, T &&Elt) {
497 iterator insert(iterator I, const T &Elt) {
526 iterator insert(iterator I, size_type NumToInsert, const T &Elt) {
637 void insert(iterator I, std::initializer_list<T> IL) {
641 template <typename... ArgTypes> reference emplace_back(ArgTypes &&... Args) {
644 ::new ((void *)this->end()) T(std::forward<ArgTypes>(Args)...);
820 AlignedCharArrayUnion<T> InlineElts[N];
837 class SmallVector : public SmallVectorImpl<T>, SmallVectorStorage<T, N> {
837 class SmallVector : public SmallVectorImpl<T>, SmallVectorStorage<T, N> {
846 explicit SmallVector(size_t Size, const T &Value = T())
865 SmallVector(std::initializer_list<T> IL) : SmallVectorImpl<T>(N) {
884 SmallVector(SmallVectorImpl<T> &&RHS) : SmallVectorImpl<T>(N) {
include/llvm/CodeGen/AsmPrinter.h 229 void EmitToStreamer(MCStreamer &S, const MCInst &Inst);
include/llvm/CodeGen/TargetInstrInfo.h 1261 virtual void getNoop(MCInst &NopInst) const;
include/llvm/CodeGen/TargetSchedule.h 187 unsigned computeInstrLatency(const MCInst &Inst) const;
199 double computeReciprocalThroughput(const MCInst &MI) const;
include/llvm/MC/MCAsmBackend.h 131 virtual bool mayNeedRelaxation(const MCInst &Inst,
153 virtual void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
154 MCInst &Res) const = 0;
206 void handleCodePaddingInstructionBegin(const MCInst &Inst);
211 void handleCodePaddingInstructionEnd(const MCInst &Inst);
include/llvm/MC/MCCodeEmitter.h 35 virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS,
include/llvm/MC/MCCodePadder.h 75 virtual bool instructionRequiresInsertionPoint(const MCInst &Inst) {
107 void handleInstructionBegin(const MCInst &Inst);
112 void handleInstructionEnd(const MCInst &Inst);
223 virtual bool instructionRequiresPaddingFragment(const MCInst &Inst) const {
include/llvm/MC/MCDisassembler/MCDisassembler.h 78 virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
110 bool tryAddingSymbolicOperand(MCInst &Inst,
include/llvm/MC/MCDisassembler/MCExternalSymbolizer.h 47 bool tryAddingSymbolicOperand(MCInst &MI, raw_ostream &CommentStream,
include/llvm/MC/MCDisassembler/MCSymbolizer.h 67 virtual bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
include/llvm/MC/MCELFStreamer.h 83 void EmitInstToFragment(const MCInst &Inst, const MCSubtargetInfo &) override;
84 void EmitInstToData(const MCInst &Inst, const MCSubtargetInfo &) override;
include/llvm/MC/MCFragment.h 275 MCInst Inst;
278 MCRelaxableFragment(const MCInst &Inst, const MCSubtargetInfo &STI,
283 const MCInst &getInst() const { return Inst; }
284 void setInst(const MCInst &Value) { Inst = Value; }
355 MCInst Inst;
395 const MCInst &getInst() const {
407 void setInstAndInstSize(const MCInst &Inst, size_t InstSize) {
413 void setInstAndInstFragment(const MCInst &Inst,
include/llvm/MC/MCInst.h 50 const MCInst *InstVal;
105 const MCInst *getInst() const {
110 void setInst(const MCInst *Val) {
143 static MCOperand createInst(const MCInst *Val) {
218 inline raw_ostream& operator<<(raw_ostream &OS, const MCInst &MI) {
include/llvm/MC/MCInstBuilder.h 22 MCInst Inst;
55 MCInstBuilder &addInst(const MCInst *Val) {
66 operator MCInst&() {
include/llvm/MC/MCInstPrinter.h 75 virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
include/llvm/MC/MCInstrAnalysis.h 37 virtual bool isBranch(const MCInst &Inst) const {
41 virtual bool isConditionalBranch(const MCInst &Inst) const {
45 virtual bool isUnconditionalBranch(const MCInst &Inst) const {
49 virtual bool isIndirectBranch(const MCInst &Inst) const {
53 virtual bool isCall(const MCInst &Inst) const {
57 virtual bool isReturn(const MCInst &Inst) const {
61 virtual bool isTerminator(const MCInst &Inst) const {
87 const MCInst &Inst,
108 virtual bool isZeroIdiom(const MCInst &MI, APInt &Mask,
133 virtual bool isDependencyBreaking(const MCInst &MI, APInt &Mask,
144 virtual bool isOptimizableRegisterMove(const MCInst &MI,
152 evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
157 virtual Optional<uint64_t> evaluateMemoryOperandAddress(const MCInst &Inst,
include/llvm/MC/MCInstrDesc.h 198 bool (*ComplexDeprecationInfo)(MCInst &, const MCSubtargetInfo &,
215 bool getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI,
321 bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const;
621 bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
include/llvm/MC/MCObjectStreamer.h 50 virtual void EmitInstToData(const MCInst &Inst, const MCSubtargetInfo&) = 0;
54 void EmitInstructionImpl(const MCInst &Inst, const MCSubtargetInfo &STI);
118 void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override;
122 virtual void EmitInstToFragment(const MCInst &Inst, const MCSubtargetInfo &);
include/llvm/MC/MCParser/MCTargetAsmParser.h 445 checkEarlyTargetMatchPredicate(MCInst &Inst, const OperandVector &Operands) {
451 virtual unsigned checkTargetMatchPredicate(MCInst &Inst) {
include/llvm/MC/MCSchedule.h 359 const MCInst &Inst) const;
371 const MCInst &Inst) const;
include/llvm/MC/MCStreamer.h 107 const MCInst &Inst, const MCSubtargetInfo &STI);
993 virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI);
include/llvm/MC/MCSubtargetInfo.h 214 resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI,
include/llvm/MC/MCWasmStreamer.h 76 void EmitInstToFragment(const MCInst &Inst, const MCSubtargetInfo &) override;
77 void EmitInstToData(const MCInst &Inst, const MCSubtargetInfo &) override;
include/llvm/MC/MCWinCOFFStreamer.h 74 void EmitInstToData(const MCInst &Inst, const MCSubtargetInfo &STI) override;
include/llvm/MC/MCXCOFFStreamer.h 28 void EmitInstToData(const MCInst &Inst, const MCSubtargetInfo &) override;
include/llvm/MCA/CodeEmitter.h 46 ArrayRef<MCInst> Sequence;
59 const MCCodeEmitter &CE, ArrayRef<MCInst> S)
include/llvm/MCA/InstrBuilder.h 46 DenseMap<const MCInst *, std::unique_ptr<const InstrDesc>> VariantDescriptors;
51 Expected<const InstrDesc &> createInstrDescImpl(const MCInst &MCI);
52 Expected<const InstrDesc &> getOrCreateInstrDesc(const MCInst &MCI);
57 void populateWrites(InstrDesc &ID, const MCInst &MCI, unsigned SchedClassID);
58 void populateReads(InstrDesc &ID, const MCInst &MCI, unsigned SchedClassID);
59 Error verifyInstrDesc(const InstrDesc &ID, const MCInst &MCI) const;
71 Expected<std::unique_ptr<Instruction>> createInstruction(const MCInst &MCI);
include/llvm/MCA/Support.h 26 class InstructionError : public ErrorInfo<InstructionError<T>> {
30 const T &Inst;
32 InstructionError(std::string M, const T &MCI)
include/llvm/Support/AlignOf.h 30 T t;
39 template <typename T> union SizerImpl<T> { char arr[sizeof(T)]; };
50 llvm::detail::SizerImpl<T, Ts...>)];
include/llvm/Support/Error.h 330 template <typename ErrT, typename... ArgTs> Error make_error(ArgTs &&... Args) {
include/llvm/Support/PointerLikeTypeTraits.h 56 static inline void *getAsVoidPointer(T *P) { return P; }
57 static inline T *getFromVoidPointer(void *P) { return static_cast<T *>(P); }
59 enum { NumLowBitsAvailable = detail::ConstantLog2<alignof(T)>::value };
91 typedef PointerLikeTypeTraits<T *> NonConst;
93 static inline const void *getAsVoidPointer(const T *P) {
96 static inline const T *getFromVoidPointer(const void *P) {
include/llvm/Support/YAMLTraits.h 313 using Signature_enumeration = void (*)(class IO&, T&);
322 (sizeof(test<ScalarEnumerationTraits<T>>(nullptr)) == 1);
329 using Signature_bitset = void (*)(class IO&, T&);
337 static bool const value = (sizeof(test<ScalarBitSetTraits<T>>(nullptr)) == 1);
344 using Signature_input = StringRef (*)(StringRef, void*, T&);
345 using Signature_output = void (*)(const T&, void*, raw_ostream&);
357 (sizeof(test<ScalarTraits<T>>(nullptr, nullptr, nullptr)) == 1);
364 using Signature_input = StringRef (*)(StringRef, void *, T &);
365 using Signature_output = void (*)(const T &, void *, raw_ostream &);
375 (sizeof(test<BlockScalarTraits<T>>(nullptr, nullptr)) == 1);
380 using Signature_input = StringRef (*)(StringRef, StringRef, void *, T &);
381 using Signature_output = void (*)(const T &, void *, raw_ostream &,
383 using Signature_mustQuote = QuotingType (*)(const T &, StringRef);
393 (sizeof(test<TaggedScalarTraits<T>>(nullptr, nullptr, nullptr)) == 1);
412 using Signature_mapping = void (*)(class IO &, T &);
419 static bool const value = (sizeof(test<MappingTraits<T>>(nullptr)) == 1);
438 using Signature_validate = StringRef (*)(class IO &, T &);
445 static bool const value = (sizeof(test<MappingTraits<T>>(nullptr)) == 1);
452 using Signature_size = size_t (*)(class IO&, T&);
460 static bool const value = (sizeof(test<SequenceTraits<T>>(nullptr)) == 1);
467 using Signature_input = void (*)(IO &io, StringRef key, T &v);
476 (sizeof(test<CustomMappingTraits<T>>(nullptr)) == 1);
516 using Signature_size = size_t (*)(class IO &, T &);
524 static bool const value = (sizeof(test<DocumentListTraits<T>>(nullptr))==1);
528 using Signature_getKind = NodeKind (*)(const T &);
535 static bool const value = (sizeof(test<PolymorphicTraits<T>>(nullptr)) == 1);
988 typename std::enable_if<has_ScalarTraits<T>::value, void>::type
989 yamlize(IO &io, T &Val, bool, EmptyContext &Ctx) {
993 ScalarTraits<T>::output(Val, io.getContext(), Buffer);
995 io.scalarString(Str, ScalarTraits<T>::mustQuote(Str));
999 io.scalarString(Str, ScalarTraits<T>::mustQuote(Str));
1000 StringRef Result = ScalarTraits<T>::input(Str, io.getContext(), Val);
1904 : SequenceTraitsImpl<std::vector<T>, SequenceElementTraits<T>::flow> {};
include/llvm/Support/type_traits.h 91 T t;
122 static auto get(F*) -> decltype(std::declval<F &>() = std::declval<const F &>(), std::true_type{});
122 static auto get(F*) -> decltype(std::declval<F &>() = std::declval<const F &>(), std::true_type{});
122 static auto get(F*) -> decltype(std::declval<F &>() = std::declval<const F &>(), std::true_type{});
130 static auto get(F*) -> decltype(std::declval<F &>() = std::declval<F &&>(), std::true_type{});
130 static auto get(F*) -> decltype(std::declval<F &>() = std::declval<F &&>(), std::true_type{});
130 static auto get(F*) -> decltype(std::declval<F &>() = std::declval<F &&>(), std::true_type{});
145 std::is_copy_constructible<detail::trivial_helper<T>>::value;
147 !std::is_copy_constructible<T>::value;
151 std::is_move_constructible<detail::trivial_helper<T>>::value;
153 !std::is_move_constructible<T>::value;
157 is_copy_assignable<detail::trivial_helper<T>>::value;
159 !is_copy_assignable<T>::value;
163 is_move_assignable<detail::trivial_helper<T>>::value;
165 !is_move_assignable<T>::value;
169 std::is_destructible<detail::trivial_helper<T>>::value;
lib/CodeGen/AsmPrinter/AsmPrinter.cpp 230 void AsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) {
1154 MCInst Noop;
lib/CodeGen/TargetInstrInfo.cpp 464 void TargetInstrInfo::getNoop(MCInst &NopInst) const {
lib/CodeGen/TargetSchedule.cpp 266 unsigned TargetSchedModel::computeInstrLatency(const MCInst &Inst) const {
354 TargetSchedModel::computeReciprocalThroughput(const MCInst &MI) const {
lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp 249 MCInst Inst;
307 MCInst Inst;
664 bool decodeInst(StringRef Symbol, MCInst &Inst, uint64_t &Size) const {
lib/MC/MCAsmBackend.cpp 127 void MCAsmBackend::handleCodePaddingInstructionBegin(const MCInst &Inst) {
131 void MCAsmBackend::handleCodePaddingInstructionEnd(const MCInst &Inst) {
lib/MC/MCAsmStreamer.cpp 112 void AddEncodingComment(const MCInst &Inst, const MCSubtargetInfo &);
333 void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override;
1838 void MCAsmStreamer::AddEncodingComment(const MCInst &Inst,
1929 void MCAsmStreamer::EmitInstruction(const MCInst &Inst,
lib/MC/MCAssembler.cpp 918 MCInst Relaxed;
lib/MC/MCCodePadder.cpp 73 void MCCodePadder::handleInstructionBegin(const MCInst &Inst) {
117 void MCCodePadder::handleInstructionEnd(const MCInst &Inst) {
lib/MC/MCDisassembler/Disassembler.cpp 169 static int getItineraryLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
194 static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
230 static void emitLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
260 MCInst Inst;
lib/MC/MCDisassembler/MCExternalSymbolizer.cpp 34 bool MCExternalSymbolizer::tryAddingSymbolicOperand(MCInst &MI,
lib/MC/MCELFStreamer.cpp 497 void MCELFStreamer::EmitInstToFragment(const MCInst &Inst,
515 void MCELFStreamer::EmitInstToData(const MCInst &Inst,
lib/MC/MCInstrAnalysis.cpp 20 const MCInst &Inst,
26 bool MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr,
38 MCInstrAnalysis::evaluateMemoryOperandAddress(const MCInst &Inst, uint64_t Addr,
lib/MC/MCInstrDesc.cpp 21 bool MCInstrDesc::getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI,
32 bool MCInstrDesc::mayAffectControlFlow(const MCInst &MI,
53 bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
lib/MC/MCMachOStreamer.cpp 59 void EmitInstToData(const MCInst &Inst, const MCSubtargetInfo &STI) override;
455 void MCMachOStreamer::EmitInstToData(const MCInst &Inst,
lib/MC/MCObjectStreamer.cpp 316 void MCObjectStreamer::EmitInstruction(const MCInst &Inst,
323 void MCObjectStreamer::EmitInstructionImpl(const MCInst &Inst,
348 MCInst Relaxed;
360 void MCObjectStreamer::EmitInstToFragment(const MCInst &Inst,
lib/MC/MCSchedule.cpp 69 const MCInst &Inst) const {
112 const MCInst &Inst) const {
lib/MC/MCStreamer.cpp 980 raw_ostream &OS, const MCInst &Inst,
1014 void MCStreamer::EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &) {
lib/MC/MCWasmStreamer.cpp 168 void MCWasmStreamer::EmitInstToFragment(const MCInst &Inst,
173 void MCWasmStreamer::EmitInstToData(const MCInst &Inst,
lib/MC/MCWinCOFFStreamer.cpp 51 void MCWinCOFFStreamer::EmitInstToData(const MCInst &Inst,
lib/MC/MCXCOFFStreamer.cpp 70 void MCXCOFFStreamer::EmitInstToData(const MCInst &Inst,
lib/MCA/CodeEmitter.cpp 25 const MCInst &Inst = Sequence[MCID];
26 MCInst Relaxed(Sequence[MCID]);
lib/MCA/InstrBuilder.cpp 218 static Error verifyOperands(const MCInstrDesc &MCDesc, const MCInst &MCI) {
229 return make_error<InstructionError<MCInst>>(
240 return make_error<InstructionError<MCInst>>(Message, MCI);
247 void InstrBuilder::populateWrites(InstrDesc &ID, const MCInst &MCI,
417 void InstrBuilder::populateReads(InstrDesc &ID, const MCInst &MCI,
484 const MCInst &MCI) const {
505 return make_error<InstructionError<MCInst>>(Message, MCI);
509 InstrBuilder::createInstrDescImpl(const MCInst &MCI) {
529 return make_error<InstructionError<MCInst>>(
537 return make_error<InstructionError<MCInst>>(
599 InstrBuilder::getOrCreateInstrDesc(const MCInst &MCI) {
610 InstrBuilder::createInstruction(const MCInst &MCI) {
lib/Object/RecordStreamer.cpp 84 void RecordStreamer::EmitInstruction(const MCInst &Inst,
lib/Object/RecordStreamer.h 49 void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override;
lib/Target/AArch64/AArch64AsmPrinter.cpp 873 MCInst MOVI;
879 MCInst FMov;
937 MCInst MovZ;
944 MCInst MovK;
958 MCInst TmpInst;
996 MCInst TmpInst;
1005 MCInst TmpInst;
1028 MCInst Adrp;
1034 MCInst Ldr;
1042 MCInst Add;
1052 MCInst TLSDescCall;
1057 MCInst Blr;
1216 MCInst TmpInst;
lib/Target/AArch64/AArch64InstrInfo.cpp 3493 void AArch64InstrInfo::getNoop(MCInst &NopInst) const {
lib/Target/AArch64/AArch64InstrInfo.h 193 void getNoop(MCInst &NopInst) const override;
lib/Target/AArch64/AArch64MCInstLower.cpp 296 void AArch64MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
lib/Target/AArch64/AArch64MCInstLower.h 38 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp 86 static PrefixInfo CreateFromInst(const MCInst &Inst, uint64_t TSFlags) {
182 bool validateInstruction(MCInst &Inst, SMLoc &IDLoc,
1414 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1424 void addRegOperands(MCInst &Inst, unsigned N) const {
1429 void addGPR32as64Operands(MCInst &Inst, unsigned N) const {
1441 void addGPR64as32Operands(MCInst &Inst, unsigned N) const {
1454 void addFPRasZPRRegOperands(MCInst &Inst, unsigned N) const {
1468 void addVectorReg64Operands(MCInst &Inst, unsigned N) const {
1475 void addVectorReg128Operands(MCInst &Inst, unsigned N) const {
1482 void addVectorRegLoOperands(MCInst &Inst, unsigned N) const {
1494 void addVectorListOperands(MCInst &Inst, unsigned N) const {
1516 void addVectorIndexOperands(MCInst &Inst, unsigned N) const {
1522 void addExactFPImmOperands(MCInst &Inst, unsigned N) const {
1528 void addImmOperands(MCInst &Inst, unsigned N) const {
1537 void addImmWithOptionalShiftOperands(MCInst &Inst, unsigned N) const {
1552 void addImmNegWithOptionalShiftOperands(MCInst &Inst, unsigned N) const {
1561 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1566 void addAdrpLabelOperands(MCInst &Inst, unsigned N) const {
1575 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1580 void addUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1591 void addUImm6Operands(MCInst &Inst, unsigned N) const {
1598 void addImmScaledOperands(MCInst &Inst, unsigned N) const {
1605 void addLogicalImmOperands(MCInst &Inst, unsigned N) const {
1614 void addLogicalImmNotOperands(MCInst &Inst, unsigned N) const {
1622 void addSIMDImmType10Operands(MCInst &Inst, unsigned N) const {
1629 void addBranchTarget26Operands(MCInst &Inst, unsigned N) const {
1643 void addPCRelLabel19Operands(MCInst &Inst, unsigned N) const {
1657 void addBranchTarget14Operands(MCInst &Inst, unsigned N) const {
1671 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1677 void addBarrierOperands(MCInst &Inst, unsigned N) const {
1682 void addMRSSystemRegisterOperands(MCInst &Inst, unsigned N) const {
1688 void addMSRSystemRegisterOperands(MCInst &Inst, unsigned N) const {
1694 void addSystemPStateFieldWithImm0_1Operands(MCInst &Inst, unsigned N) const {
1700 void addSystemPStateFieldWithImm0_15Operands(MCInst &Inst, unsigned N) const {
1706 void addSysCROperands(MCInst &Inst, unsigned N) const {
1711 void addPrefetchOperands(MCInst &Inst, unsigned N) const {
1716 void addPSBHintOperands(MCInst &Inst, unsigned N) const {
1721 void addBTIHintOperands(MCInst &Inst, unsigned N) const {
1726 void addShifterOperands(MCInst &Inst, unsigned N) const {
1733 void addExtendOperands(MCInst &Inst, unsigned N) const {
1741 void addExtend64Operands(MCInst &Inst, unsigned N) const {
1749 void addMemExtendOperands(MCInst &Inst, unsigned N) const {
1761 void addMemExtend8Operands(MCInst &Inst, unsigned N) const {
1770 void addMOVZMovAliasOperands(MCInst &Inst, unsigned N) const {
1779 void addMOVNMovAliasOperands(MCInst &Inst, unsigned N) const {
1787 void addComplexRotationEvenOperands(MCInst &Inst, unsigned N) const {
1793 void addComplexRotationOddOperands(MCInst &Inst, unsigned N) const {
3888 bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
4777 MCInst Inst;
5307 MCInst Inst;
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp 40 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst,
43 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst,
47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
59 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
65 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst,
68 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
71 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst,
74 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
77 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
80 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
83 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
86 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
89 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
92 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
95 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
98 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
101 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
104 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
107 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
110 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
113 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
117 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
120 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
123 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
125 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
127 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
129 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
131 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
134 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
137 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
140 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
143 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
146 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
149 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
152 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
155 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
158 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
161 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
163 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
165 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
168 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
171 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
174 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
177 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
179 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
182 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
184 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
187 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
189 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
192 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
194 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
196 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
198 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
200 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
202 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
206 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
210 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
215 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
218 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
220 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
251 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
315 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
326 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
344 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
365 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
386 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
407 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
428 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
439 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
450 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
472 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
483 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
506 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
517 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
525 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
544 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
568 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
592 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
609 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
619 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
639 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo,
661 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
684 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
707 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
728 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
751 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
774 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
784 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
793 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
800 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
816 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
823 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
833 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
841 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
864 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
870 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
876 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
881 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
887 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
892 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
898 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
903 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
909 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
914 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
919 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
924 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
929 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
934 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
996 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
1029 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
1090 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
1288 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
1371 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
1505 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
1562 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
1593 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
1632 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
1650 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
1669 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
1705 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
1722 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
1752 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
1776 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst,
1790 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
1799 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
1808 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
1826 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
1841 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
1853 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
lib/Target/AArch64/Disassembler/AArch64Disassembler.h 27 getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes,
lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp 60 MCInst &MI, raw_ostream &CommentStream, int64_t Value, uint64_t Address,
lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.h 30 bool tryAddingSymbolicOperand(MCInst &MI, raw_ostream &CommentStream,
lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp 84 bool mayNeedRelaxation(const MCInst &Inst,
89 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
90 MCInst &Res) const override;
422 bool AArch64AsmBackend::mayNeedRelaxation(const MCInst &Inst,
438 void AArch64AsmBackend::relaxInstruction(const MCInst &Inst,
440 MCInst &Res) const {
lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp 105 void EmitInstruction(const MCInst &Inst,
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 59 void AArch64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
701 void AArch64AppleInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
754 bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
867 void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
882 void AArch64InstPrinter::printImm(const MCInst *MI, unsigned OpNo,
889 void AArch64InstPrinter::printImmHex(const MCInst *MI, unsigned OpNo,
896 void AArch64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
909 void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
918 void AArch64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo,
926 void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
949 void AArch64InstPrinter::printLogicalImm(const MCInst *MI, unsigned OpNum,
957 void AArch64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum,
969 void AArch64InstPrinter::printShiftedRegister(const MCInst *MI, unsigned OpNum,
976 void AArch64InstPrinter::printExtendedRegister(const MCInst *MI, unsigned OpNum,
983 void AArch64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum,
1024 void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
1033 void AArch64InstPrinter::printRegWithShiftExtend(const MCInst *MI,
1050 void AArch64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
1057 void AArch64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum,
1064 void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
1071 void AArch64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
1077 void AArch64InstPrinter::printUImm12Offset(const MCInst *MI, unsigned OpNum,
1088 void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
1103 void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
1120 void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum,
1131 void AArch64InstPrinter::printBTIHintOp(const MCInst *MI, unsigned OpNum,
1142 void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1234 void AArch64InstPrinter::printGPRSeqPairsClassOperand(const MCInst *MI,
1250 void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
1304 AArch64InstPrinter::printImplicitlyTypedVectorList(const MCInst *MI,
1312 void AArch64InstPrinter::printTypedVectorList(const MCInst *MI, unsigned OpNum,
1324 void AArch64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1330 void AArch64InstPrinter::printAlignedLabel(const MCInst *MI, unsigned OpNum,
1355 void AArch64InstPrinter::printAdrpLabel(const MCInst *MI, unsigned OpNum,
1371 void AArch64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo,
1394 void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo,
1414 void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo,
1434 void AArch64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo,
1446 void AArch64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo,
1455 void AArch64InstPrinter::printComplexRotationOp(const MCInst *MI, unsigned OpNo,
1462 void AArch64InstPrinter::printSVEPattern(const MCInst *MI, unsigned OpNum,
1473 void AArch64InstPrinter::printSVERegOp(const MCInst *MI, unsigned OpNum,
1512 void AArch64InstPrinter::printImm8OptLsl(const MCInst *MI, unsigned OpNum,
1537 void AArch64InstPrinter::printSVELogicalImm(const MCInst *MI, unsigned OpNum,
1556 void AArch64InstPrinter::printZPRasFPR(const MCInst *MI, unsigned OpNum,
1574 void AArch64InstPrinter::printExactFPImm(const MCInst *MI, unsigned OpNum,
1583 void AArch64InstPrinter::printGPR64as32(const MCInst *MI, unsigned OpNum,
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h 28 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
33 virtual void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
35 virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
37 virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
50 bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI,
53 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
55 void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
57 void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
60 void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm,
63 void printPostIncOperand(const MCInst *MI, unsigned OpNo,
68 void printVRegOperand(const MCInst *MI, unsigned OpNo,
70 void printSysCROperand(const MCInst *MI, unsigned OpNo,
72 void printAddSubImm(const MCInst *MI, unsigned OpNum,
75 void printLogicalImm(const MCInst *MI, unsigned OpNum,
77 void printShifter(const MCInst *MI, unsigned OpNum,
79 void printShiftedRegister(const MCInst *MI, unsigned OpNum,
81 void printExtendedRegister(const MCInst *MI, unsigned OpNum,
83 void printArithExtend(const MCInst *MI, unsigned OpNum,
86 void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O,
89 void printMemExtend(const MCInst *MI, unsigned OpNum,
94 void printRegWithShiftExtend(const MCInst *MI, unsigned OpNum,
96 void printCondCode(const MCInst *MI, unsigned OpNum,
98 void printInverseCondCode(const MCInst *MI, unsigned OpNum,
100 void printAlignedLabel(const MCInst *MI, unsigned OpNum,
102 void printUImm12Offset(const MCInst *MI, unsigned OpNum, unsigned Scale,
104 void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale,
108 void printUImm12Offset(const MCInst *MI, unsigned OpNum,
114 void printAMIndexedWB(const MCInst *MI, unsigned OpNum,
119 void printAMNoIndex(const MCInst *MI, unsigned OpNum,
123 void printImmScale(const MCInst *MI, unsigned OpNum,
127 void printPrefetchOp(const MCInst *MI, unsigned OpNum,
130 void printPSBHintOp(const MCInst *MI, unsigned OpNum,
133 void printBTIHintOp(const MCInst *MI, unsigned OpNum,
136 void printFPImmOperand(const MCInst *MI, unsigned OpNum,
139 void printVectorList(const MCInst *MI, unsigned OpNum,
145 void printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum,
150 void printTypedVectorList(const MCInst *MI, unsigned OpNum,
153 void printVectorIndex(const MCInst *MI, unsigned OpNum,
155 void printAdrpLabel(const MCInst *MI, unsigned OpNum,
157 void printBarrierOption(const MCInst *MI, unsigned OpNum,
159 void printMSRSystemRegister(const MCInst *MI, unsigned OpNum,
161 void printMRSSystemRegister(const MCInst *MI, unsigned OpNum,
163 void printSystemPStateField(const MCInst *MI, unsigned OpNum,
165 void printSIMDType10Operand(const MCInst *MI, unsigned OpNum,
168 void printComplexRotationOp(const MCInst *MI, unsigned OpNo,
171 void printGPRSeqPairsClassOperand(const MCInst *MI, unsigned OpNum,
175 void printImm8OptLsl(const MCInst *MI, unsigned OpNum,
178 void printSVELogicalImm(const MCInst *MI, unsigned OpNum,
180 void printSVEPattern(const MCInst *MI, unsigned OpNum,
183 void printSVERegOp(const MCInst *MI, unsigned OpNum,
185 void printGPR64as32(const MCInst *MI, unsigned OpNum,
188 void printZPRasFPR(const MCInst *MI, unsigned OpNum,
191 void printExactFPImm(const MCInst *MI, unsigned OpNum,
200 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
203 void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
205 bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
207 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp 56 uint64_t getBinaryCodeForInstr(const MCInst &MI,
62 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
70 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
76 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
82 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
88 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
94 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
101 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
107 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
113 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
119 uint32_t getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
124 uint32_t getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
130 uint32_t getMoveVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
136 uint32_t getFixedPointScaleOpValue(const MCInst &MI, unsigned OpIdx,
140 uint32_t getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx,
143 uint32_t getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx,
146 uint32_t getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx,
149 uint32_t getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx,
152 uint32_t getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx,
155 uint32_t getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx,
158 uint32_t getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx,
161 uint32_t getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx,
165 uint32_t getImm8OptLsl(const MCInst &MI, unsigned OpIdx,
168 uint32_t getSVEIncDecImm(const MCInst &MI, unsigned OpIdx,
172 unsigned fixMOVZ(const MCInst &MI, unsigned EncodedValue,
175 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
179 unsigned fixMulHigh(const MCInst &MI, unsigned EncodedValue,
183 fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue,
186 unsigned fixOneOperandFPComparison(const MCInst &MI, unsigned EncodedValue,
192 verifyInstructionPredicates(const MCInst &MI,
201 AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
212 AArch64MCCodeEmitter::getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
233 AArch64MCCodeEmitter::getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
259 AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
296 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
317 AArch64MCCodeEmitter::getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
337 AArch64MCCodeEmitter::getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
346 AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
366 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
387 AArch64MCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
415 AArch64MCCodeEmitter::getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
440 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
448 AArch64MCCodeEmitter::getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx,
457 AArch64MCCodeEmitter::getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx,
466 AArch64MCCodeEmitter::getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx,
475 AArch64MCCodeEmitter::getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx,
484 AArch64MCCodeEmitter::getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx,
493 AArch64MCCodeEmitter::getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx,
502 AArch64MCCodeEmitter::getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx,
511 AArch64MCCodeEmitter::getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx,
520 AArch64MCCodeEmitter::getImm8OptLsl(const MCInst &MI, unsigned OpIdx,
538 AArch64MCCodeEmitter::getSVEIncDecImm(const MCInst &MI, unsigned OpIdx,
550 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
560 unsigned AArch64MCCodeEmitter::fixMOVZ(const MCInst &MI, unsigned EncodedValue,
591 void AArch64MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
615 AArch64MCCodeEmitter::fixMulHigh(const MCInst &MI,
625 AArch64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI,
635 const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const {
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp 312 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
lib/Target/AMDGPU/AMDGPUMCInstLower.cpp 56 void lower(const MachineInstr *MI, MCInst &OutMI) const;
66 void lower(const MachineInstr *MI, MCInst &OutMI) const;
176 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
315 MCInst TmpInst;
375 void R600MCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
403 MCInst TmpInst;
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp 738 void addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers = true) const;
740 void addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyModifiers) const;
743 void addKImmFPOperands(MCInst &Inst, unsigned N) const;
745 void addKImmFP16Operands(MCInst &Inst, unsigned N) const {
749 void addKImmFP32Operands(MCInst &Inst, unsigned N) const {
753 void addRegOperands(MCInst &Inst, unsigned N) const;
755 void addBoolRegOperands(MCInst &Inst, unsigned N) const {
759 void addRegOrImmOperands(MCInst &Inst, unsigned N) const {
768 void addRegOrImmWithInputModsOperands(MCInst &Inst, unsigned N) const {
778 void addRegOrImmWithFPInputModsOperands(MCInst &Inst, unsigned N) const {
783 void addRegOrImmWithIntInputModsOperands(MCInst &Inst, unsigned N) const {
788 void addRegWithInputModsOperands(MCInst &Inst, unsigned N) const {
795 void addRegWithFPInputModsOperands(MCInst &Inst, unsigned N) const {
800 void addRegWithIntInputModsOperands(MCInst &Inst, unsigned N) const {
805 void addSoppBrTargetOperands(MCInst &Inst, unsigned N) const {
1087 void cvtMubufImpl(MCInst &Inst, const OperandVector &Operands,
1089 void cvtDSImpl(MCInst &Inst, const OperandVector &Operands,
1231 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
1281 void cvtDSOffset01(MCInst &Inst, const OperandVector &Operands);
1282 void cvtDS(MCInst &Inst, const OperandVector &Operands) { cvtDSImpl(Inst, Operands, false); }
1283 void cvtDSGds(MCInst &Inst, const OperandVector &Operands) { cvtDSImpl(Inst, Operands, true); }
1284 void cvtExp(MCInst &Inst, const OperandVector &Operands);
1315 bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);
1316 bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands);
1317 bool validateSOPLiteral(const MCInst &Inst) const;
1318 bool validateConstantBusLimitations(const MCInst &Inst);
1319 bool validateEarlyClobberLimitations(const MCInst &Inst);
1320 bool validateIntClampSupported(const MCInst &Inst);
1321 bool validateMIMGAtomicDMask(const MCInst &Inst);
1322 bool validateMIMGGatherDMask(const MCInst &Inst);
1323 bool validateMIMGDataSize(const MCInst &Inst);
1324 bool validateMIMGAddrSize(const MCInst &Inst);
1325 bool validateMIMGD16(const MCInst &Inst);
1326 bool validateMIMGDim(const MCInst &Inst);
1327 bool validateLdsDirect(const MCInst &Inst);
1328 bool validateOpSel(const MCInst &Inst);
1330 bool validateVOP3Literal(const MCInst &Inst) const;
1332 bool usesConstantBus(const MCInst &Inst, unsigned OpIdx);
1333 bool isInlineConstant(const MCInst &Inst, unsigned OpIdx) const;
1334 unsigned findImplicitSGPRReadInVOP(const MCInst &Inst) const;
1381 void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false, false); }
1382 void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true, false); }
1383 void cvtMubufAtomicReturn(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true, true); }
1384 void cvtMubufLds(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false, false, true); }
1385 void cvtMtbuf(MCInst &Inst, const OperandVector &Operands);
1398 void cvtVOP3(MCInst &Inst, const OperandVector &Operands,
1400 void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands);
1401 void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
1402 void cvtVOP3P(MCInst &Inst, const OperandVector &Operands);
1404 void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);
1406 void cvtMIMG(MCInst &Inst, const OperandVector &Operands,
1408 void cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands);
1417 void cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8 = false);
1418 void cvtDPP8(MCInst &Inst, const OperandVector &Operands) { cvtDPP(Inst, Operands, true); }
1423 void cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands);
1424 void cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands);
1425 void cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands);
1426 void cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands);
1427 void cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands);
1428 void cvtSDWA(MCInst &Inst, const OperandVector &Operands,
1687 void AMDGPUOperand::addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers) const {
1699 void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyModifiers) const {
1847 void AMDGPUOperand::addKImmFPOperands(MCInst &Inst, unsigned N) const {
1863 void AMDGPUOperand::addRegOperands(MCInst &Inst, unsigned N) const {
2658 unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
2717 unsigned AMDGPUAsmParser::findImplicitSGPRReadInVOP(const MCInst &Inst) const {
2740 bool AMDGPUAsmParser::isInlineConstant(const MCInst &Inst,
2797 bool AMDGPUAsmParser::usesConstantBus(const MCInst &Inst, unsigned OpIdx) {
2810 bool AMDGPUAsmParser::validateConstantBusLimitations(const MCInst &Inst) {
2889 bool AMDGPUAsmParser::validateEarlyClobberLimitations(const MCInst &Inst) {
2926 bool AMDGPUAsmParser::validateIntClampSupported(const MCInst &Inst) {
2940 bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst) {
2973 bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst) {
3013 bool AMDGPUAsmParser::validateMIMGAtomicDMask(const MCInst &Inst) {
3033 bool AMDGPUAsmParser::validateMIMGGatherDMask(const MCInst &Inst) {
3052 bool AMDGPUAsmParser::validateMIMGD16(const MCInst &Inst) {
3069 bool AMDGPUAsmParser::validateMIMGDim(const MCInst &Inst) {
3216 bool AMDGPUAsmParser::validateLdsDirect(const MCInst &Inst) {
3262 bool AMDGPUAsmParser::validateFlatOffset(const MCInst &Inst,
3302 bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst) const {
3338 bool AMDGPUAsmParser::validateOpSel(const MCInst &Inst) {
3359 bool AMDGPUAsmParser::validateVOP3Literal(const MCInst &Inst) const {
3404 bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
3488 MCInst Inst;
4640 MCInst& Inst, const OperandVector& Operands,
4728 void AMDGPUAsmParser::cvtDSOffset01(MCInst &Inst,
4752 void AMDGPUAsmParser::cvtDSImpl(MCInst &Inst, const OperandVector &Operands,
4788 void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) {
5793 void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
5866 void AMDGPUAsmParser::cvtMtbuf(MCInst &Inst, const OperandVector &Operands) {
5910 void AMDGPUAsmParser::cvtMIMG(MCInst &Inst, const OperandVector &Operands,
5957 void AMDGPUAsmParser::cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands) {
6159 void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands) {
6194 void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands)
6233 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,
6296 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {
6301 void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst,
6678 void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8) {
6810 void AMDGPUAsmParser::cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands) {
6814 void AMDGPUAsmParser::cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands) {
6818 void AMDGPUAsmParser::cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands) {
6822 void AMDGPUAsmParser::cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands) {
6826 void AMDGPUAsmParser::cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands) {
6830 void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp 72 addOperand(MCInst &Inst, const MCOperand& Opnd) {
79 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op,
90 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val,
149 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst,
157 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst,
165 static DecodeStatus decodeOperand_VS_16(MCInst &Inst,
173 static DecodeStatus decodeOperand_VS_32(MCInst &Inst,
181 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst,
189 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst,
197 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst,
205 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst,
213 static DecodeStatus decodeOperand_VGPR_32(MCInst &Inst,
242 MCInst &MI,
247 MCInst TmpInst;
258 static bool isValidDPP8(const MCInst &MI) {
268 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
432 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const {
452 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const {
473 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
1211 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst,
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h 54 DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
66 DecodeStatus tryDecodeInst(const uint8_t* Table, MCInst &MI, uint64_t Inst,
69 DecodeStatus convertSDWAInst(MCInst &MI) const;
70 DecodeStatus convertDPP8Inst(MCInst &MI) const;
71 DecodeStatus convertMIMGInst(MCInst &MI) const;
159 bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp 42 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
43 MCInst &Res) const override;
45 bool mayNeedRelaxation(const MCInst &Inst,
56 void AMDGPUAsmBackend::relaxInstruction(const MCInst &Inst,
58 MCInst &Res) const {
75 bool AMDGPUAsmBackend::mayNeedRelaxation(const MCInst &Inst,
lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp 29 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
36 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
42 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
47 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
59 void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo,
64 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
69 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
74 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
80 void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo,
87 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
92 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
97 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
102 void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
110 void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
120 void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
142 void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
151 void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo,
160 void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
166 void AMDGPUInstPrinter::printSMRDOffset20(const MCInst *MI, unsigned OpNo,
172 void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
178 void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
183 void AMDGPUInstPrinter::printDLC(const MCInst *MI, unsigned OpNo,
189 void AMDGPUInstPrinter::printGLC(const MCInst *MI, unsigned OpNo,
194 void AMDGPUInstPrinter::printSLC(const MCInst *MI, unsigned OpNo,
199 void AMDGPUInstPrinter::printSWZ(const MCInst *MI, unsigned OpNo,
203 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
208 void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo,
216 void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
228 void AMDGPUInstPrinter::printUNorm(const MCInst *MI, unsigned OpNo,
233 void AMDGPUInstPrinter::printDA(const MCInst *MI, unsigned OpNo,
238 void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo,
246 void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo,
251 void AMDGPUInstPrinter::printD16(const MCInst *MI, unsigned OpNo,
256 void AMDGPUInstPrinter::printExpCompr(const MCInst *MI, unsigned OpNo,
263 void AMDGPUInstPrinter::printExpVM(const MCInst *MI, unsigned OpNo,
270 void AMDGPUInstPrinter::printFORMAT(const MCInst *MI, unsigned OpNo,
302 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
338 void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo,
460 void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
470 void AMDGPUInstPrinter::printCBSZ(const MCInst *MI, unsigned OpNo,
480 void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo,
501 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
620 void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
655 void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
681 void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo,
695 void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
780 void AMDGPUInstPrinter::printRowMask(const MCInst *MI, unsigned OpNo,
787 void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo,
794 void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo,
803 void AMDGPUInstPrinter::printFI(const MCInst *MI, unsigned OpNo,
813 void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo,
830 void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo,
837 void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo,
844 void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo,
851 void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
867 void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo,
890 void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo,
896 void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo,
902 void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo,
908 void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo,
914 void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
953 void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
997 void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned,
1015 void AMDGPUInstPrinter::printOpSelHi(const MCInst *MI, unsigned OpNo,
1021 void AMDGPUInstPrinter::printNegLo(const MCInst *MI, unsigned OpNo,
1027 void AMDGPUInstPrinter::printNegHi(const MCInst *MI, unsigned OpNo,
1033 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
1052 void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum,
1059 void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum,
1066 void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
1089 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1097 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1109 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1117 void AMDGPUInstPrinter::printHigh(const MCInst *MI, unsigned OpNo,
1124 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
1131 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
1143 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
1206 void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
1279 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
1309 void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo,
1332 void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo,
1345 void R600InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
1352 void R600InstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
1357 void R600InstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
1381 void R600InstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
1386 void R600InstPrinter::printCT(const MCInst *MI, unsigned OpNo,
1401 void R600InstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
1413 void R600InstPrinter::printLast(const MCInst *MI, unsigned OpNo,
1418 void R600InstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
1431 void R600InstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
1436 void R600InstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
1452 void R600InstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1459 void R600InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
1494 void R600InstPrinter::printRel(const MCInst *MI, unsigned OpNo,
1499 void R600InstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
1529 void R600InstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
1534 void R600InstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
1539 void R600InstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h 26 void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
30 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
36 void printU4ImmOperand(const MCInst *MI, unsigned OpNo,
38 void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
39 void printU16ImmOperand(const MCInst *MI, unsigned OpNo,
41 void printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
42 void printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
43 void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
44 void printU32ImmOperand(const MCInst *MI, unsigned OpNo,
46 void printNamedBit(const MCInst *MI, unsigned OpNo, raw_ostream &O,
48 void printOffen(const MCInst *MI, unsigned OpNo, raw_ostream &O);
49 void printIdxen(const MCInst *MI, unsigned OpNo, raw_ostream &O);
50 void printAddr64(const MCInst *MI, unsigned OpNo, raw_ostream &O);
51 void printMBUFOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
52 void printOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
54 void printFlatOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
57 void printOffset0(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
59 void printOffset1(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
61 void printSMRDOffset8(const MCInst *MI, unsigned OpNo,
63 void printSMRDOffset20(const MCInst *MI, unsigned OpNo,
65 void printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
67 void printGDS(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
69 void printDLC(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
71 void printGLC(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
73 void printSLC(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
75 void printSWZ(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
77 void printTFE(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
79 void printDMask(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
81 void printDim(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
83 void printUNorm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
85 void printDA(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
87 void printR128A16(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
89 void printLWE(const MCInst *MI, unsigned OpNo,
91 void printD16(const MCInst *MI, unsigned OpNo,
93 void printExpCompr(const MCInst *MI, unsigned OpNo,
95 void printExpVM(const MCInst *MI, unsigned OpNo,
97 void printFORMAT(const MCInst *MI, unsigned OpNo,
101 void printVOPDst(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
103 void printVINTRPDst(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
113 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
115 void printOperandAndFPInputMods(const MCInst *MI, unsigned OpNo,
117 void printOperandAndIntInputMods(const MCInst *MI, unsigned OpNo,
119 void printDPP8(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
121 void printDPPCtrl(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
123 void printRowMask(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
125 void printBankMask(const MCInst *MI, unsigned OpNo,
127 void printBoundCtrl(const MCInst *MI, unsigned OpNo,
129 void printFI(const MCInst *MI, unsigned OpNo,
131 void printSDWASel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
132 void printSDWADstSel(const MCInst *MI, unsigned OpNo,
134 void printSDWASrc0Sel(const MCInst *MI, unsigned OpNo,
136 void printSDWASrc1Sel(const MCInst *MI, unsigned OpNo,
138 void printSDWADstUnused(const MCInst *MI, unsigned OpNo,
140 void printPackedModifier(const MCInst *MI, StringRef Name, unsigned Mod,
142 void printOpSel(const MCInst *MI, unsigned OpNo,
144 void printOpSelHi(const MCInst *MI, unsigned OpNo,
146 void printNegLo(const MCInst *MI, unsigned OpNo,
148 void printNegHi(const MCInst *MI, unsigned OpNo,
150 void printInterpSlot(const MCInst *MI, unsigned OpNo,
152 void printInterpAttr(const MCInst *MI, unsigned OpNo,
154 void printInterpAttrChan(const MCInst *MI, unsigned OpNo,
157 void printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
159 void printMemOperand(const MCInst *MI, unsigned OpNo,
161 void printBLGP(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
163 void printCBSZ(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
165 void printABID(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
172 void printExpSrcN(const MCInst *MI, unsigned OpNo,
174 void printExpSrc0(const MCInst *MI, unsigned OpNo,
176 void printExpSrc1(const MCInst *MI, unsigned OpNo,
178 void printExpSrc2(const MCInst *MI, unsigned OpNo,
180 void printExpSrc3(const MCInst *MI, unsigned OpNo,
182 void printExpTgt(const MCInst *MI, unsigned OpNo,
186 static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O,
188 static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O,
191 void printAbs(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
193 void printHigh(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
195 void printClamp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
197 void printClampSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
199 void printOModSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
201 void printLiteral(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
203 void printLast(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
205 void printNeg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
207 void printOMOD(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
209 void printRel(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
211 void printUpdateExecMask(const MCInst *MI, unsigned OpNo,
213 void printUpdatePred(const MCInst *MI, unsigned OpNo,
215 void printWrite(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
217 void printBankSwizzle(const MCInst *MI, unsigned OpNo,
219 void printRSel(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
221 void printCT(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
223 void printKCache(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
225 void printSendMsg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
227 void printSwizzle(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
229 void printWaitFlag(const MCInst *MI, unsigned OpNo,
231 void printHwreg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
233 void printEndpgm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
243 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
245 void printInstruction(const MCInst *MI, raw_ostream &O);
248 void printAbs(const MCInst *MI, unsigned OpNo, raw_ostream &O);
249 void printBankSwizzle(const MCInst *MI, unsigned OpNo, raw_ostream &O);
250 void printClamp(const MCInst *MI, unsigned OpNo, raw_ostream &O);
251 void printCT(const MCInst *MI, unsigned OpNo, raw_ostream &O);
252 void printKCache(const MCInst *MI, unsigned OpNo, raw_ostream &O);
253 void printLast(const MCInst *MI, unsigned OpNo, raw_ostream &O);
254 void printLiteral(const MCInst *MI, unsigned OpNo, raw_ostream &O);
255 void printMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
256 void printNeg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
257 void printOMOD(const MCInst *MI, unsigned OpNo, raw_ostream &O);
258 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
259 void printRel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
260 void printRSel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
261 void printUpdateExecMask(const MCInst *MI, unsigned OpNo, raw_ostream &O);
262 void printUpdatePred(const MCInst *MI, unsigned OpNo, raw_ostream &O);
263 void printWrite(const MCInst *MI, unsigned OpNo, raw_ostream &O);
lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.h 38 uint64_t getBinaryCodeForInstr(const MCInst &MI,
42 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
48 virtual unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
54 virtual unsigned getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
60 virtual unsigned getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo,
66 virtual unsigned getAVOperandEncoding(const MCInst &MI, unsigned OpNo,
75 verifyInstructionPredicates(const MCInst &MI,
lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp 115 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp 48 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
53 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
64 uint64_t getBinaryCodeForInstr(const MCInst &MI,
69 verifyInstructionPredicates(const MCInst &MI,
99 void R600MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
171 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp 59 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
64 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
70 unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
74 unsigned getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
78 unsigned getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo,
82 unsigned getAVOperandEncoding(const MCInst &MI, unsigned OpNo,
279 void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
347 unsigned SIMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
363 SIMCCodeEmitter::getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
393 SIMCCodeEmitter::getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo,
412 SIMCCodeEmitter::getAVOperandEncoding(const MCInst &MI, unsigned OpNo,
451 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
lib/Target/ARC/ARCAsmPrinter.cpp 59 MCInst TmpInst;
lib/Target/ARC/ARCMCInstLower.cpp 104 void ARCMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
lib/Target/ARC/ARCMCInstLower.h 33 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
lib/Target/ARC/Disassembler/ARCDisassembler.cpp 43 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
87 static DecodeStatus DecodeSignedOperand(MCInst &Inst, unsigned InsnS,
92 static DecodeStatus DecodeFromCyclicRange(MCInst &Inst, unsigned InsnS,
97 static DecodeStatus DecodeBranchTargetS(MCInst &Inst, unsigned InsnS,
100 static DecodeStatus DecodeMEMrs9(MCInst &, unsigned, uint64_t, const void *);
102 static DecodeStatus DecodeLdLImmInstruction(MCInst &, uint64_t, uint64_t,
105 static DecodeStatus DecodeStLImmInstruction(MCInst &, uint64_t, uint64_t,
108 static DecodeStatus DecodeLdRLImmInstruction(MCInst &, uint64_t, uint64_t,
111 static DecodeStatus DecodeMoveHRegInstruction(MCInst &Inst, uint64_t, uint64_t,
121 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
134 static DecodeStatus DecodeGBR32ShortRegister(MCInst &Inst, unsigned RegNo,
159 static DecodeStatus DecodeMEMrs9(MCInst &Inst, unsigned Insn, uint64_t Address,
169 static bool DecodeSymbolicOperand(MCInst &Inst, uint64_t Address,
179 static void DecodeSymbolicOperandOff(MCInst &Inst, uint64_t Address,
188 static DecodeStatus DecodeBranchTargetS(MCInst &Inst, unsigned InsnS,
197 static DecodeStatus DecodeSignedOperand(MCInst &Inst, unsigned InsnS,
208 static DecodeStatus DecodeFromCyclicRange(MCInst &Inst, unsigned InsnS,
219 static DecodeStatus DecodeStLImmInstruction(MCInst &Inst, uint64_t Insn,
236 static DecodeStatus DecodeLdLImmInstruction(MCInst &Inst, uint64_t Insn,
254 static DecodeStatus DecodeLdRLImmInstruction(MCInst &Inst, uint64_t Insn,
271 static DecodeStatus DecodeMoveHRegInstruction(MCInst &Inst, uint64_t Insn,
297 DecodeStatus ARCDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
lib/Target/ARC/MCTargetDesc/ARCInstPrinter.cpp 100 void ARCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
139 void ARCInstPrinter::printOperand(const MCInst *MI, unsigned OpNum,
156 void ARCInstPrinter::printMemOperandRI(const MCInst *MI, unsigned OpNum,
166 void ARCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
174 void ARCInstPrinter::printBRCCPredicateOperand(const MCInst *MI, unsigned OpNum,
lib/Target/ARC/MCTargetDesc/ARCInstPrinter.h 29 void printInstruction(const MCInst *MI, raw_ostream &O);
33 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
37 void printMemOperandRI(const MCInst *MI, unsigned OpNum, raw_ostream &O);
38 void printOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
39 void printPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
40 void printBRCCPredicateOperand(const MCInst *MI, unsigned OpNum,
lib/Target/ARM/ARM.h 58 void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
lib/Target/ARM/ARMAsmPrinter.cpp 1394 MCInst TmpInst;
1425 MCInst TmpInst;
1750 MCInst TmpInst;
1767 MCInst TmpInst;
1780 MCInst TmpInst;
2134 MCInst TmpInst;
lib/Target/ARM/ARMFeatures.h 24 inline bool isV8EligibleForIT(const InstrType *Instr) {
lib/Target/ARM/ARMInstrInfo.cpp 35 void ARMInstrInfo::getNoop(MCInst &NopInst) const {
lib/Target/ARM/ARMInstrInfo.h 28 void getNoop(MCInst &NopInst) const override;
lib/Target/ARM/ARMMCInstLower.cpp 123 void llvm::LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
210 MCInst Noop;
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 235 SmallVector<MCInst, 4> PendingConditionalInsts;
244 MCInst ITInst;
252 for (const MCInst &Inst : PendingConditionalInsts) {
389 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
391 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
579 void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
580 void cvtThumbBranches(MCInst &Inst, const OperandVector &);
581 void cvtMVEVMOVQtoDReg(MCInst &Inst, const OperandVector &);
583 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
584 bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
588 bool isITBlockTerminator(MCInst &Inst) const;
590 bool validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands,
637 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
643 unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst,
2322 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
2332 void addARMBranchTargetOperands(MCInst &Inst, unsigned N) const {
2337 void addThumbBranchTargetOperands(MCInst &Inst, unsigned N) const {
2342 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
2349 void addVPTPredNOperands(MCInst &Inst, unsigned N) const {
2356 void addVPTPredROperands(MCInst &Inst, unsigned N) const {
2373 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
2378 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
2383 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
2388 void addITMaskOperands(MCInst &Inst, unsigned N) const {
2393 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
2398 void addITCondCodeInvOperands(MCInst &Inst, unsigned N) const {
2403 void addCCOutOperands(MCInst &Inst, unsigned N) const {
2408 void addRegOperands(MCInst &Inst, unsigned N) const {
2413 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
2423 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
2434 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
2440 void addRegListOperands(MCInst &Inst, unsigned N) const {
2448 void addRegListWithAPSROperands(MCInst &Inst, unsigned N) const {
2456 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
2460 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
2464 void addFPSRegListWithVPROperands(MCInst &Inst, unsigned N) const {
2468 void addFPDRegListWithVPROperands(MCInst &Inst, unsigned N) const {
2472 void addRotImmOperands(MCInst &Inst, unsigned N) const {
2478 void addModImmOperands(MCInst &Inst, unsigned N) const {
2488 void addModImmNotOperands(MCInst &Inst, unsigned N) const {
2495 void addModImmNegOperands(MCInst &Inst, unsigned N) const {
2502 void addThumbModImmNeg8_255Operands(MCInst &Inst, unsigned N) const {
2509 void addThumbModImmNeg1_7Operands(MCInst &Inst, unsigned N) const {
2516 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
2527 void addImmOperands(MCInst &Inst, unsigned N) const {
2532 void addFBits16Operands(MCInst &Inst, unsigned N) const {
2538 void addFBits32Operands(MCInst &Inst, unsigned N) const {
2544 void addFPImmOperands(MCInst &Inst, unsigned N) const {
2551 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
2559 void addImm7s4Operands(MCInst &Inst, unsigned N) const {
2567 void addImm7Shift0Operands(MCInst &Inst, unsigned N) const {
2573 void addImm7Shift1Operands(MCInst &Inst, unsigned N) const {
2579 void addImm7Shift2Operands(MCInst &Inst, unsigned N) const {
2585 void addImm7Operands(MCInst &Inst, unsigned N) const {
2591 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
2599 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
2607 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
2615 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
2623 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
2631 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
2640 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
2649 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
2657 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
2665 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
2673 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
2682 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
2700 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
2705 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2710 void addTraceSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2715 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
2720 void addMemNoOffsetT2Operands(MCInst &Inst, unsigned N) const {
2725 void addMemNoOffsetT2NoSpOperands(MCInst &Inst, unsigned N) const {
2730 void addMemNoOffsetTOperands(MCInst &Inst, unsigned N) const {
2735 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
2741 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2757 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2763 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2767 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2771 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2775 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2779 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2783 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2787 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2791 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2795 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2799 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2803 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2807 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2827 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2841 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2870 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2892 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2914 void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const {
2936 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2952 void addMemImm7s4OffsetOperands(MCInst &Inst, unsigned N) const {
2968 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2976 void addMemImmOffsetOperands(MCInst &Inst, unsigned N) const {
2983 void addMemRegRQOffsetOperands(MCInst &Inst, unsigned N) const {
2989 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
3004 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
3019 void addConstPoolAsmImmOperands(MCInst &Inst, unsigned N) const {
3027 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
3033 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
3039 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
3049 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
3056 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
3062 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
3069 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
3076 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
3083 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
3090 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
3101 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
3113 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
3119 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
3130 void addPowerTwoOperands(MCInst &Inst, unsigned N) const {
3136 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
3141 void addBankedRegOperands(MCInst &Inst, unsigned N) const {
3146 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
3151 void addVecListOperands(MCInst &Inst, unsigned N) const {
3156 void addMVEVecListOperands(MCInst &Inst, unsigned N) const {
3187 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
3193 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
3198 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
3203 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
3208 void addVectorIndex64Operands(MCInst &Inst, unsigned N) const {
3213 void addMVEVectorIndexOperands(MCInst &Inst, unsigned N) const {
3218 void addMVEPairVectorIndexOperands(MCInst &Inst, unsigned N) const {
3223 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
3231 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
3240 void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
3249 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
3258 void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
3267 void addNEONi8ReplicateOperands(MCInst &Inst, bool Inv) const {
3282 void addNEONinvi8ReplicateOperands(MCInst &Inst, unsigned N) const {
3297 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
3305 void addNEONvmovi8ReplicateOperands(MCInst &Inst, unsigned N) const {
3310 void addNEONvmovi16ReplicateOperands(MCInst &Inst, unsigned N) const {
3326 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
3334 void addNEONvmovi32ReplicateOperands(MCInst &Inst, unsigned N) const {
3348 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
3360 void addComplexRotationEvenOperands(MCInst &Inst, unsigned N) const {
3366 void addComplexRotationOddOperands(MCInst &Inst, unsigned N) const {
3372 void addMveSaturateOperands(MCInst &Inst, unsigned N) const {
5551 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
5567 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
5626 MCInst &Inst, const OperandVector &Operands) {
7150 static bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo,
7167 static bool listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) {
7178 static bool instIsBreakpoint(const MCInst &Inst) {
7185 bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst,
7204 bool ARMAsmParser::validatetSTMRegList(const MCInst &Inst,
7225 bool ARMAsmParser::validateLDRDSTRD(MCInst &Inst,
7296 bool ARMAsmParser::validateInstruction(MCInst &Inst,
8189 bool ARMAsmParser::processInstruction(MCInst &Inst,
8234 MCInst TmpInst;
8254 MCInst TmpInst;
8272 MCInst TmpInst;
8290 MCInst TmpInst;
8349 MCInst TmpInst;
8433 MCInst TmpInst;
8455 MCInst TmpInst;
8479 MCInst TmpInst;
8505 MCInst TmpInst;
8531 MCInst TmpInst;
8553 MCInst TmpInst;
8577 MCInst TmpInst;
8603 MCInst TmpInst;
8629 MCInst TmpInst;
8649 MCInst TmpInst;
8671 MCInst TmpInst;
8695 MCInst TmpInst;
8720 MCInst TmpInst;
8743 MCInst TmpInst;
8770 MCInst TmpInst;
8801 MCInst TmpInst;
8834 MCInst TmpInst;
8857 MCInst TmpInst;
8884 MCInst TmpInst;
8915 MCInst TmpInst;
8948 MCInst TmpInst;
8969 MCInst TmpInst;
8994 MCInst TmpInst;
9023 MCInst TmpInst;
9058 MCInst TmpInst;
9080 MCInst TmpInst;
9104 MCInst TmpInst;
9129 MCInst TmpInst;
9151 MCInst TmpInst;
9175 MCInst TmpInst;
9200 MCInst TmpInst;
9224 MCInst TmpInst;
9250 MCInst TmpInst;
9277 MCInst TmpInst;
9301 MCInst TmpInst;
9327 MCInst TmpInst;
9354 MCInst TmpInst;
9376 MCInst TmpInst;
9400 MCInst TmpInst;
9425 MCInst TmpInst;
9449 MCInst TmpInst;
9475 MCInst TmpInst;
9511 MCInst TmpInst;
9538 MCInst TmpInst;
9573 MCInst TmpInst;
9630 MCInst TmpInst;
9661 MCInst TmpInst;
9675 MCInst TmpInst;
9691 MCInst TmpInst;
9707 MCInst TmpInst;
9723 MCInst TmpInst;
9741 MCInst TmpInst;
9803 MCInst TmpInst;
9832 MCInst TmpInst;
9952 MCInst TmpInst;
9973 MCInst TmpInst;
10003 MCInst TmpInst;
10021 MCInst TmpInst;
10055 MCInst TmpInst;
10099 MCInst TmpInst;
10133 MCInst TmpInst;
10183 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
10295 template <> inline bool IsCPSRDead<MCInst>(const MCInst *Instr) {
10295 template <> inline bool IsCPSRDead<MCInst>(const MCInst *Instr) {
10303 bool ARMAsmParser::isITBlockTerminator(MCInst &Inst) const {
10320 unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst,
10413 MCInst Inst;
lib/Target/ARM/Disassembler/ARMDisassembler.cpp 138 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
144 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size,
149 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size,
157 DecodeStatus AddThumbPredicate(MCInst&) const;
158 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const;
180 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
182 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
184 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
186 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
188 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
191 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
194 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst,
198 MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder);
199 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
201 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
203 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
205 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
207 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
209 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
211 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
213 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
215 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
217 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
221 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
223 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
225 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
227 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
229 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
231 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
235 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
237 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
239 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
241 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
243 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
246 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
248 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
250 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
254 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
256 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
258 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
260 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
263 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
267 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
269 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
271 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
273 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
275 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
277 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
279 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
281 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
283 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
285 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
287 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
289 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
291 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
293 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
295 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
297 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
299 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
301 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
303 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
305 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
307 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
309 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
311 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
313 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
315 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
317 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst,unsigned Val,
319 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val,
321 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
323 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
325 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
327 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
329 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
331 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
333 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
335 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
337 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
340 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
342 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
344 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
346 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
348 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
350 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
352 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
354 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
356 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
358 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
360 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
362 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
364 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
366 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
368 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
370 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
372 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
374 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
376 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
378 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
380 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
382 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
384 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
386 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
388 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
390 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn,
392 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
397 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
399 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
401 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
403 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
405 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
407 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
409 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
411 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
413 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
415 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
417 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
419 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
421 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
423 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
425 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
427 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val,
429 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
431 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
434 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
436 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
439 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val,
441 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
444 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
447 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
449 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
451 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
453 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
455 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
457 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
459 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
461 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
463 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
465 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
467 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
469 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
471 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
473 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
475 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
477 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
479 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
481 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
484 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
486 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
488 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
492 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val,
494 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val,
497 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
500 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
502 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
505 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
507 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
509 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val,
511 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val,
514 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val,
517 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val,
520 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst,
525 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn,
529 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
532 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
535 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
538 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
542 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val,
546 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val,
549 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
552 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
555 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
557 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val,
560 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn,
562 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn,
564 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn,
566 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn,
578 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
610 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
619 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size,
703 MCInst &MI, const void *Decoder) {
729 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
732 MCInst::iterator I = MI.begin();
760 ARMDisassembler::AddThumbPredicate(MCInst &MI) const {
827 MCInst::iterator CCI = MI.begin();
843 MCInst::iterator VCCI = MI.begin();
876 DecodeStatus &S, MCInst &MI) const {
889 MCInst::iterator I = MI.begin();
906 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size,
1127 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1137 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1152 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
1165 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
1180 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo,
1198 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo,
1207 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1219 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
1234 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1264 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1289 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
1299 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
1315 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1330 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1337 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1345 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1359 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1379 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1400 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1412 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1429 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1438 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1475 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1510 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1557 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1581 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1606 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1633 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1812 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1917 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1961 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
2152 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
2181 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
2204 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
2296 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
2318 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
2365 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
2407 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2431 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2458 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2486 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
2507 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
2535 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2555 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2575 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
2595 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2601 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2628 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2653 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2670 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2946 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2959 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2974 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2987 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2997 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
3267 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
3314 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
3362 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
3397 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
3450 DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn,
3496 DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn,
3524 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
3549 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3568 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3574 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3580 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3586 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3592 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3628 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3652 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3660 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3668 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3676 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3691 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3705 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3715 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3723 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3752 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3835 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3919 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3999 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
4038 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
4091 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
4105 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
4120 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
4135 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
4151 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
4166 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
4179 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val,
4193 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
4240 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
4257 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
4275 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
4336 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
4362 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
4373 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
4398 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
4409 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
4422 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
4437 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
4459 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
4483 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
4499 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
4515 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
4557 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
4589 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
4597 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
4621 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
4630 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
4639 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
4721 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4736 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4757 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4783 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4808 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4835 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4860 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4885 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4952 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
5017 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
5084 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
5147 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
5217 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
5280 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
5361 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
5433 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
5459 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
5485 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
5515 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
5552 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
5586 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
5601 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
5612 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
5639 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
5698 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
5757 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
5790 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
5817 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
5862 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
5914 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val,
5933 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val,
5945 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
5954 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
6016 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
6029 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
6039 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
6049 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
6075 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
6091 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
6107 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
6118 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
6149 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo,
6161 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst,
6169 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst,
6192 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst,
6200 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val,
6231 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val,
6274 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val,
6318 MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder,
6337 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
6346 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
6355 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
6364 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
6377 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val,
6387 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val,
6397 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
6420 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
6446 MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) {
6524 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address,
6544 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
6581 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
6591 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address,
lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp 220 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst,
319 void ARMAsmBackend::relaxInstruction(const MCInst &Inst,
321 MCInst &Res) const {
lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h 59 bool mayNeedRelaxation(const MCInst &Inst,
69 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
70 MCInst &Res) const override;
lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp 487 void EmitInstruction(const MCInst &Inst,
lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp 91 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
265 MCInst NewMI;
310 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
350 void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
380 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
400 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
417 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
446 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
458 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
470 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
489 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
515 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
544 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
559 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
578 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum,
587 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
597 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum,
607 void ARMInstPrinter::printMveAddrModeRQOperand(const MCInst *MI, unsigned OpNum,
624 void ARMInstPrinter::printMveAddrModeQOperand(const MCInst *MI, unsigned OpNum,
640 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
649 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
673 void ARMInstPrinter::printAddrMode5FP16Operand(const MCInst *MI, unsigned OpNum,
700 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
714 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
723 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
736 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
749 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
756 void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
763 void ARMInstPrinter::printTraceSyncBOption(const MCInst *MI, unsigned OpNum,
770 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
784 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
794 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
805 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
825 void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
834 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
844 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
850 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
862 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
944 void ARMInstPrinter::printBankedRegOperand(const MCInst *MI, unsigned OpNum,
958 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
970 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
978 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
986 void ARMInstPrinter::printMandatoryInvertedPredicateOperand(const MCInst *MI,
994 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
1004 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
1010 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
1016 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
1022 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
1028 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
1034 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
1056 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
1063 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
1071 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
1086 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
1106 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
1128 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
1135 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
1142 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
1149 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
1159 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1175 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
1203 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
1227 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
1259 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1274 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1289 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1306 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
1329 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1337 void ARMInstPrinter::printVMOVModImmOperand(const MCInst *MI, unsigned OpNum,
1348 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
1355 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1365 void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum,
1406 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1412 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1418 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1424 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1432 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1445 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
1458 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1473 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1490 void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1499 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1513 void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
1529 void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
1548 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1561 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1576 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1592 void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1608 void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI, unsigned OpNum,
1626 void ARMInstPrinter::printMVEVectorList(const MCInst *MI, unsigned OpNum,
1640 void ARMInstPrinter::printComplexRotationOp(const MCInst *MI, unsigned OpNo,
1647 void ARMInstPrinter::printVPTPredicateOperand(const MCInst *MI, unsigned OpNum,
1655 void ARMInstPrinter::printVPTMask(const MCInst *MI, unsigned OpNum,
1671 void ARMInstPrinter::printExpandedImmOperand(const MCInst *MI, unsigned OpNum,
1680 void ARMInstPrinter::printMveSaturateOp(const MCInst *MI, unsigned OpNum,
lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h 28 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
33 void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
35 virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
37 virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
44 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
47 void printSORegRegOperand(const MCInst *MI, unsigned OpNum,
49 void printSORegImmOperand(const MCInst *MI, unsigned OpNum,
52 void printAddrModeTBB(const MCInst *MI, unsigned OpNum,
54 void printAddrModeTBH(const MCInst *MI, unsigned OpNum,
56 void printAddrMode2Operand(const MCInst *MI, unsigned OpNum,
58 void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum,
60 void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum,
62 void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum,
65 void printAddrMode3Operand(const MCInst *MI, unsigned OpNum,
67 void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum,
69 void printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, raw_ostream &O,
71 void printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum,
73 void printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
75 void printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum,
78 void printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
81 void printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
84 void printAddrMode5FP16Operand(const MCInst *MI, unsigned OpNum,
86 void printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
88 void printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
90 void printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum,
93 void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum,
96 void printMemBOption(const MCInst *MI, unsigned OpNum,
98 void printInstSyncBOption(const MCInst *MI, unsigned OpNum,
100 void printTraceSyncBOption(const MCInst *MI, unsigned OpNum,
102 void printShiftImmOperand(const MCInst *MI, unsigned OpNum,
104 void printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
106 void printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
110 void printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
112 void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
114 void printThumbSRImm(const MCInst *MI, unsigned OpNum,
116 void printThumbITMask(const MCInst *MI, unsigned OpNum,
118 void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum,
120 void printThumbAddrModeImm5SOperand(const MCInst *MI, unsigned OpNum,
123 void printThumbAddrModeImm5S1Operand(const MCInst *MI, unsigned OpNum,
126 void printThumbAddrModeImm5S2Operand(const MCInst *MI, unsigned OpNum,
129 void printThumbAddrModeImm5S4Operand(const MCInst *MI, unsigned OpNum,
132 void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum,
135 void printT2SOOperand(const MCInst *MI, unsigned OpNum,
138 void printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
141 void printT2AddrModeImm8Operand(const MCInst *MI, unsigned OpNum,
144 void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum,
146 void printT2AddrModeImm0_1020s4Operand(const MCInst *MI, unsigned OpNum,
149 void printT2AddrModeImm8OffsetOperand(const MCInst *MI, unsigned OpNum,
152 void printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, unsigned OpNum,
155 void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum,
158 void printSetendOperand(const MCInst *MI, unsigned OpNum,
160 void printCPSIMod(const MCInst *MI, unsigned OpNum,
162 void printCPSIFlag(const MCInst *MI, unsigned OpNum,
164 void printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
166 void printBankedRegOperand(const MCInst *MI, unsigned OpNum,
168 void printPredicateOperand(const MCInst *MI, unsigned OpNum,
170 void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum,
173 void printMandatoryRestrictedPredicateOperand(const MCInst *MI,
177 void printMandatoryInvertedPredicateOperand(const MCInst *MI, unsigned OpNum,
180 void printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
182 void printRegisterList(const MCInst *MI, unsigned OpNum,
184 void printNoHashImmediate(const MCInst *MI, unsigned OpNum,
186 void printPImmediate(const MCInst *MI, unsigned OpNum,
188 void printCImmediate(const MCInst *MI, unsigned OpNum,
190 void printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
192 void printFPImmOperand(const MCInst *MI, unsigned OpNum,
194 void printVMOVModImmOperand(const MCInst *MI, unsigned OpNum,
196 void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
198 void printRotImmOperand(const MCInst *MI, unsigned OpNum,
200 void printModImmOperand(const MCInst *MI, unsigned OpNum,
202 void printGPRPairOperand(const MCInst *MI, unsigned OpNum,
205 void printPCLabel(const MCInst *MI, unsigned OpNum,
207 void printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
209 void printFBits16(const MCInst *MI, unsigned OpNum,
211 void printFBits32(const MCInst *MI, unsigned OpNum,
213 void printVectorIndex(const MCInst *MI, unsigned OpNum,
215 void printVectorListOne(const MCInst *MI, unsigned OpNum,
217 void printVectorListTwo(const MCInst *MI, unsigned OpNum,
219 void printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
221 void printVectorListThree(const MCInst *MI, unsigned OpNum,
223 void printVectorListFour(const MCInst *MI, unsigned OpNum,
225 void printVectorListOneAllLanes(const MCInst *MI, unsigned OpNum,
227 void printVectorListTwoAllLanes(const MCInst *MI, unsigned OpNum,
229 void printVectorListThreeAllLanes(const MCInst *MI, unsigned OpNum,
231 void printVectorListFourAllLanes(const MCInst *MI, unsigned OpNum,
233 void printVectorListTwoSpacedAllLanes(const MCInst *MI, unsigned OpNum,
236 void printVectorListThreeSpacedAllLanes(const MCInst *MI, unsigned OpNum,
239 void printVectorListFourSpacedAllLanes(const MCInst *MI, unsigned OpNum,
242 void printVectorListThreeSpaced(const MCInst *MI, unsigned OpNum,
244 void printVectorListFourSpaced(const MCInst *MI, unsigned OpNum,
247 void printMVEVectorList(const MCInst *MI, unsigned OpNum,
250 void printComplexRotationOp(const MCInst *MI, unsigned OpNum,
253 void printVPTPredicateOperand(const MCInst *MI, unsigned OpNum,
256 void printVPTMask(const MCInst *MI, unsigned OpNum,
259 void printMveAddrModeRQOperand(const MCInst *MI, unsigned OpNum,
261 void printMveAddrModeQOperand(const MCInst *MI, unsigned OpNum,
263 void printExpandedImmOperand(const MCInst *MI, unsigned OpNum,
265 void printMveSaturateOp(const MCInst *MI, unsigned OpNum,
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp 80 uint64_t getBinaryCodeForInstr(const MCInst &MI,
86 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
93 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
97 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
104 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
110 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
115 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
120 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
125 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
131 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
137 uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
143 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
146 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
149 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
155 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
158 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
161 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
165 uint32_t getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
171 uint32_t getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
177 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
182 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
188 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
194 uint32_t getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
200 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
207 uint32_t getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
213 uint32_t getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
220 uint32_t getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
226 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
231 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
260 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
265 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
270 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
275 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
281 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
286 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
291 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
296 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
301 uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
306 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
314 unsigned getModImmOpValue(const MCInst &MI, unsigned Op,
333 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
352 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
356 unsigned getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
359 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
364 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
367 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
370 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
374 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
380 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
384 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
387 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
390 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
393 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
396 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
400 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
403 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
406 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
409 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
413 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
417 unsigned getExpandedImmOpValue(const MCInst &MI, unsigned Op,
425 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
428 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
431 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
434 unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
438 unsigned VFPThumb2PostEncoder(const MCInst &MI,
442 uint32_t getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
458 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
463 uint32_t getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
467 uint32_t getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
471 uint32_t getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
474 uint32_t getRestrictedCondCodeOpValue(const MCInst &MI, unsigned OpIdx,
478 uint32_t getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
488 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
508 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
522 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
535 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
548 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue,
560 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
597 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
626 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
664 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
677 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
689 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
701 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
713 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
723 static bool HasConditionalBranch(const MCInst &MI) {
742 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
756 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
772 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
787 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
800 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
829 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
870 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
890 getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
917 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
930 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
946 ARMMCCodeEmitter::getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
980 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
1031 getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
1062 getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
1082 getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
1113 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
1154 ARMMCCodeEmitter::getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
1181 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
1194 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
1250 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
1284 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1307 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1319 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1339 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1376 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1392 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1407 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1418 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1458 getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
1497 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1545 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1592 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1612 getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
1637 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1654 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1697 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1711 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1758 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1782 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1809 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1830 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1839 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1846 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1853 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1860 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1867 encodeInstruction(const MCInst &MI, raw_ostream &OS,
1895 ARMMCCodeEmitter::getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
1905 ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
1927 uint32_t ARMMCCodeEmitter::getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
1959 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
1987 getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
1997 getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp 37 static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
69 static bool getITDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
81 static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
98 static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
251 bool isUnconditionalBranch(const MCInst &Inst) const override {
258 bool isConditionalBranch(const MCInst &Inst) const override {
265 bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
281 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
lib/Target/ARM/Thumb1InstrInfo.cpp 26 void Thumb1InstrInfo::getNoop(MCInst &NopInst) const {
lib/Target/ARM/Thumb1InstrInfo.h 28 void getNoop(MCInst &NopInst) const override;
lib/Target/ARM/Thumb2InstrInfo.cpp 45 void Thumb2InstrInfo::getNoop(MCInst &NopInst) const {
lib/Target/ARM/Thumb2InstrInfo.h 29 void getNoop(MCInst &NopInst) const override;
lib/Target/AVR/AVRAsmPrinter.cpp 174 MCInst I;
lib/Target/AVR/AVRMCInstLower.cpp 62 void AVRMCInstLower::lowerInstruction(const MachineInstr &MI, MCInst &OutMI) const {
lib/Target/AVR/AVRMCInstLower.h 31 void lowerInstruction(const MachineInstr &MI, MCInst &OutMI) const;
lib/Target/AVR/AsmParser/AVRAsmParser.cpp 81 bool emit(MCInst &Instruction, SMLoc const &Loc, MCStreamer &Out) const;
129 void addRegOperands(MCInst &Inst, unsigned N) const {
136 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
146 void addImmOperands(MCInst &Inst, unsigned N) const {
155 void addMemriOperands(MCInst &Inst, unsigned N) const {
163 void addImmCom8Operands(MCInst &Inst, unsigned N) const {
308 bool AVRAsmParser::emit(MCInst &Inst, SMLoc const &Loc, MCStreamer &Out) const {
319 MCInst Inst;
lib/Target/AVR/Disassembler/AVRDisassembler.cpp 41 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
61 static DecodeStatus DecodeGPR8RegisterClass(MCInst &Inst, unsigned RegNo,
66 static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst, unsigned RegNo,
71 static DecodeStatus DecodePTRREGSRegisterClass(MCInst &Inst, unsigned RegNo,
114 DecodeStatus AVRDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
154 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h 53 bool mayNeedRelaxation(const MCInst &Inst,
65 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
66 MCInst &Res) const override {}
lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp 35 void AVRInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
100 void AVRInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
125 void AVRInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
145 void AVRInstPrinter::printMemri(const MCInst *MI, unsigned OpNo,
lib/Target/AVR/MCTargetDesc/AVRInstPrinter.h 32 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
39 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
40 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
41 void printMemri(const MCInst *MI, unsigned OpNo, raw_ostream &O);
44 void printInstruction(const MCInst *MI, raw_ostream &O);
45 bool printAliasInstr(const MCInst *MI, raw_ostream &O);
46 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp 67 AVRMCCodeEmitter::loadStorePostEncoder(const MCInst &MI, unsigned EncodedValue,
92 AVRMCCodeEmitter::encodeRelCondBrTarget(const MCInst &MI, unsigned OpNo,
112 unsigned AVRMCCodeEmitter::encodeLDSTPtrReg(const MCInst &MI, unsigned OpNo,
133 unsigned AVRMCCodeEmitter::encodeMemri(const MCInst &MI, unsigned OpNo,
169 unsigned AVRMCCodeEmitter::encodeComplement(const MCInst &MI, unsigned OpNo,
180 unsigned AVRMCCodeEmitter::encodeImm(const MCInst &MI, unsigned OpNo,
204 unsigned AVRMCCodeEmitter::encodeCallTarget(const MCInst &MI, unsigned OpNo,
249 unsigned AVRMCCodeEmitter::getMachineOpValue(const MCInst &MI,
282 void AVRMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h 46 unsigned loadStorePostEncoder(const MCInst &MI, unsigned EncodedValue,
51 unsigned encodeRelCondBrTarget(const MCInst &MI, unsigned OpNo,
56 unsigned encodeLDSTPtrReg(const MCInst &MI, unsigned OpNo,
61 unsigned encodeMemri(const MCInst &MI, unsigned OpNo,
66 unsigned encodeComplement(const MCInst &MI, unsigned OpNo,
73 unsigned encodeImm(const MCInst &MI, unsigned OpNo,
78 unsigned encodeCallTarget(const MCInst &MI, unsigned OpNo,
83 uint64_t getBinaryCodeForInstr(const MCInst &MI,
94 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
101 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
lib/Target/BPF/AsmParser/BPFAsmParser.cpp 176 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
186 void addRegOperands(MCInst &Inst, unsigned N) const {
191 void addImmOperands(MCInst &Inst, unsigned N) const {
287 MCInst Inst;
lib/Target/BPF/BPFAsmPrinter.cpp 141 MCInst TmpInst;
lib/Target/BPF/BPFMCInstLower.cpp 47 void BPFMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
lib/Target/BPF/BPFMCInstLower.h 34 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
lib/Target/BPF/BTFDebug.cpp 1123 bool BTFDebug::InstLower(const MachineInstr *MI, MCInst &OutMI) {
lib/Target/BPF/BTFDebug.h 326 bool InstLower(const MachineInstr *MI, MCInst &OutMI);
lib/Target/BPF/Disassembler/BPFDisassembler.cpp 68 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
101 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
116 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
127 static DecodeStatus decodeMemoryOpValue(MCInst &Inst, unsigned Insn,
162 DecodeStatus BPFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
221 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp 46 bool mayNeedRelaxation(const MCInst &Inst,
51 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
52 MCInst &Res) const override {}
lib/Target/BPF/MCTargetDesc/BPFInstPrinter.cpp 27 void BPFInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
50 void BPFInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
64 void BPFInstPrinter::printMemOperand(const MCInst *MI, int OpNo, raw_ostream &O,
85 void BPFInstPrinter::printImm64Operand(const MCInst *MI, unsigned OpNo,
96 void BPFInstPrinter::printBrTargetOperand(const MCInst *MI, unsigned OpNo,
lib/Target/BPF/MCTargetDesc/BPFInstPrinter.h 25 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
27 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
29 void printMemOperand(const MCInst *MI, int OpNo, raw_ostream &O,
31 void printImm64Operand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
32 void printBrTargetOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
35 void printInstruction(const MCInst *MI, raw_ostream &O);
lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp 47 uint64_t getBinaryCodeForInstr(const MCInst &MI,
53 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
57 uint64_t getMemoryOpValue(const MCInst &MI, unsigned Op,
61 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
68 verifyInstructionPredicates(const MCInst &MI,
86 unsigned BPFMCCodeEmitter::getMachineOpValue(const MCInst &MI,
118 void BPFMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
158 uint64_t BPFMCCodeEmitter::getMemoryOpValue(const MCInst &MI, unsigned Op,
lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp 78 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp 95 MCInst MCB;
126 void canonicalizeImmediates(MCInst &MCI);
127 bool matchOneInstruction(MCInst &MCB, SMLoc IDLoc,
139 int processInstruction(MCInst &Inst, OperandVector const &Operands,
378 void addRegOperands(MCInst &Inst, unsigned N) const {
383 void addImmOperands(MCInst &Inst, unsigned N) const {
388 void addSignedImmOperands(MCInst &Inst, unsigned N) const {
407 void addn1ConstOperands(MCInst &Inst, unsigned N) const {
531 void HexagonAsmParser::canonicalizeImmediates(MCInst &MCI) {
532 MCInst NewInst;
548 bool HexagonAsmParser::matchOneInstruction(MCInst &MCI, SMLoc IDLoc,
637 MCInst *SubInst = new (getParser().getContext()) MCInst;
637 MCInst *SubInst = new (getParser().getContext()) MCInst;
1223 static MCInst makeCombineInst(int opCode, MCOperand &Rdd, MCOperand &MO1,
1225 MCInst TmpInst;
1281 int HexagonAsmParser::processInstruction(MCInst &Inst,
1359 MCInst TmpInst;
1530 MCInst TmpInst;
1616 MCInst TmpInst;
1636 MCInst TmpInst;
1656 MCInst TmpInst;
1679 MCInst TmpInst;
1706 MCInst TmpInst;
1742 MCInst TmpInst;
1817 MCInst TmpInst;
1886 MCInst TmpInst;
1910 MCInst TmpInst;
lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp 46 std::unique_ptr<MCInst *> CurrentBundle;
47 mutable MCInst const *CurrentExtender;
51 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *),
54 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
54 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
58 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
62 void remapInstruction(MCInst &Instr) const;
65 static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI,
87 static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) {
98 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
101 static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst,
105 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo,
108 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
111 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
115 DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
117 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
120 static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst,
124 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
127 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
130 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
133 static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
136 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
139 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
142 static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
146 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
148 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
150 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
166 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
181 MCInst *Inst = new (getContext()) MCInst;
181 MCInst *Inst = new (getContext()) MCInst;
199 void HexagonDisassembler::remapInstruction(MCInst &Instr) const {
201 auto &MI = const_cast<MCInst &>(*I.getInst());
278 static void adjustDuplex(MCInst &MI, MCContext &Context) {
294 MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address,
294 MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address,
385 MCInst *MILow = new (getContext()) MCInst;
385 MCInst *MILow = new (getContext()) MCInst;
386 MCInst *MIHigh = new (getContext()) MCInst;
386 MCInst *MIHigh = new (getContext()) MCInst;
487 auto const &Inst = *i->getInst();
512 MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI)
522 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
532 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo,
538 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
553 static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst,
567 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
582 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
595 MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) {
603 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
616 static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst,
627 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
636 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
645 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
673 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
701 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
719 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
729 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
739 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
753 static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
779 static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
lib/Target/Hexagon/HexagonAsmPrinter.cpp 59 MCInst &MCB, HexagonAsmPrinter &AP);
246 static MCInst ScaleVectorOffset(MCInst &Inst, unsigned OpNo,
246 static MCInst ScaleVectorOffset(MCInst &Inst, unsigned OpNo,
248 MCInst T;
265 void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
267 MCInst &MappedInst = static_cast <MCInst &>(Inst);
334 MCInst TmpInst;
350 MCInst TmpInst;
431 MCInst TmpInst;
458 MCInst TmpInst;
494 MCInst TmpInst;
515 MCInst TmpInst;
606 MCInst TmpInst;
619 MCInst TmpInst;
744 MCInst MCB;
lib/Target/Hexagon/HexagonAsmPrinter.h 50 void HexagonProcessInstruction(MCInst &Inst, const MachineInstr &MBB);
lib/Target/Hexagon/HexagonDepDecoders.inc 18 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp,
23 static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp,
28 static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp,
33 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp,
38 static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp,
43 static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp,
48 static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp,
53 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp,
58 static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp,
63 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp,
68 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp,
lib/Target/Hexagon/HexagonMCInstLower.cpp 37 MCInst &MCB, HexagonAsmPrinter &AP);
98 MCInst &MCB, HexagonAsmPrinter &AP) {
107 MCInst *MCI = new (AP.OutContext) MCInst;
107 MCInst *MCI = new (AP.OutContext) MCInst;
lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp 44 std::unique_ptr <MCInst *> RelaxTarget;
45 MCInst * Extender;
48 MCInst &HMB) const {
64 MCII(T.createMCInstrInfo()), RelaxTarget(new MCInst *),
74 const_cast<HexagonAsmBackend *>(this)->Extender = new (Context) MCInst;
77 MCInst *takeExtender() const {
79 MCInst * Result = Extender;
535 bool isInstRelaxable(MCInst const &HMI) const {
561 bool mayNeedRelaxation(MCInst const &Inst,
573 MCInst const &MCB = DF->getInst();
577 MCInst &MCI = const_cast<MCInst &>(HexagonMCInstrInfo::instruction(
651 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
652 MCInst &Res) const override {
661 MCInst &CrntHMI = const_cast<MCInst &>(*I.getInst());
669 MCInst *HMIx = takeExtender();
730 auto &Inst = const_cast<MCInst &>(RF.getInst());
732 MCInst *Nop = new (Context) MCInst;
732 MCInst *Nop = new (Context) MCInst;
lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp 33 void HexagonInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
40 MCInst const &MCI = *I.getInst();
61 void HexagonInstPrinter::printOperand(MCInst const *MI, unsigned OpNo,
80 void HexagonInstPrinter::printBrtarget(MCInst const *MI, unsigned OpNo,
lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h 31 void printInst(MCInst const *MI, raw_ostream &O, StringRef Annot,
37 void printInstruction(MCInst const *MI, raw_ostream &O);
38 void printOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const;
39 void printBrtarget(MCInst const *MI, unsigned OpNo, raw_ostream &O) const;
lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp 55 MCInst const &Inst = *I.getInst();
66 void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg,
86 void HexagonMCChecker::init(MCInst const &MCI) {
192 MCSubtargetInfo const &STI, MCInst &mcb,
260 static bool isNeitherAnorX(MCInstrInfo const &MCII, MCInst const &ID) {
278 MCInst const *HasSoloAXInst = nullptr;
279 for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
286 for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
301 for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
312 for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
325 SmallVector<MCInst const *, 2> BranchLocations;
326 for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
332 MCInst const &I = *BranchLocations[J];
362 MCInst const &MCI = *HMI.getInst();
411 for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
495 MCInst const &Inst = *I.getInst();
512 for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB))
523 std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
526 std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
528 for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
552 for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
652 for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h 36 MCInst &MCB;
76 void init(MCInst const &);
77 void initReg(MCInst const &, unsigned, unsigned &PredReg, bool &isTrue);
80 std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
112 MCSubtargetInfo const &STI, MCInst &mcb,
lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp 340 uint32_t HexagonMCCodeEmitter::parseBits(size_t Last, MCInst const &MCB,
341 MCInst const &MCI) const {
367 void HexagonMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
370 MCInst &HMB = const_cast<MCInst &>(MI);
382 MCInst &HMI = const_cast<MCInst &>(*I.getInst());
406 void HexagonMCCodeEmitter::EncodeSingleInstruction(const MCInst &MI,
441 const MCInst *Sub0 = MI.getOperand(0).getInst();
442 const MCInst *Sub1 = MI.getOperand(1).getInst();
469 MCInstrInfo const &MCII, const MCInst &MI, const MCOperand &MO,
482 const MCInst &NextI = *(I+1)->getInst();
584 unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
719 HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
745 MCInst const &Inst = *I->getInst();
lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h 43 const MCInst *Bundle = nullptr;
52 void encodeInstruction(MCInst const &MI, raw_ostream &OS,
56 void EncodeSingleInstruction(const MCInst &MI, raw_ostream &OS,
63 uint64_t getBinaryCodeForInstr(MCInst const &MI,
68 unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO,
74 unsigned getExprOpValue(const MCInst &MI, const MCOperand &MO,
78 Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI,
83 uint32_t parseBits(size_t Last, MCInst const &MCB, MCInst const &MCI) const;
83 uint32_t parseBits(size_t Last, MCInst const &MCB, MCInst const &MCI) const;
87 verifyInstructionPredicates(const MCInst &MI,
lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp 79 static unsigned getCompoundCandidateGroup(MCInst const &MI, bool IsExtended) {
174 static unsigned getCompoundOp(MCInst const &HMCI) {
196 static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L,
196 static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L,
197 MCInst const &R) {
198 MCInst *CompoundInsn = nullptr;
212 CompoundInsn = new (Context) MCInst;
225 CompoundInsn = new (Context) MCInst;
239 CompoundInsn = new (Context) MCInst;
252 CompoundInsn = new (Context) MCInst;
265 CompoundInsn = new (Context) MCInst;
283 CompoundInsn = new (Context) MCInst;
301 CompoundInsn = new (Context) MCInst;
312 CompoundInsn = new (Context) MCInst;
323 CompoundInsn = new (Context) MCInst;
334 static bool isOrderedCompoundPair(MCInst const &MIa, bool IsExtendedA,
335 MCInst const &MIb, bool IsExtendedB) {
349 MCInst &MCI) {
352 for (MCInst::iterator J =
355 MCInst const *JumpInst = J->getInst();
363 for (MCInst::iterator B =
366 MCInst const *Inst = B->getInst();
376 MCInst *CompoundInsn = getCompoundInsn(Context, *Inst, *JumpInst);
399 MCContext &Context, MCInst &MCI) {
410 MCInst CheckList(MCI);
416 MCInst OriginalBundle(MCI);
lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp 190 unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) {
541 bool HexagonMCInstrInfo::subInstWouldBeExtended(MCInst const &potentialDuplex) {
579 MCInst const &MIa, bool ExtendedA,
580 MCInst const &MIb, bool ExtendedB,
601 MCInst SubInst0 = HexagonMCInstrInfo::deriveSubInst(MIa);
602 MCInst SubInst1 = HexagonMCInstrInfo::deriveSubInst(MIb);
657 bool HexagonMCInstrInfo::isDuplexPair(MCInst const &MIa, MCInst const &MIb) {
657 bool HexagonMCInstrInfo::isDuplexPair(MCInst const &MIa, MCInst const &MIb) {
663 inline static void addOps(MCInst &subInstPtr, MCInst const &Inst,
663 inline static void addOps(MCInst &subInstPtr, MCInst const &Inst,
702 MCInst HexagonMCInstrInfo::deriveSubInst(MCInst const &Inst) {
702 MCInst HexagonMCInstrInfo::deriveSubInst(MCInst const &Inst) {
703 MCInst Result;
lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp 61 void HexagonMCELFStreamer::EmitInstruction(const MCInst &MCB,
70 MCInst *MCI = const_cast<MCInst *>(I.getInst());
77 void HexagonMCELFStreamer::EmitSymbol(const MCInst &Inst) {
lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h 33 void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override;
34 void EmitSymbol(const MCInst &Inst);
lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp 39 MCInst const &Inst)
45 MCInst const &Inst, std::nullptr_t)
61 MCInst const &Inst = *BundleCurrent->getInst();
70 MCInst const &Hexagon::PacketIterator::operator*() const {
81 void HexagonMCInstrInfo::addConstant(MCInst &MI, uint64_t Value,
87 MCInstrInfo const &MCII, MCInst &MCB,
88 MCInst const &MCI) {
94 MCInst *XMCI =
95 new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp));
103 MCInst const &MCI) {
109 iterator_range<MCInst::const_iterator>
110 HexagonMCInstrInfo::bundleInstructions(MCInst const &MCI) {
115 size_t HexagonMCInstrInfo::bundleSize(MCInst const &MCI) {
124 MCContext &Context, MCInst &MCB,
137 MCInst InstBundlePreDuplex = MCInst(MCB);
159 MCInst HexagonMCInstrInfo::deriveExtender(MCInstrInfo const &MCII,
160 MCInst const &Inst,
165 MCInst XMI;
176 MCInst *HexagonMCInstrInfo::deriveDuplex(MCContext &Context, unsigned iClass,
177 MCInst const &inst0,
178 MCInst const &inst1) {
180 MCInst *duplexInst = new (Context) MCInst;
180 MCInst *duplexInst = new (Context) MCInst;
183 MCInst *SubInst0 = new (Context) MCInst(deriveSubInst(inst0));
183 MCInst *SubInst0 = new (Context) MCInst(deriveSubInst(inst0));
184 MCInst *SubInst1 = new (Context) MCInst(deriveSubInst(inst1));
184 MCInst *SubInst1 = new (Context) MCInst(deriveSubInst(inst1));
190 MCInst const *HexagonMCInstrInfo::extenderForIndex(MCInst const &MCB,
190 MCInst const *HexagonMCInstrInfo::extenderForIndex(MCInst const &MCB,
195 MCInst const *Inst =
203 MCInstrInfo const &MCII, MCInst &MCB,
204 MCInst const &MCI) {
210 MCInst const &MCI) {
217 MCInst const &MCI) {
224 MCInst const &MCI) {
285 MCInst const &MCI) {
292 MCInst const &MCI) {
303 MCInst const &MCI) {
309 MCInst const &MCI) {
315 MCInst const &MCI) {
322 MCInst const &MCI) {
333 MCInst const &MCI) {
343 MCInst const &MCI) {
348 MCInst const &MCI) {
354 MCInst const &MCI) {
373 MCInst const &MCI) {
380 MCInst const &MCI) {
392 MCInst const &MCI) {
400 MCInst const &MCI) {
411 MCInst const &MCI) {
432 bool HexagonMCInstrInfo::hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
444 bool HexagonMCInstrInfo::hasExtenderForIndex(MCInst const &MCB, size_t Index) {
448 bool HexagonMCInstrInfo::hasImmExt(MCInst const &MCI) {
462 MCInst const &MCI) {
469 MCInst const &MCI) {
474 MCInst const &HexagonMCInstrInfo::instruction(MCInst const &MCB, size_t Index) {
474 MCInst const &HexagonMCInstrInfo::instruction(MCInst const &MCB, size_t Index) {
482 MCInst const &MCI) {
487 bool HexagonMCInstrInfo::isBundle(MCInst const &MCI) {
494 MCInst const &MCI) {
527 bool HexagonMCInstrInfo::isCanon(MCInstrInfo const &MCII, MCInst const &MCI) {
532 bool HexagonMCInstrInfo::isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI) {
538 MCInst const &MCI) {
544 MCInst const &MCI) {
550 MCInst const &MCI) {
554 bool HexagonMCInstrInfo::isCVINew(MCInstrInfo const &MCII, MCInst const &MCI) {
564 bool HexagonMCInstrInfo::isDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
569 MCInst const &MCI) {
575 MCInst const &MCI) {
580 bool HexagonMCInstrInfo::isFloat(MCInstrInfo const &MCII, MCInst const &MCI) {
585 bool HexagonMCInstrInfo::isHVX(MCInstrInfo const &MCII, MCInst const &MCI) {
590 bool HexagonMCInstrInfo::isImmext(MCInst const &MCI) {
594 bool HexagonMCInstrInfo::isInnerLoop(MCInst const &MCI) {
611 MCInst const &MCI) {
618 MCInst const &MCI, unsigned short O) {
622 bool HexagonMCInstrInfo::isOuterLoop(MCInst const &MCI) {
629 MCInst const &MCI) {
634 bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) {
639 MCInst const &MCI) {
646 MCInst const &MCI) {
652 MCInst const &MCI) {
663 bool HexagonMCInstrInfo::isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI) {
670 MCInst const &MCI) {
677 MCInst const &MCI) {
684 bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) {
689 bool HexagonMCInstrInfo::isMemReorderDisabled(MCInst const &MCI) {
695 bool HexagonMCInstrInfo::isSubInstruction(MCInst const &MCI) {
755 bool HexagonMCInstrInfo::isVector(MCInstrInfo const &MCII, MCInst const &MCI) {
762 int64_t HexagonMCInstrInfo::minConstant(MCInst const &MCI, size_t Index) {
805 void HexagonMCInstrInfo::padEndloop(MCInst &MCB, MCContext &Context) {
806 MCInst Nop;
813 MCB.addOperand(MCOperand::createInst(new (Context) MCInst(Nop)));
817 HexagonMCInstrInfo::predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI) {
828 MCInst const &MCI) {
834 bool HexagonMCInstrInfo::hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI) {
839 void HexagonMCInstrInfo::replaceDuplex(MCContext &Context, MCInst &MCB,
844 MCInst *Duplex =
853 void HexagonMCInstrInfo::setInnerLoop(MCInst &MCI) {
859 void HexagonMCInstrInfo::setMemReorderDisabled(MCInst &MCI) {
866 void HexagonMCInstrInfo::setOuterLoop(MCInst &MCI) {
lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h 45 MCInst::const_iterator BundleCurrent;
46 MCInst::const_iterator BundleEnd;
47 MCInst::const_iterator DuplexCurrent;
48 MCInst::const_iterator DuplexEnd;
51 PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst);
52 PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst, std::nullptr_t);
55 MCInst const &operator*() const;
79 void addConstant(MCInst &MI, uint64_t Value, MCContext &Context);
80 void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
81 MCInst const &MCI);
85 bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI);
86 iterator_range<MCInst::const_iterator> bundleInstructions(MCInst const &MCI);
86 iterator_range<MCInst::const_iterator> bundleInstructions(MCInst const &MCI);
89 size_t bundleSize(MCInst const &MCI);
93 MCContext &Context, MCInst &MCB,
97 MCInst *deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0,
97 MCInst *deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0,
98 MCInst const &inst1);
99 MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst,
99 MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst,
103 MCInst deriveSubInst(MCInst const &Inst);
103 MCInst deriveSubInst(MCInst const &Inst);
106 MCInst const *extenderForIndex(MCInst const &MCB, size_t Index);
106 MCInst const *extenderForIndex(MCInst const &MCB, size_t Index);
107 void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
108 MCInst const &MCI);
111 unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI);
114 unsigned getAddrMode(MCInstrInfo const &MCII, MCInst const &MCI);
116 MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI);
119 unsigned getDuplexCandidateGroup(MCInst const &MI);
124 MCInst const &MCB);
130 unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI);
134 MCInst const &MCI);
137 unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI);
140 unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI);
143 bool isExtentSigned(MCInstrInfo const &MCII, MCInst const &MCI);
147 int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI);
151 int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI);
154 StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI);
157 unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI);
160 MCOperand const &getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI);
161 unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI);
163 MCInst const &MCI);
166 unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI);
170 MCInst const &MCI);
172 MCSubtargetInfo const &STI, MCInst const &MCI);
173 bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI);
176 bool hasExtenderForIndex(MCInst const &MCB, size_t Index);
178 bool hasImmExt(MCInst const &MCI);
181 bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI);
182 bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI);
183 bool hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI);
186 int64_t minConstant(MCInst const &MCI, size_t Index);
188 bool inRange(MCInst const &MCI, size_t Index) {
192 bool inSRange(MCInst const &MCI, size_t Index) {
195 template <unsigned N> bool inRange(MCInst const &MCI, size_t Index) {
200 MCInst const &instruction(MCInst const &MCB, size_t Index);
200 MCInst const &instruction(MCInst const &MCB, size_t Index);
201 bool isAccumulator(MCInstrInfo const &MCII, MCInst const &MCI);
204 bool isBundle(MCInst const &MCI);
207 bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI);
208 bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI);
209 bool isCofRelax1(MCInstrInfo const &MCII, MCInst const &MCI);
210 bool isCofRelax2(MCInstrInfo const &MCII, MCInst const &MCI);
211 bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI);
214 bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI);
215 bool isCVINew(MCInstrInfo const &MCII, MCInst const &MCI);
221 bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI);
224 bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
224 bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
230 bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI);
233 bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI);
236 bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI);
238 bool isHVX(MCInstrInfo const &MCII, MCInst const &MCI);
241 bool isImmext(MCInst const &MCI);
244 bool isInnerLoop(MCInst const &MCI);
251 bool isMemReorderDisabled(MCInst const &MCI);
254 bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI);
255 bool isOpExtendable(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short);
258 bool isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa,
259 bool ExtendedA, MCInst const &MIb, bool ExtendedB,
263 bool isOuterLoop(MCInst const &MCI);
266 bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI);
267 bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI);
268 bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI);
271 bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI);
277 bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI);
280 bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI);
283 bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI);
286 bool isRestrictSlot1AOK(MCInstrInfo const &MCII, MCInst const &MCI);
287 bool isRestrictNoSlot1Store(MCInstrInfo const &MCII, MCInst const &MCI);
288 bool isSubInstruction(MCInst const &MCI);
289 bool isVector(MCInstrInfo const &MCII, MCInst const &MCI);
294 void padEndloop(MCInst &MCI, MCContext &Context);
305 PredicateInfo predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI);
306 bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI);
309 void replaceDuplex(MCContext &Context, MCInst &MCI, DuplexCandidate Candidate);
313 void setInnerLoop(MCInst &MCI);
314 void setMemReorderDisabled(MCInst &MCI);
320 void setOuterLoop(MCInst &MCI);
323 bool subInstWouldBeExtended(MCInst const &potentialDuplex);
329 MCContext &Context, MCInst &MCI);
lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp 33 void HexagonMCShuffler::init(MCInst &MCB) {
35 MCInst const *Extender = nullptr;
38 MCInst &MI = *const_cast<MCInst *>(I.getInst());
55 void HexagonMCShuffler::init(MCInst &MCB, MCInst const &AddMI,
55 void HexagonMCShuffler::init(MCInst &MCB, MCInst const &AddMI,
60 MCInst const *Extender = nullptr;
64 MCInst &MI = *const_cast<MCInst *>(I.getInst());
79 void HexagonMCShuffler::copyTo(MCInst &MCB) {
86 MCInst const &MI = I->getDesc();
87 MCInst const *Extender = I->getExtender();
94 bool HexagonMCShuffler::reshuffleTo(MCInst &MCB) {
106 MCInst &MCB) {
133 MCSubtargetInfo const &STI, MCInst &MCB,
157 MCInst Attempt(MCB);
183 MCSubtargetInfo const &STI, MCInst &MCB,
184 MCInst const &AddMI, int fixupCount) {
lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.h 32 MCSubtargetInfo const &STI, MCInst &MCB)
38 MCSubtargetInfo const &STI, MCInst &MCB,
39 MCInst const &AddMI, bool InsertAtFront)
45 void copyTo(MCInst &MCB);
48 bool reshuffleTo(MCInst &MCB);
51 void init(MCInst &MCB);
52 void init(MCInst &MCB, MCInst const &AddMI, bool InsertAtFront);
52 void init(MCInst &MCB, MCInst const &AddMI, bool InsertAtFront);
57 MCSubtargetInfo const &STI, MCInst &MCB);
59 MCSubtargetInfo const &STI, MCInst &MCB,
60 MCInst const &AddMI, int fixupCount);
62 MCSubtargetInfo const &STI, MCInst &MCB,
lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp 141 const MCInst &Inst, const MCSubtargetInfo &STI) override {
427 bool isUnconditionalBranch(MCInst const &Inst) const override {
432 bool isConditionalBranch(MCInst const &Inst) const override {
437 bool evaluateBranch(MCInst const &Inst, uint64_t Addr,
lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp 146 MCInst const *id)
212 void HexagonShuffler::append(MCInst const &ID, MCInst const *Extender,
212 void HexagonShuffler::append(MCInst const &ID, MCInst const *Extender,
229 MCInst const &Inst = ISJ->getDesc();
237 MCInst const &Inst = ISJ->getDesc();
260 MCInst const &Inst = ISJ->getDesc();
269 MCInst const &Inst = ISJ->getDesc();
315 MCInst const &ID = ISJ->getDesc();
400 MCInst const &Inst0 = *ID.getOperand(0).getInst();
401 MCInst const &Inst1 = *ID.getOperand(1).getInst();
430 MCInst const &ID = ISJ->getDesc();
574 MCInst const &ID = ISJ->getDesc();
lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h 94 unsigned s, MCInst const *id);
108 MCInst const *ID;
109 MCInst const *Extender;
115 MCInstrInfo const &MCII, MCInst const *id,
116 MCInst const *Extender, unsigned s)
119 MCInst const &getDesc() const { return *ID; }
120 MCInst const *getExtender() const { return Extender; }
184 void append(MCInst const &ID, MCInst const *Extender, unsigned S);
184 void append(MCInst const &ID, MCInst const *Extender, unsigned S);
lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp 389 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
400 void addRegOperands(MCInst &Inst, unsigned N) const {
405 void addImmOperands(MCInst &Inst, unsigned N) const {
410 void addBrTargetOperands(MCInst &Inst, unsigned N) const {
415 void addCallTargetOperands(MCInst &Inst, unsigned N) const {
420 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
425 void addMemImmOperands(MCInst &Inst, unsigned N) const {
431 void addMemRegImmOperands(MCInst &Inst, unsigned N) const {
439 void addMemRegRegOperands(MCInst &Inst, unsigned N) const {
447 void addMemSplsOperands(MCInst &Inst, unsigned N) const {
454 void addImmShiftOperands(MCInst &Inst, unsigned N) const {
459 void addImm10Operands(MCInst &Inst, unsigned N) const {
464 void addLoImm16Operands(MCInst &Inst, unsigned N) const {
488 void addLoImm16AndOperands(MCInst &Inst, unsigned N) const {
496 void addHiImm16Operands(MCInst &Inst, unsigned N) const {
519 void addHiImm16AndOperands(MCInst &Inst, unsigned N) const {
527 void addLoImm21Operands(MCInst &Inst, unsigned N) const {
655 MCInst Inst;
lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp 50 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
54 static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
57 static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn,
60 static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn,
63 static DecodeStatus decodeBranch(MCInst &Inst, unsigned Insn, uint64_t Address,
66 static DecodeStatus decodePredicateOperand(MCInst &Inst, unsigned Val,
70 static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn,
90 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) {
132 MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address,
162 DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
173 static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
185 static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn,
197 static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn,
211 uint64_t Width, MCInst &MI,
218 static DecodeStatus decodeBranch(MCInst &MI, unsigned Insn, uint64_t Address,
226 static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn,
234 static DecodeStatus decodePredicateOperand(MCInst &Inst, unsigned Val,
lib/Target/Lanai/Disassembler/LanaiDisassembler.h 30 getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes,
lib/Target/Lanai/LanaiAsmPrinter.cpp 175 MCInst TmpInst;
192 MCInst TmpInst;
lib/Target/Lanai/LanaiMCInstLower.cpp 93 void LanaiMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
lib/Target/Lanai/LanaiMCInstLower.h 34 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp 72 bool mayNeedRelaxation(const MCInst & /*Inst*/,
77 void relaxInstruction(const MCInst & /*Inst*/,
79 MCInst & /*Res*/) const override {}
lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.cpp 38 bool LanaiInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
48 static bool usesGivenOffset(const MCInst *MI, int AddOffset) {
55 static bool isPreIncrementForm(const MCInst *MI, int AddOffset) {
60 static bool isPostIncrementForm(const MCInst *MI, int AddOffset) {
65 static StringRef decIncOperator(const MCInst *MI) {
71 bool LanaiInstPrinter::printMemoryLoadIncrement(const MCInst *MI,
90 bool LanaiInstPrinter::printMemoryStoreIncrement(const MCInst *MI,
109 bool LanaiInstPrinter::printAlias(const MCInst *MI, raw_ostream &OS) {
140 void LanaiInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
148 void LanaiInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
162 void LanaiInstPrinter::printMemImmOperand(const MCInst *MI, unsigned OpNo,
176 void LanaiInstPrinter::printHi16ImmOperand(const MCInst *MI, unsigned OpNo,
188 void LanaiInstPrinter::printHi16AndImmOperand(const MCInst *MI, unsigned OpNo,
200 void LanaiInstPrinter::printLo16AndImmOperand(const MCInst *MI, unsigned OpNo,
236 void LanaiInstPrinter::printMemRiOperand(const MCInst *MI, int OpNo,
251 void LanaiInstPrinter::printMemRrOperand(const MCInst *MI, int OpNo,
272 void LanaiInstPrinter::printMemSplsOperand(const MCInst *MI, int OpNo,
287 void LanaiInstPrinter::printCCOperand(const MCInst *MI, int OpNo,
298 void LanaiInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h 27 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
29 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
31 void printPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
32 void printMemRiOperand(const MCInst *MI, int OpNo, raw_ostream &O,
34 void printMemRrOperand(const MCInst *MI, int OpNo, raw_ostream &O,
36 void printMemSplsOperand(const MCInst *MI, int OpNo, raw_ostream &O,
38 void printCCOperand(const MCInst *MI, int OpNo, raw_ostream &O);
39 void printAluOperand(const MCInst *MI, int OpNo, raw_ostream &O);
40 void printHi16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
41 void printHi16AndImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
42 void printLo16AndImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
43 void printMemImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
46 void printInstruction(const MCInst *MI, raw_ostream &O);
47 bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
48 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
54 bool printAlias(const MCInst *MI, raw_ostream &Ostream);
55 bool printInst(const MCInst *MI, raw_ostream &Ostream, StringRef Alias,
57 bool printMemoryLoadIncrement(const MCInst *MI, raw_ostream &Ostream,
59 bool printMemoryStoreIncrement(const MCInst *MI, raw_ostream &Ostream,
lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp 51 uint64_t getBinaryCodeForInstr(const MCInst &Inst,
57 unsigned getMachineOpValue(const MCInst &Inst, const MCOperand &MCOp,
61 unsigned getRiMemoryOpValue(const MCInst &Inst, unsigned OpNo,
65 unsigned getRrMemoryOpValue(const MCInst &Inst, unsigned OpNo,
69 unsigned getSplsOpValue(const MCInst &Inst, unsigned OpNo,
73 unsigned getBranchTargetOpValue(const MCInst &Inst, unsigned OpNo,
77 void encodeInstruction(const MCInst &Inst, raw_ostream &Ostream,
81 unsigned adjustPqBitsRmAndRrm(const MCInst &Inst, unsigned Value,
84 unsigned adjustPqBitsSpls(const MCInst &Inst, unsigned Value,
110 const MCInst &Inst, const MCOperand &MCOp, SmallVectorImpl<MCFixup> &Fixups,
135 static unsigned adjustPqBits(const MCInst &Inst, unsigned Value,
161 LanaiMCCodeEmitter::adjustPqBitsRmAndRrm(const MCInst &Inst, unsigned Value,
167 LanaiMCCodeEmitter::adjustPqBitsSpls(const MCInst &Inst, unsigned Value,
173 const MCInst &Inst, raw_ostream &Ostream, SmallVectorImpl<MCFixup> &Fixups,
186 const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
218 const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
256 LanaiMCCodeEmitter::getSplsOpValue(const MCInst &Inst, unsigned OpNo,
289 const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp 96 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp 124 void addRegOperands(MCInst &Inst, unsigned N) const {
132 void addExprOperand(MCInst &Inst, const MCExpr *Expr) const {
142 void addImmOperands(MCInst &Inst, unsigned N) const {
149 void addMemOperands(MCInst &Inst, unsigned N) const {
257 MCInst Inst;
lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp 33 DecodeStatus getInstructionI(MCInst &MI, uint64_t &Size,
38 DecodeStatus getInstructionII(MCInst &MI, uint64_t &Size,
43 DecodeStatus getInstructionCJ(MCInst &MI, uint64_t &Size,
52 DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
77 static DecodeStatus DecodeGR8RegisterClass(MCInst &MI, uint64_t RegNo,
95 static DecodeStatus DecodeGR16RegisterClass(MCInst &MI, uint64_t RegNo,
106 static DecodeStatus DecodeCGImm(MCInst &MI, uint64_t Bits, uint64_t Address,
109 static DecodeStatus DecodeMemOperand(MCInst &MI, uint64_t Bits,
115 static DecodeStatus DecodeCGImm(MCInst &MI, uint64_t Bits, uint64_t Address,
132 static DecodeStatus DecodeMemOperand(MCInst &MI, uint64_t Bits,
233 DecodeStatus MSP430Disassembler::getInstructionI(MCInst &MI, uint64_t &Size,
289 DecodeStatus MSP430Disassembler::getInstructionII(MCInst &MI, uint64_t &Size,
345 DecodeStatus MSP430Disassembler::getInstructionCJ(MCInst &MI, uint64_t &Size,
367 DecodeStatus MSP430Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp 93 bool mayNeedRelaxation(const MCInst &Inst,
98 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
99 MCInst &Res) const override {}
lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.cpp 29 void MSP430InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
36 void MSP430InstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo,
51 void MSP430InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
66 void MSP430InstPrinter::printSrcMemOperand(const MCInst *MI, unsigned OpNo,
96 void MSP430InstPrinter::printIndRegOperand(const MCInst *MI, unsigned OpNo,
102 void MSP430InstPrinter::printPostIndRegOperand(const MCInst *MI, unsigned OpNo,
108 void MSP430InstPrinter::printCCOperand(const MCInst *MI, unsigned OpNo,
lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h 25 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
29 void printInstruction(const MCInst *MI, raw_ostream &O);
30 bool printAliasInstr(const MCInst *MI, raw_ostream &O);
31 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
36 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
38 void printPCRelImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
39 void printSrcMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
41 void printIndRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
42 void printPostIndRegOperand(const MCInst *MI, unsigned OpNo,
44 void printCCOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
lib/Target/MSP430/MCTargetDesc/MSP430MCCodeEmitter.cpp 45 uint64_t getBinaryCodeForInstr(const MCInst &MI,
53 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
57 unsigned getMemOpValue(const MCInst &MI, unsigned Op,
61 unsigned getPCRelImmOpValue(const MCInst &MI, unsigned Op,
65 unsigned getCGImmOpValue(const MCInst &MI, unsigned Op,
69 unsigned getCCOpValue(const MCInst &MI, unsigned Op,
77 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
82 void MSP430MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
101 unsigned MSP430MCCodeEmitter::getMachineOpValue(const MCInst &MI,
120 unsigned MSP430MCCodeEmitter::getMemOpValue(const MCInst &MI, unsigned Op,
152 unsigned MSP430MCCodeEmitter::getPCRelImmOpValue(const MCInst &MI, unsigned Op,
165 unsigned MSP430MCCodeEmitter::getCGImmOpValue(const MCInst &MI, unsigned Op,
184 unsigned MSP430MCCodeEmitter::getCCOpValue(const MCInst &MI, unsigned Op,
lib/Target/MSP430/MSP430AsmPrinter.cpp 154 MCInst TmpInst;
lib/Target/MSP430/MSP430MCInstLower.cpp 115 void MSP430MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
lib/Target/MSP430/MSP430MCInstLower.h 33 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 162 void ConvertXWPOperands(MCInst &Inst, const OperandVector &Operands);
168 checkEarlyTargetMatchPredicate(MCInst &Inst,
170 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
217 MacroExpanderResultTy tryExpandInstruction(MCInst &Inst, SMLoc IDLoc,
221 bool expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
234 bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
237 bool expandLoadSingleImmToGPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
239 bool expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
241 bool expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
243 bool expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU, SMLoc IDLoc,
251 bool expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
254 void expandMemInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
257 bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
260 bool expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
263 bool expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
266 bool expandCondBranches(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
269 bool expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
273 bool expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU, SMLoc IDLoc,
276 bool expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, MCStreamer &Out,
279 bool expandUsh(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
282 bool expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
285 bool expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
288 bool expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
291 bool expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
294 bool expandRotation(MCInst &Inst, SMLoc IDLoc,
296 bool expandRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
298 bool expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
300 bool expandDRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
303 bool expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
306 bool expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
309 bool expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
312 bool expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
315 bool expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
318 bool expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
321 bool expandStoreDM1Macro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
324 bool expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
327 bool expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
330 bool expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
419 bool processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
1008 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1018 void addRegOperands(MCInst &Inst, unsigned N) const {
1025 void addGPR32ZeroAsmRegOperands(MCInst &Inst, unsigned N) const {
1030 void addGPR32NonZeroAsmRegOperands(MCInst &Inst, unsigned N) const {
1035 void addGPR32AsmRegOperands(MCInst &Inst, unsigned N) const {
1040 void addGPRMM16AsmRegOperands(MCInst &Inst, unsigned N) const {
1045 void addGPRMM16AsmRegZeroOperands(MCInst &Inst, unsigned N) const {
1050 void addGPRMM16AsmRegMovePOperands(MCInst &Inst, unsigned N) const {
1055 void addGPRMM16AsmRegMovePPairFirstOperands(MCInst &Inst, unsigned N) const {
1060 void addGPRMM16AsmRegMovePPairSecondOperands(MCInst &Inst,
1069 void addGPR64AsmRegOperands(MCInst &Inst, unsigned N) const {
1074 void addAFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
1079 void addStrictlyAFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
1084 void addStrictlyFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
1089 void addFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
1094 void addFGR32AsmRegOperands(MCInst &Inst, unsigned N) const {
1105 void addStrictlyFGR32AsmRegOperands(MCInst &Inst, unsigned N) const {
1114 void addFCCAsmRegOperands(MCInst &Inst, unsigned N) const {
1119 void addMSA128AsmRegOperands(MCInst &Inst, unsigned N) const {
1124 void addMSACtrlAsmRegOperands(MCInst &Inst, unsigned N) const {
1129 void addCOP0AsmRegOperands(MCInst &Inst, unsigned N) const {
1134 void addCOP2AsmRegOperands(MCInst &Inst, unsigned N) const {
1139 void addCOP3AsmRegOperands(MCInst &Inst, unsigned N) const {
1144 void addACC64DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
1149 void addHI32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
1154 void addLO32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
1159 void addCCRAsmRegOperands(MCInst &Inst, unsigned N) const {
1164 void addHWRegsAsmRegOperands(MCInst &Inst, unsigned N) const {
1170 void addConstantUImmOperands(MCInst &Inst, unsigned N) const {
1180 void addSImmOperands(MCInst &Inst, unsigned N) const {
1189 void addUImmOperands(MCInst &Inst, unsigned N) const {
1198 void addConstantSImmOperands(MCInst &Inst, unsigned N) const {
1207 void addImmOperands(MCInst &Inst, unsigned N) const {
1213 void addMemOperands(MCInst &Inst, unsigned N) const {
1224 void addMicroMipsMemOperands(MCInst &Inst, unsigned N) const {
1233 void addRegListOperands(MCInst &Inst, unsigned N) const {
1720 static bool hasShortDelaySlot(MCInst &Inst) {
1780 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
2009 MCInst BInst;
2040 MCInst JalrInst;
2304 MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
2551 bool MipsAsmParser::expandJalWithRegs(MCInst &Inst, SMLoc IDLoc,
2557 MCInst JalrInst;
2778 bool MipsAsmParser::expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
3277 bool MipsAsmParser::expandLoadSingleImmToGPR(MCInst &Inst, SMLoc IDLoc,
3293 bool MipsAsmParser::expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc,
3347 bool MipsAsmParser::expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc,
3412 bool MipsAsmParser::expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU,
3485 bool MipsAsmParser::expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc,
3530 bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
3596 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
3715 bool MipsAsmParser::expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc,
3744 bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc,
4015 bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4186 bool MipsAsmParser::expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU,
4225 bool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc,
4277 bool MipsAsmParser::expandUsh(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4328 bool MipsAsmParser::expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4383 bool MipsAsmParser::expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4417 bool MipsAsmParser::expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4473 bool MipsAsmParser::expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4520 bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc,
4627 bool MipsAsmParser::expandRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4689 bool MipsAsmParser::expandRotationImm(MCInst &Inst, SMLoc IDLoc,
4752 bool MipsAsmParser::expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4814 bool MipsAsmParser::expandDRotationImm(MCInst &Inst, SMLoc IDLoc,
4826 MCInst TmpInst;
4909 bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4925 bool MipsAsmParser::expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4948 bool MipsAsmParser::expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4990 bool MipsAsmParser::expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5026 bool MipsAsmParser::expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5044 bool MipsAsmParser::expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc,
5092 bool MipsAsmParser::expandStoreDM1Macro(MCInst &Inst, SMLoc IDLoc,
5129 bool MipsAsmParser::expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5155 bool MipsAsmParser::expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5212 static unsigned getRegisterForMxtrDSP(MCInst &Inst, bool IsMFDSP) {
5266 static unsigned getRegisterForMxtrFP(MCInst &Inst, bool IsMFTC1) {
5305 static unsigned getRegisterForMxtrC0(MCInst &Inst, bool IsMFTC0) {
5345 bool MipsAsmParser::expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5416 MipsAsmParser::checkEarlyTargetMatchPredicate(MCInst &Inst,
5430 unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
5586 MCInst Inst;
5791 void MipsAsmParser::ConvertXWPOperands(MCInst &Inst,
lib/Target/Mips/Disassembler/MipsDisassembler.cpp 71 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
81 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
86 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
91 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
96 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
101 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
106 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
111 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
116 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
121 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
126 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
131 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
136 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
141 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
145 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
150 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
155 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
160 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
165 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
170 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
175 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
180 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
185 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
190 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
195 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
200 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
205 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
210 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst,
215 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
220 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
225 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst,
230 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
237 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
244 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
251 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
258 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst,
265 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
272 static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst,
277 static DecodeStatus DecodeMem(MCInst &Inst,
282 static DecodeStatus DecodeMemEVA(MCInst &Inst,
287 static DecodeStatus DecodeLoadByte15(MCInst &Inst,
292 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
295 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
300 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
305 static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
310 static DecodeStatus DecodeSyncI(MCInst &Inst,
315 static DecodeStatus DecodeSyncI_MM(MCInst &Inst,
320 static DecodeStatus DecodeSynciR6(MCInst &Inst,
325 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
328 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
333 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
338 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
343 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
348 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
353 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
358 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
363 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
367 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
371 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address,
374 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address,
377 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
380 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
384 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
389 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
394 static DecodeStatus DecodeLi16Imm(MCInst &Inst,
399 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
405 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
410 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value,
418 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
422 static DecodeStatus DecodeInsSize(MCInst &Inst,
427 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
430 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
433 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
436 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
439 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
445 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
449 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
453 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
457 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
461 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
466 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
471 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
476 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
481 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
486 DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
491 DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
496 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
501 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
506 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
511 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
516 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
521 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
525 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
529 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
533 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
536 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
540 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
544 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
548 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,
586 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
588 using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *);
633 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
647 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
661 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
700 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn,
734 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
773 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn,
807 static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn,
846 static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn,
885 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
928 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
972 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
1021 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
1065 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
1105 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
1145 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
1214 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
1383 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
1390 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
1402 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
1413 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
1424 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
1435 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
1446 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
1456 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
1463 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1475 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1487 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1498 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1509 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1520 static DecodeStatus DecodeMem(MCInst &Inst,
1542 static DecodeStatus DecodeMemEVA(MCInst &Inst,
1563 static DecodeStatus DecodeLoadByte15(MCInst &Inst,
1581 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1598 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1615 static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
1632 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
1649 static DecodeStatus DecodeSyncI(MCInst &Inst,
1664 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn,
1677 static DecodeStatus DecodeSynciR6(MCInst &Inst,
1692 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1738 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1796 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1812 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
1828 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
1853 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
1874 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1909 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1927 static DecodeStatus DecodeFMem(MCInst &Inst,
1945 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
1963 static DecodeStatus DecodeFMem2(MCInst &Inst,
1981 static DecodeStatus DecodeFMem3(MCInst &Inst,
1999 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
2017 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
2033 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
2055 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
2066 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
2078 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
2090 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
2102 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
2114 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
2126 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
2138 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
2150 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
2162 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
2174 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
2186 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
2198 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
2207 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst,
2216 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
2225 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
2235 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst,
2245 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
2255 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
2264 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
2273 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
2282 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst,
2292 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
2301 static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst,
2310 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
2323 static DecodeStatus DecodeLi16Imm(MCInst &Inst,
2334 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
2343 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
2353 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
2361 static DecodeStatus DecodeInsSize(MCInst &Inst,
2374 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
2380 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
2386 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
2400 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
2410 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
2439 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
2463 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,
2489 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
2531 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
2538 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn,
2587 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn,
lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h 62 bool mayNeedRelaxation(const MCInst &Inst,
83 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
84 MCInst &Res) const override {}
lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp 36 void MipsELFStreamer::EmitInstruction(const MCInst &Inst,
lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h 44 void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override;
lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp 31 static bool isReg(const MCInst &MI, unsigned OpNo) {
78 void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
124 void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
142 void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
157 printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) {
184 printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O) {
193 printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) {
199 printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) {
203 bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
210 bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
219 bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) {
268 void MipsInstPrinter::printSaveRestore(const MCInst *MI, raw_ostream &O) {
279 printRegisterList(const MCInst *MI, int opNum, raw_ostream &O) {
lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h 82 void printInstruction(const MCInst *MI, raw_ostream &O);
86 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
89 bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
90 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
94 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
96 void printUImm(const MCInst *MI, int opNum, raw_ostream &O);
97 void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O);
98 void printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O);
99 void printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O);
100 void printSHFMask(const MCInst *MI, int opNum, raw_ostream &O);
102 bool printAlias(const char *Str, const MCInst &MI, unsigned OpNo,
104 bool printAlias(const char *Str, const MCInst &MI, unsigned OpNo0,
106 bool printAlias(const MCInst &MI, raw_ostream &OS);
107 void printSaveRestore(const MCInst *MI, raw_ostream &O);
108 void printRegisterList(const MCInst *MI, int opNum, raw_ostream &O);
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp 60 static void LowerLargeShift(MCInst& Inst) {
92 void MipsMCCodeEmitter::LowerCompactBranch(MCInst& Inst) const {
153 encodeInstruction(const MCInst &MI, raw_ostream &OS,
161 MCInst TmpInst = MI;
236 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
258 getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo,
280 getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo,
303 getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo,
326 getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
347 getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
368 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
390 getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
412 getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo,
434 getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
456 const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
478 getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
499 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
516 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
533 getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
551 getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
564 getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
577 getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
745 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
766 unsigned MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
781 getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
795 getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
809 getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
823 getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
838 getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,
853 getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
866 getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo,
879 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
902 getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo,
915 getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
943 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
956 MipsMCCodeEmitter::getUImmWithOffsetEncoding(const MCInst &MI, unsigned OpNo,
966 MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
988 MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
1010 MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
1019 MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo,
1047 MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
1067 MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
1074 MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
1108 MipsMCCodeEmitter::getMovePRegSingleOpValue(const MCInst &MI, unsigned OpNo,
1131 MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h 50 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
56 uint64_t getBinaryCodeForInstr(const MCInst &MI,
63 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
70 unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
76 unsigned getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
80 unsigned getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
84 unsigned getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
90 unsigned getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
97 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
104 unsigned getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo,
111 unsigned getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo,
118 unsigned getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo,
125 unsigned getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
132 unsigned getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
139 unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
146 unsigned getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
153 unsigned getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo,
160 unsigned getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
167 unsigned getBranchTarget26OpValueMM(const MCInst &MI, unsigned OpNo,
174 unsigned getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
180 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
184 unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
189 unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
192 unsigned getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
195 unsigned getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
198 unsigned getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
201 unsigned getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
204 unsigned getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,
207 unsigned getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
210 unsigned getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo,
213 unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
216 unsigned getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo,
219 unsigned getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
222 unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
228 unsigned getUImmWithOffsetEncoding(const MCInst &MI, unsigned OpNo,
232 unsigned getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
236 unsigned getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
240 unsigned getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
243 unsigned getUImm4AndValue(const MCInst &MI, unsigned OpNo,
247 unsigned getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
250 unsigned getMovePRegSingleOpValue(const MCInst &MI, unsigned OpNo,
254 unsigned getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
261 unsigned getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
265 unsigned getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
270 void LowerCompactBranch(MCInst& Inst) const;
lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp 140 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp 58 bool isIndirectJump(const MCInst &MI) {
68 bool isStackPointerFirstOperand(const MCInst &MI) {
73 bool isCall(const MCInst &MI, bool *IsIndirectCall) {
103 MCInst MaskInst;
113 void sandboxIndirectJump(const MCInst &MI, const MCSubtargetInfo &STI) {
124 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx,
146 void EmitInstruction(const MCInst &Inst,
lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp 173 MCInst TmpInst;
182 MCInst TmpInst;
202 MCInst TmpInst;
213 MCInst TmpInst;
231 MCInst TmpInst;
251 MCInst TmpInst;
1168 MCInst TmpInst;
1240 MCInst Inst;
1294 MCInst Inst;
lib/Target/Mips/MipsAsmPrinter.cpp 119 MCInst TmpInst0;
281 MCInst TmpInst0;
853 MCInst I;
862 MCInst I;
871 MCInst I;
891 MCInst I;
lib/Target/Mips/MipsMCInstLower.cpp 217 lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const {
255 MCInst &OutMI, int Opcode) const {
297 MCInst &OutMI) const {
317 void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
lib/Target/Mips/MipsMCInstLower.h 37 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
45 void lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const;
46 void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI,
48 bool lowerLongBranch(const MachineInstr *MI, MCInst &OutMI) const;
lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp 75 void NVPTXInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
83 void NVPTXInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
97 void NVPTXInstPrinter::printCvtMode(const MCInst *MI, int OpNum, raw_ostream &O,
147 void NVPTXInstPrinter::printCmpMode(const MCInst *MI, int OpNum, raw_ostream &O,
220 void NVPTXInstPrinter::printLdStCode(const MCInst *MI, int OpNum,
272 void NVPTXInstPrinter::printMmaCode(const MCInst *MI, int OpNum, raw_ostream &O,
286 void NVPTXInstPrinter::printMemOperand(const MCInst *MI, int OpNum,
302 void NVPTXInstPrinter::printProtoIdent(const MCInst *MI, int OpNum,
lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h 28 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
32 void printInstruction(const MCInst *MI, raw_ostream &O);
36 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
37 void printCvtMode(const MCInst *MI, int OpNum, raw_ostream &O,
39 void printCmpMode(const MCInst *MI, int OpNum, raw_ostream &O,
41 void printLdStCode(const MCInst *MI, int OpNum,
43 void printMmaCode(const MCInst *MI, int OpNum, raw_ostream &O,
45 void printMemOperand(const MCInst *MI, int OpNum,
47 void printProtoIdent(const MCInst *MI, int OpNum,
lib/Target/NVPTX/NVPTXAsmPrinter.cpp 145 MCInst Inst;
212 void NVPTXAsmPrinter::lowerToMCInst(const MachineInstr *MI, MCInst &OutMI) {
lib/Target/NVPTX/NVPTXAsmPrinter.h 210 void lowerToMCInst(const MachineInstr *MI, MCInst &OutMI);
lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp 133 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
409 void addRegOperands(MCInst &Inst, unsigned N) const {
413 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
418 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
423 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
428 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
433 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
440 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
447 void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
452 void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
457 void addRegVFRCOperands(MCInst &Inst, unsigned N) const {
462 void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
467 void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
472 void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
477 void addRegVSSRCOperands(MCInst &Inst, unsigned N) const {
482 void addRegQFRCOperands(MCInst &Inst, unsigned N) const {
487 void addRegQSRCOperands(MCInst &Inst, unsigned N) const {
492 void addRegQBRCOperands(MCInst &Inst, unsigned N) const {
497 void addRegSPE4RCOperands(MCInst &Inst, unsigned N) const {
502 void addRegSPERCOperands(MCInst &Inst, unsigned N) const {
507 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
512 void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
517 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
522 void addImmOperands(MCInst &Inst, unsigned N) const {
530 void addS16ImmOperands(MCInst &Inst, unsigned N) const {
545 void addU16ImmOperands(MCInst &Inst, unsigned N) const {
560 void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
568 void addTLSRegOperands(MCInst &Inst, unsigned N) const {
690 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
712 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
720 MCInst TmpInst;
732 MCInst TmpInst;
742 MCInst TmpInst;
759 MCInst TmpInst;
768 MCInst TmpInst;
777 MCInst TmpInst;
786 MCInst TmpInst;
795 MCInst TmpInst;
804 MCInst TmpInst;
814 MCInst TmpInst;
828 MCInst TmpInst;
842 MCInst TmpInst;
857 MCInst TmpInst;
872 MCInst TmpInst;
885 MCInst TmpInst;
898 MCInst TmpInst;
911 MCInst TmpInst;
924 MCInst TmpInst;
938 MCInst TmpInst;
951 MCInst TmpInst;
964 MCInst TmpInst;
978 MCInst TmpInst;
990 MCInst TmpInst;
1001 MCInst TmpInst;
1011 MCInst TmpInst;
1023 MCInst TmpInst;
1035 MCInst TmpInst;
1053 MCInst TmpInst;
1070 MCInst TmpInst;
1088 MCInst TmpInst;
1107 MCInst TmpInst;
1118 MCInst TmpInst;
1138 MCInst Inst;
lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp 35 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
64 static DecodeStatus DecodePCRel24BranchTarget(MCInst &Inst, unsigned Imm,
76 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
83 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
89 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo,
95 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
101 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
107 static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
113 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
119 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
125 static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
131 static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
137 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
143 static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo,
149 static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
155 static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo,
164 static DecodeStatus DecodeQFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
170 static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo,
180 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
188 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
195 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm,
230 static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm,
251 static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm,
266 static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm,
281 static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm,
296 static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm,
311 static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm,
324 DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp 167 bool mayNeedRelaxation(const MCInst &Inst,
181 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
182 MCInst &Res) const override {
lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp 67 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
201 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
298 void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo,
307 void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
314 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
321 void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,
328 void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
335 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
342 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
349 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
356 void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,
366 void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
372 void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
379 void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
386 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
394 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
402 void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
416 void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
425 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
443 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
454 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
467 void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
538 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h 35 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
39 void printInstruction(const MCInst *MI, raw_ostream &O);
42 bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
43 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
47 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
48 void printPredicateOperand(const MCInst *MI, unsigned OpNo,
50 void printATBitsAsHint(const MCInst *MI, unsigned OpNo, raw_ostream &O);
52 void printU1ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
53 void printU2ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
54 void printU3ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
55 void printU4ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
56 void printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
57 void printU5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
58 void printU6ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
59 void printU7ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
60 void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
61 void printU10ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
62 void printU12ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
63 void printS16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
64 void printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
65 void printBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
66 void printAbsBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
67 void printTLSCall(const MCInst *MI, unsigned OpNo, raw_ostream &O);
69 void printcrbitm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
71 void printMemRegImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
72 void printMemRegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp 43 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
55 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
68 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
81 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
93 unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
105 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
123 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
141 unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
162 unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
177 unsigned PPCMCCodeEmitter::getSPE4DisEncoding(const MCInst &MI, unsigned OpNo,
192 unsigned PPCMCCodeEmitter::getSPE2DisEncoding(const MCInst &MI, unsigned OpNo,
207 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
223 unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
236 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
250 static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO) {
261 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
283 const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
313 unsigned PPCMCCodeEmitter::getInstSizeInBytes(const MCInst &MI) const {
lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h 38 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
41 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
44 unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
47 unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
50 unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo,
53 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
56 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
59 unsigned getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
62 unsigned getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
65 unsigned getSPE4DisEncoding(const MCInst &MI, unsigned OpNo,
68 unsigned getSPE2DisEncoding(const MCInst &MI, unsigned OpNo,
71 unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
74 unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
77 unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
83 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
89 uint64_t getBinaryCodeForInstr(const MCInst &MI,
93 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
98 unsigned getInstSizeInBytes(const MCInst &MI) const;
103 verifyInstructionPredicates(const MCInst &MI,
lib/Target/PowerPC/PPC.h 52 void LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
lib/Target/PowerPC/PPCAsmPrinter.cpp 537 MCInst TmpInst;
1226 MCInst RetInst;
lib/Target/PowerPC/PPCInstrInfo.cpp 488 void PPCInstrInfo::getNoop(MCInst &NopInst) const {
lib/Target/PowerPC/PPCInstrInfo.h 380 void getNoop(MCInst &NopInst) const override;
lib/Target/PowerPC/PPCMCInstLower.cpp 150 void llvm::LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 79 void emitToStreamer(MCStreamer &S, const MCInst &Inst);
92 void emitLoadLocalAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
95 void emitLoadAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
99 void emitLoadTLSIEAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
103 void emitLoadTLSGDAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
106 void emitLoadStoreSymbol(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
113 bool checkPseudoAddTPRel(MCInst &Inst, OperandVector &Operands);
119 bool processInstruction(MCInst &Inst, SMLoc IDLoc, OperandVector &Operands,
675 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
688 void addRegOperands(MCInst &Inst, unsigned N) const {
693 void addImmOperands(MCInst &Inst, unsigned N) const {
698 void addFenceArgOperands(MCInst &Inst, unsigned N) const {
717 void addCSRSystemRegisterOperands(MCInst &Inst, unsigned N) const {
733 void addFRMArgOperands(MCInst &Inst, unsigned N) const {
783 MCInst Inst;
1587 void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
1588 MCInst CInst;
1643 void RISCVAsmParser::emitLoadLocalAddress(MCInst &Inst, SMLoc IDLoc,
1657 void RISCVAsmParser::emitLoadAddress(MCInst &Inst, SMLoc IDLoc,
1683 void RISCVAsmParser::emitLoadTLSIEAddress(MCInst &Inst, SMLoc IDLoc,
1698 void RISCVAsmParser::emitLoadTLSGDAddress(MCInst &Inst, SMLoc IDLoc,
1712 void RISCVAsmParser::emitLoadStoreSymbol(MCInst &Inst, unsigned Opcode,
1731 bool RISCVAsmParser::checkPseudoAddTPRel(MCInst &Inst,
1744 bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp 39 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
60 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
77 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo,
88 static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo,
99 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo,
110 static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo,
121 static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint64_t RegNo,
131 static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo,
141 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
154 static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) {
171 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
180 static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint64_t Imm,
189 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
199 static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint64_t Imm,
208 static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint64_t Imm,
219 static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint64_t Imm,
230 static DecodeStatus decodeFRMArg(MCInst &Inst, uint64_t Imm,
241 static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
244 static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
247 static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
251 static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn,
254 static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn,
260 static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
270 static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
282 static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
295 static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn,
304 static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn,
315 DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp 107 void RISCVAsmBackend::relaxInstruction(const MCInst &Inst,
109 MCInst &Res) const {
159 bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst,
lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h 134 bool mayNeedRelaxation(const MCInst &Inst,
138 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
139 MCInst &Res) const override;
lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp 66 void RISCVInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
69 const MCInst *NewMI = MI;
70 MCInst UncompressedMI;
84 void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
104 void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
115 void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
133 void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo,
140 void RISCVInstPrinter::printAtomicMemOp(const MCInst *MI, unsigned OpNo,
lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h 30 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
34 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
36 void printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
38 void printFenceArg(const MCInst *MI, unsigned OpNo,
40 void printFRMArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
42 void printAtomicMemOp(const MCInst *MI, unsigned OpNo,
46 void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
48 bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
50 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp 52 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
56 void expandFunctionCall(const MCInst &MI, raw_ostream &OS,
60 void expandAddTPRel(const MCInst &MI, raw_ostream &OS,
66 uint64_t getBinaryCodeForInstr(const MCInst &MI,
72 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
76 unsigned getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
80 unsigned getImmOpValue(const MCInst &MI, unsigned OpNo,
99 void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS,
102 MCInst TmpInst;
139 void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI, raw_ostream &OS,
168 MCInst TmpInst = MCInstBuilder(RISCV::ADD)
176 void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
216 RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
231 RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
245 unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
lib/Target/RISCV/RISCV.h 33 void LowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
lib/Target/RISCV/RISCVAsmPrinter.cpp 50 void EmitToStreamer(MCStreamer &S, const MCInst &Inst);
63 void RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) {
64 MCInst CInst;
79 MCInst TmpInst;
lib/Target/RISCV/RISCVMCInstLower.cpp 128 void llvm::LowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
lib/Target/Sparc/AsmParser/SparcAsmParser.cpp 105 bool expandSET(MCInst &Inst, SMLoc IDLoc,
106 SmallVectorImpl<MCInst> &Instructions);
333 void addRegOperands(MCInst &Inst, unsigned N) const {
338 void addImmOperands(MCInst &Inst, unsigned N) const {
344 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
354 void addMEMrrOperands(MCInst &Inst, unsigned N) const {
363 void addMEMriOperands(MCInst &Inst, unsigned N) const {
372 void addMembarTagOperands(MCInst &Inst, unsigned N) const {
506 bool SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc,
507 SmallVectorImpl<MCInst> &Instructions) {
543 MCInst TmpInst;
564 MCInst TmpInst;
585 MCInst Inst;
586 SmallVector<MCInst, 8> Instructions;
602 for (const MCInst &I : Instructions) {
lib/Target/Sparc/Disassembler/SparcDisassembler.cpp 37 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
146 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst,
157 static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst,
169 static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst,
181 static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst,
193 static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst,
207 static DecodeStatus DecodeCPRegsRegisterClass(MCInst &Inst,
218 static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
227 static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
236 static DecodeStatus DecodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
245 static DecodeStatus DecodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo,
260 static DecodeStatus DecodeCPPairRegisterClass(MCInst &Inst, unsigned RegNo,
270 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
272 static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address,
274 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
276 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
278 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
280 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,
282 static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address,
284 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
286 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn,
288 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn,
290 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
292 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
294 static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn,
296 static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn,
298 static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn,
300 static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn,
302 static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address,
304 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
306 static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address,
308 static DecodeStatus DecodeTRAP(MCInst &Inst, unsigned insn, uint64_t Address,
332 DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
369 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
372 static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address,
419 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
425 static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address,
431 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
437 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
443 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
449 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,
455 static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address,
461 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
467 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn,
473 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address,
479 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
485 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
491 static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn,
497 static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn,
505 uint64_t Width, MCInst &MI,
512 static DecodeStatus DecodeCall(MCInst &MI, unsigned insn,
522 static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn,
529 static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address,
563 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
591 static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address,
631 static DecodeStatus DecodeTRAP(MCInst &MI, unsigned insn, uint64_t Address,
lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp 257 bool mayNeedRelaxation(const MCInst &Inst,
273 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
274 MCInst &Res) const override {
lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp 46 void SparcInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
53 bool SparcInstPrinter::printSparcAliasInstr(const MCInst *MI,
107 void SparcInstPrinter::printOperand(const MCInst *MI, int opNum,
139 void SparcInstPrinter::printMemOperand(const MCInst *MI, int opNum,
162 void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum,
191 bool SparcInstPrinter::printGetPCX(const MCInst *MI, unsigned opNum,
198 void SparcInstPrinter::printMembarTag(const MCInst *MI, int opNum,
lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h 27 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
29 bool printSparcAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
34 void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
36 bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
38 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
43 void printOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
45 void printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
47 void printCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
49 bool printGetPCX(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
51 void printMembarTag(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp 56 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
62 uint64_t getBinaryCodeForInstr(const MCInst &MI,
68 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
72 unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
75 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
78 unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
81 unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
88 verifyInstructionPredicates(const MCInst &MI,
94 void SparcMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
124 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
150 getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
185 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
198 getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
211 getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
lib/Target/Sparc/Sparc.h 33 MCInst &OutMI,
lib/Target/Sparc/SparcAsmPrinter.cpp 108 MCInst CallInst;
118 MCInst SETHIInst;
129 MCInst Inst;
267 MCInst TmpInst;
lib/Target/Sparc/SparcMCInstLower.cpp 94 MCInst &OutMI,
lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp 141 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
295 void addRegOperands(MCInst &Inst, unsigned N) const {
299 void addImmOperands(MCInst &Inst, unsigned N) const {
303 void addBDAddrOperands(MCInst &Inst, unsigned N) const {
309 void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
316 void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
323 void addBDRAddrOperands(MCInst &Inst, unsigned N) const {
330 void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
337 void addImmTLSOperands(MCInst &Inst, unsigned N) const {
1095 MCInst Inst = MCInstBuilder(Entry->Opcode);
1246 MCInst Inst;
lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp 35 DecodeStatus getInstruction(MCInst &instr, uint64_t &Size,
76 uint64_t Width, MCInst &MI,
83 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
93 static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
99 static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
105 static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
111 static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
117 static DecodeStatus DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
123 static DecodeStatus DecodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
129 static DecodeStatus DecodeFP64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
135 static DecodeStatus DecodeFP128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
141 static DecodeStatus DecodeVR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
147 static DecodeStatus DecodeVR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
153 static DecodeStatus DecodeVR128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
159 static DecodeStatus DecodeAR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
165 static DecodeStatus DecodeCR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
172 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) {
180 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) {
187 static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm,
192 static DecodeStatus decodeU2ImmOperand(MCInst &Inst, uint64_t Imm,
197 static DecodeStatus decodeU3ImmOperand(MCInst &Inst, uint64_t Imm,
202 static DecodeStatus decodeU4ImmOperand(MCInst &Inst, uint64_t Imm,
207 static DecodeStatus decodeU6ImmOperand(MCInst &Inst, uint64_t Imm,
212 static DecodeStatus decodeU8ImmOperand(MCInst &Inst, uint64_t Imm,
217 static DecodeStatus decodeU12ImmOperand(MCInst &Inst, uint64_t Imm,
222 static DecodeStatus decodeU16ImmOperand(MCInst &Inst, uint64_t Imm,
227 static DecodeStatus decodeU32ImmOperand(MCInst &Inst, uint64_t Imm,
232 static DecodeStatus decodeS8ImmOperand(MCInst &Inst, uint64_t Imm,
237 static DecodeStatus decodeS16ImmOperand(MCInst &Inst, uint64_t Imm,
242 static DecodeStatus decodeS32ImmOperand(MCInst &Inst, uint64_t Imm,
248 static DecodeStatus decodePCDBLOperand(MCInst &Inst, uint64_t Imm,
262 static DecodeStatus decodePC12DBLBranchOperand(MCInst &Inst, uint64_t Imm,
268 static DecodeStatus decodePC16DBLBranchOperand(MCInst &Inst, uint64_t Imm,
274 static DecodeStatus decodePC24DBLBranchOperand(MCInst &Inst, uint64_t Imm,
280 static DecodeStatus decodePC32DBLBranchOperand(MCInst &Inst, uint64_t Imm,
286 static DecodeStatus decodePC32DBLOperand(MCInst &Inst, uint64_t Imm,
292 static DecodeStatus decodeBDAddr12Operand(MCInst &Inst, uint64_t Field,
302 static DecodeStatus decodeBDAddr20Operand(MCInst &Inst, uint64_t Field,
312 static DecodeStatus decodeBDXAddr12Operand(MCInst &Inst, uint64_t Field,
324 static DecodeStatus decodeBDXAddr20Operand(MCInst &Inst, uint64_t Field,
336 static DecodeStatus decodeBDLAddr12Len4Operand(MCInst &Inst, uint64_t Field,
348 static DecodeStatus decodeBDLAddr12Len8Operand(MCInst &Inst, uint64_t Field,
360 static DecodeStatus decodeBDRAddr12Operand(MCInst &Inst, uint64_t Field,
372 static DecodeStatus decodeBDVAddr12Operand(MCInst &Inst, uint64_t Field,
384 static DecodeStatus decodeBDAddr32Disp12Operand(MCInst &Inst, uint64_t Field,
390 static DecodeStatus decodeBDAddr32Disp20Operand(MCInst &Inst, uint64_t Field,
396 static DecodeStatus decodeBDAddr64Disp12Operand(MCInst &Inst, uint64_t Field,
402 static DecodeStatus decodeBDAddr64Disp20Operand(MCInst &Inst, uint64_t Field,
408 static DecodeStatus decodeBDXAddr64Disp12Operand(MCInst &Inst, uint64_t Field,
414 static DecodeStatus decodeBDXAddr64Disp20Operand(MCInst &Inst, uint64_t Field,
420 static DecodeStatus decodeBDLAddr64Disp12Len4Operand(MCInst &Inst,
427 static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst &Inst,
434 static DecodeStatus decodeBDRAddr64Disp12Operand(MCInst &Inst,
441 static DecodeStatus decodeBDVAddr64Disp12Operand(MCInst &Inst, uint64_t Field,
449 DecodeStatus SystemZDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp 54 void SystemZInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
66 static void printUImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) {
73 static void printSImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) {
79 void SystemZInstPrinter::printU1ImmOperand(const MCInst *MI, int OpNum,
84 void SystemZInstPrinter::printU2ImmOperand(const MCInst *MI, int OpNum,
89 void SystemZInstPrinter::printU3ImmOperand(const MCInst *MI, int OpNum,
94 void SystemZInstPrinter::printU4ImmOperand(const MCInst *MI, int OpNum,
99 void SystemZInstPrinter::printU6ImmOperand(const MCInst *MI, int OpNum,
104 void SystemZInstPrinter::printS8ImmOperand(const MCInst *MI, int OpNum,
109 void SystemZInstPrinter::printU8ImmOperand(const MCInst *MI, int OpNum,
114 void SystemZInstPrinter::printU12ImmOperand(const MCInst *MI, int OpNum,
119 void SystemZInstPrinter::printS16ImmOperand(const MCInst *MI, int OpNum,
124 void SystemZInstPrinter::printU16ImmOperand(const MCInst *MI, int OpNum,
129 void SystemZInstPrinter::printS32ImmOperand(const MCInst *MI, int OpNum,
134 void SystemZInstPrinter::printU32ImmOperand(const MCInst *MI, int OpNum,
139 void SystemZInstPrinter::printU48ImmOperand(const MCInst *MI, int OpNum,
144 void SystemZInstPrinter::printPCRelOperand(const MCInst *MI, int OpNum,
154 void SystemZInstPrinter::printPCRelTLSOperand(const MCInst *MI, int OpNum,
177 void SystemZInstPrinter::printOperand(const MCInst *MI, int OpNum,
182 void SystemZInstPrinter::printBDAddrOperand(const MCInst *MI, int OpNum,
188 void SystemZInstPrinter::printBDXAddrOperand(const MCInst *MI, int OpNum,
195 void SystemZInstPrinter::printBDLAddrOperand(const MCInst *MI, int OpNum,
206 void SystemZInstPrinter::printBDRAddrOperand(const MCInst *MI, int OpNum,
217 void SystemZInstPrinter::printBDVAddrOperand(const MCInst *MI, int OpNum,
224 void SystemZInstPrinter::printCond4Operand(const MCInst *MI, int OpNum,
lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.h 30 void printInstruction(const MCInst *MI, raw_ostream &O);
43 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
48 void printOperand(const MCInst *MI, int OpNum, raw_ostream &O);
49 void printBDAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O);
50 void printBDXAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O);
51 void printBDLAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O);
52 void printBDRAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O);
53 void printBDVAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O);
54 void printU1ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
55 void printU2ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
56 void printU3ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
57 void printU4ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
58 void printU6ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
59 void printS8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
60 void printU8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
61 void printU12ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
62 void printS16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
63 void printU16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
64 void printS32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
65 void printU32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
66 void printU48ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
67 void printPCRelOperand(const MCInst *MI, int OpNum, raw_ostream &O);
68 void printPCRelTLSOperand(const MCInst *MI, int OpNum, raw_ostream &O);
72 void printCond4Operand(const MCInst *MI, int OpNum, raw_ostream &O);
lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp 57 bool mayNeedRelaxation(const MCInst &Inst,
66 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
67 MCInst &Res) const override {
lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp 47 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
53 uint64_t getBinaryCodeForInstr(const MCInst &MI,
59 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
67 uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
70 uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
73 uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
76 uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
79 uint64_t getBDLAddr12Len4Encoding(const MCInst &MI, unsigned OpNum,
82 uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum,
85 uint64_t getBDRAddr12Encoding(const MCInst &MI, unsigned OpNum,
88 uint64_t getBDVAddr12Encoding(const MCInst &MI, unsigned OpNum,
97 uint64_t getPCRelEncoding(const MCInst &MI, unsigned OpNum,
102 uint64_t getPC16DBLEncoding(const MCInst &MI, unsigned OpNum,
108 uint64_t getPC32DBLEncoding(const MCInst &MI, unsigned OpNum,
114 uint64_t getPC16DBLTLSEncoding(const MCInst &MI, unsigned OpNum,
120 uint64_t getPC32DBLTLSEncoding(const MCInst &MI, unsigned OpNum,
126 uint64_t getPC12DBLBPPEncoding(const MCInst &MI, unsigned OpNum,
132 uint64_t getPC16DBLBPPEncoding(const MCInst &MI, unsigned OpNum,
138 uint64_t getPC24DBLBPPEncoding(const MCInst &MI, unsigned OpNum,
148 verifyInstructionPredicates(const MCInst &MI,
155 encodeInstruction(const MCInst &MI, raw_ostream &OS,
172 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
183 getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
193 getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
203 getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
214 getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
226 getBDLAddr12Len4Encoding(const MCInst &MI, unsigned OpNum,
237 getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum,
248 getBDRAddr12Encoding(const MCInst &MI, unsigned OpNum,
259 getBDVAddr12Encoding(const MCInst &MI, unsigned OpNum,
270 SystemZMCCodeEmitter::getPCRelEncoding(const MCInst &MI, unsigned OpNum,
lib/Target/SystemZ/SystemZAsmPrinter.cpp 31 static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode) {
45 static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode) {
59 static MCInst lowerRIEfLow(const MachineInstr *MI, unsigned Opcode) {
87 static void lowerAlignmentHint(const MachineInstr *MI, MCInst &LoweredMI,
106 static MCInst lowerSubvectorLoad(const MachineInstr *MI, unsigned Opcode) {
116 static MCInst lowerSubvectorStore(const MachineInstr *MI, unsigned Opcode) {
127 MCInst LoweredMI;
lib/Target/SystemZ/SystemZMCInstLower.cpp 94 void SystemZMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
lib/Target/SystemZ/SystemZMCInstLower.h 32 void lower(const MachineInstr *MI, MCInst &OutMI) const;
lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp 111 void addRegOperands(MCInst &, unsigned) const {
116 void addImmOperands(MCInst &Inst, unsigned N) const {
126 void addFPImmOperands(MCInst &Inst, unsigned N) const {
134 void addBrListOperands(MCInst &Inst, unsigned N) const {
787 MCInst Inst;
lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp 46 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
100 static bool parseLEBImmediate(MCInst &MI, uint64_t &Size,
110 bool parseImmediate(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes) {
160 MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t /*Address*/,
lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp 62 bool mayNeedRelaxation(const MCInst &Inst,
67 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
68 MCInst &Res) const override {}
lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp 47 void WebAssemblyInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
208 void WebAssemblyInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
252 void WebAssemblyInstPrinter::printBrList(const MCInst *MI, unsigned OpNo,
263 void WebAssemblyInstPrinter::printWebAssemblyP2AlignOperand(const MCInst *MI,
272 void WebAssemblyInstPrinter::printWebAssemblySignatureOperand(const MCInst *MI,
lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h 40 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
44 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
45 void printBrList(const MCInst *MI, unsigned OpNo, raw_ostream &O);
46 void printWebAssemblyP2AlignOperand(const MCInst *MI, unsigned OpNo,
48 void printWebAssemblySignatureOperand(const MCInst *MI, unsigned OpNo,
52 void printInstruction(const MCInst *MI, raw_ostream &O);
lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp 42 uint64_t getBinaryCodeForInstr(const MCInst &MI,
46 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
60 const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp 358 MCInst TmpInst;
lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp 45 static void removeRegisterOperands(const MachineInstr *MI, MCInst &OutMI);
207 MCInst &OutMI) const {
311 static void removeRegisterOperands(const MachineInstr *MI, MCInst &OutMI) {
lib/Target/WebAssembly/WebAssemblyMCInstLower.h 43 void lower(const MachineInstr *MI, MCInst &OutMI) const;
lib/Target/X86/AsmParser/X86AsmParser.cpp 99 unsigned MatchInstruction(const OperandVector &Operands, MCInst &Inst,
881 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
883 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
884 bool processInstruction(MCInst &Inst, const OperandVector &Ops);
888 void EmitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out);
2873 bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
2939 bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) {
3040 void X86AsmParser::EmitInstruction(MCInst &Inst, OperandVector &Operands,
3073 MCInst Inst;
3106 unsigned X86AsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3154 MCInst Inst;
3361 MCInst Inst;
lib/Target/X86/AsmParser/X86Operand.h 488 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
496 void addRegOperands(MCInst &Inst, unsigned N) const {
501 void addGR32orGR64Operands(MCInst &Inst, unsigned N) const {
509 void addAVX512RCOperands(MCInst &Inst, unsigned N) const {
514 void addImmOperands(MCInst &Inst, unsigned N) const {
519 void addMaskPairOperands(MCInst &Inst, unsigned N) const {
543 void addMemOperands(MCInst &Inst, unsigned N) const {
552 void addAbsMemOperands(MCInst &Inst, unsigned N) const {
561 void addSrcIdxOperands(MCInst &Inst, unsigned N) const {
567 void addDstIdxOperands(MCInst &Inst, unsigned N) const {
572 void addMemOffsOperands(MCInst &Inst, unsigned N) const {
lib/Target/X86/Disassembler/X86Disassembler.cpp 126 static bool translateInstruction(MCInst &target,
141 DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
215 MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address,
268 static void translateRegister(MCInst &mcInst, Reg reg) {
298 uint64_t Width, MCInst &MI,
331 static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) {
356 static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) {
378 static void translateImmediate(MCInst &mcInst, uint64_t immediate,
484 static bool translateRMRegister(MCInst &mcInst,
522 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,
682 static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
716 static void translateFPRegister(MCInst &mcInst,
727 static bool translateMaskRegister(MCInst &mcInst,
745 static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
807 static bool translateInstruction(MCInst &mcInst,
lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp 41 void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
78 bool X86ATTInstPrinter::printVecCompareInstr(const MCInst *MI,
352 void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
385 void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
425 void X86ATTInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
439 void X86ATTInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
450 void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
469 void X86ATTInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
478 void X86ATTInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,
lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h 27 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
29 bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS);
33 bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
34 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
38 void printInstruction(const MCInst *MI, raw_ostream &OS);
41 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS) override;
42 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS);
43 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
44 void printSrcIdx(const MCInst *MI, unsigned Op, raw_ostream &O);
45 void printDstIdx(const MCInst *MI, unsigned Op, raw_ostream &O);
46 void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &OS);
47 void printSTiRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
49 void printanymem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
52 void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
56 void printbytemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
59 void printwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
62 void printdwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
65 void printqwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
68 void printxmmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
71 void printymmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
74 void printzmmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
77 void printtbytemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
81 void printSrcIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
84 void printSrcIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
87 void printSrcIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
90 void printSrcIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
93 void printDstIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
96 void printDstIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
99 void printDstIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
102 void printDstIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
105 void printMemOffs8(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
108 void printMemOffs16(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
111 void printMemOffs32(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
114 void printMemOffs64(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp 128 bool mayNeedRelaxation(const MCInst &Inst,
135 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
136 MCInst &Res) const override;
142 static unsigned getRelaxedOpcodeBranch(const MCInst &Inst, bool is16BitMode) {
154 static unsigned getRelaxedOpcodeArith(const MCInst &Inst) {
239 static unsigned getRelaxedOpcode(const MCInst &Inst, bool is16BitMode) {
265 bool X86AsmBackend::mayNeedRelaxation(const MCInst &Inst,
295 void X86AsmBackend::relaxInstruction(const MCInst &Inst,
297 MCInst &Res) const {
lib/Target/X86/MCTargetDesc/X86InstComments.cpp 215 static unsigned getRegOperandNumElts(const MCInst *MI, unsigned ScalarSize,
226 static void printMasking(raw_ostream &OS, const MCInst *MI,
250 static bool printFMA3Comments(const MCInst *MI, raw_ostream &OS) {
499 bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
lib/Target/X86/MCTargetDesc/X86InstComments.h 22 bool EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp 27 void X86InstPrinterCommon::printCondCode(const MCInst *MI, unsigned Op,
51 void X86InstPrinterCommon::printSSEAVXCC(const MCInst *MI, unsigned Op,
91 void X86InstPrinterCommon::printVPCOMMnemonic(const MCInst *MI,
121 void X86InstPrinterCommon::printVPCMPMnemonic(const MCInst *MI,
208 void X86InstPrinterCommon::printCMPMnemonic(const MCInst *MI, bool IsVCmp,
269 void X86InstPrinterCommon::printRoundingControl(const MCInst *MI, unsigned Op,
294 void X86InstPrinterCommon::printPCRelImm(const MCInst *MI, unsigned OpNo,
314 void X86InstPrinterCommon::printOptionalSegReg(const MCInst *MI, unsigned OpNo,
322 void X86InstPrinterCommon::printInstFlags(const MCInst *MI, raw_ostream &O) {
339 void X86InstPrinterCommon::printVKPair(const MCInst *MI, unsigned OpNo,
lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.h 25 virtual void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) = 0;
26 void printCondCode(const MCInst *MI, unsigned Op, raw_ostream &OS);
27 void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS);
28 void printVPCOMMnemonic(const MCInst *MI, raw_ostream &OS);
29 void printVPCMPMnemonic(const MCInst *MI, raw_ostream &OS);
30 void printCMPMnemonic(const MCInst *MI, bool IsVCmp, raw_ostream &OS);
31 void printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &O);
32 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
34 void printInstFlags(const MCInst *MI, raw_ostream &O);
35 void printOptionalSegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
36 void printVKPair(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp 39 void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
60 bool X86IntelInstPrinter::printVecCompareInstr(const MCInst *MI, raw_ostream &OS) {
330 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
344 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
392 void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
401 void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
409 void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
428 void X86IntelInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
436 void X86IntelInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,
lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.h 28 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
30 bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS);
34 bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
35 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
39 void printInstruction(const MCInst *MI, raw_ostream &O);
42 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) override;
43 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O);
44 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
45 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
46 void printDstIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
47 void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &O);
48 void printSTiRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
50 void printanymem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
54 void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
58 void printbytemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
62 void printwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
66 void printdwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
70 void printqwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
74 void printxmmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
78 void printymmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
82 void printzmmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
86 void printtbytemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
92 void printSrcIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
96 void printSrcIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
100 void printSrcIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
104 void printSrcIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
108 void printDstIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
112 void printDstIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
116 void printDstIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
120 void printDstIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
124 void printMemOffs8(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
128 void printMemOffs16(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
132 void printMemOffs32(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
136 void printMemOffs64(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp 65 bool Is16BitMemOperand(const MCInst &MI, unsigned Op,
86 unsigned getX86RegEncoding(const MCInst &MI, unsigned OpNum) const {
92 bool isREXExtendedReg(const MCInst &MI, unsigned OpNum) const {
132 void emitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField,
137 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
142 const MCInst &MI, const MCInstrDesc &Desc,
146 const MCInst &MI, raw_ostream &OS) const;
149 const MCInst &MI, const MCInstrDesc &Desc,
152 uint8_t DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
155 bool isPCRel32Branch(const MCInst &MI) const;
208 static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) {
229 static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) {
282 bool X86MCCodeEmitter::isPCRel32Branch(const MCInst &MI) const {
376 void X86MCCodeEmitter::emitMemModRMByte(const MCInst &MI, unsigned Op,
644 int MemOperand, const MCInst &MI,
1049 uint8_t X86MCCodeEmitter::DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
1127 const MCInst &MI,
1149 int MemOperand, const MCInst &MI,
1212 encodeInstruction(const MCInst &MI, raw_ostream &OS,
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp 73 bool X86_MC::hasLockPrefix(const MCInst &MI) {
401 bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst,
407 Optional<uint64_t> evaluateMemoryOperandAddress(const MCInst &Inst,
416 const MCInst &Inst,
526 const MCInst &Inst, uint64_t Addr, uint64_t Size) const {
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h 63 bool hasLockPrefix(const MCInst &MI);
lib/Target/X86/X86AsmPrinter.h 49 void count(MCInst &Inst, const MCSubtargetInfo &STI,
82 void EmitAndCountInstruction(MCInst &Inst);
lib/Target/X86/X86InstrInfo.cpp 6911 void X86InstrInfo::getNoop(MCInst &NopInst) const {
lib/Target/X86/X86InstrInfo.h 396 void getNoop(MCInst &NopInst) const override;
lib/Target/X86/X86MCInstLower.cpp 64 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
79 void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,
102 void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
292 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
315 static void SimplifyMOVSX(MCInst &Inst) {
342 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
465 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
1143 MCInst CallInst;
1169 MCInst MI;
1205 MCInst MCI;
1544 MCInst Ret;
1577 MCInst TC;
2488 MCInst TmpInst;
lib/Target/XCore/Disassembler/XCoreDisassembler.cpp 38 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
76 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
81 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
86 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
89 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
92 static DecodeStatus Decode2RInstruction(MCInst &Inst,
97 static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
102 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
107 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
112 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
117 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
122 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst,
127 static DecodeStatus DecodeL2RInstruction(MCInst &Inst,
132 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
137 static DecodeStatus Decode3RInstruction(MCInst &Inst,
142 static DecodeStatus Decode3RImmInstruction(MCInst &Inst,
147 static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
152 static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst,
157 static DecodeStatus DecodeL3RInstruction(MCInst &Inst,
162 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst,
167 static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst,
172 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst,
177 static DecodeStatus DecodeL6RInstruction(MCInst &Inst,
182 static DecodeStatus DecodeL5RInstruction(MCInst &Inst,
187 static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst,
192 static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst,
199 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
211 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
223 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
234 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
275 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
345 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
358 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
371 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
384 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
398 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
411 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
424 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
438 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
509 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
523 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
537 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
550 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
563 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
576 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
589 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
603 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
618 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
632 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
646 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
666 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
680 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
700 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
719 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
739 MCInst &instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address,
lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.cpp 33 void XCoreInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
40 printInlineJT(const MCInst *MI, int opNum, raw_ostream &O) {
45 printInlineJT32(const MCInst *MI, int opNum, raw_ostream &O) {
75 printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.h 30 void printInstruction(const MCInst *MI, raw_ostream &O);
34 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
38 void printInlineJT(const MCInst *MI, int opNum, raw_ostream &O);
39 void printInlineJT32(const MCInst *MI, int opNum, raw_ostream &O);
40 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
41 void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O);
lib/Target/XCore/XCoreAsmPrinter.cpp 288 MCInst TmpInst;
lib/Target/XCore/XCoreMCInstLower.cpp 103 void XCoreMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
lib/Target/XCore/XCoreMCInstLower.h 31 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
tools/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp 55 lldb::addr_t pc, llvm::MCInst &mc_inst) const;
56 void PrintMCInst(llvm::MCInst &mc_inst, std::string &inst_string,
59 bool CanBranch(llvm::MCInst &mc_inst) const;
60 bool HasDelaySlot(llvm::MCInst &mc_inst) const;
61 bool IsCall(llvm::MCInst &mc_inst) const;
108 llvm::MCInst inst;
141 llvm::MCInst inst;
242 llvm::MCInst inst;
311 llvm::MCInst inst;
881 llvm::MCInst inst;
1017 llvm::MCInst &mc_inst) const {
1031 llvm::MCInst &mc_inst, std::string &inst_string,
1067 llvm::MCInst &mc_inst) const {
1073 llvm::MCInst &mc_inst) const {
1077 bool DisassemblerLLVMC::MCDisasmInstance::IsCall(llvm::MCInst &mc_inst) const {
tools/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp 979 llvm::MCInst mc_insn;
1063 llvm::MCInst mc_insn;
1183 bool EmulateInstructionMIPS::Emulate_ADDiu(llvm::MCInst &insn) {
1235 bool EmulateInstructionMIPS::Emulate_SW(llvm::MCInst &insn) {
1299 bool EmulateInstructionMIPS::Emulate_LW(llvm::MCInst &insn) {
1346 bool EmulateInstructionMIPS::Emulate_SUBU_ADDU(llvm::MCInst &insn) {
1424 bool EmulateInstructionMIPS::Emulate_LUI(llvm::MCInst &insn) {
1441 bool EmulateInstructionMIPS::Emulate_ADDIUSP(llvm::MCInst &insn) {
1467 bool EmulateInstructionMIPS::Emulate_ADDIUS5(llvm::MCInst &insn) {
1500 bool EmulateInstructionMIPS::Emulate_SWSP(llvm::MCInst &insn) {
1565 bool EmulateInstructionMIPS::Emulate_SWM16_32(llvm::MCInst &insn) {
1642 bool EmulateInstructionMIPS::Emulate_LWSP(llvm::MCInst &insn) {
1693 bool EmulateInstructionMIPS::Emulate_LWM16_32(llvm::MCInst &insn) {
1750 bool EmulateInstructionMIPS::Emulate_JRADDIUSP(llvm::MCInst &insn) {
1802 bool EmulateInstructionMIPS::Emulate_BXX_3ops(llvm::MCInst &insn) {
1851 bool EmulateInstructionMIPS::Emulate_BXX_3ops_C(llvm::MCInst &insn) {
1930 bool EmulateInstructionMIPS::Emulate_Bcond_Link_C(llvm::MCInst &insn) {
1999 bool EmulateInstructionMIPS::Emulate_Bcond_Link(llvm::MCInst &insn) {
2049 bool EmulateInstructionMIPS::Emulate_BXX_2ops(llvm::MCInst &insn) {
2102 bool EmulateInstructionMIPS::Emulate_BXX_2ops_C(llvm::MCInst &insn) {
2162 bool EmulateInstructionMIPS::Emulate_B16_MM(llvm::MCInst &insn) {
2189 bool EmulateInstructionMIPS::Emulate_Branch_MM(llvm::MCInst &insn) {
2290 bool EmulateInstructionMIPS::Emulate_JALRx16_MM(llvm::MCInst &insn) {
2329 bool EmulateInstructionMIPS::Emulate_JALx(llvm::MCInst &insn) {
2374 bool EmulateInstructionMIPS::Emulate_JALRS(llvm::MCInst &insn) {
2411 bool EmulateInstructionMIPS::Emulate_BAL(llvm::MCInst &insn) {
2442 bool EmulateInstructionMIPS::Emulate_BALC(llvm::MCInst &insn) {
2473 bool EmulateInstructionMIPS::Emulate_BC(llvm::MCInst &insn) {
2496 bool EmulateInstructionMIPS::Emulate_J(llvm::MCInst &insn) {
2519 bool EmulateInstructionMIPS::Emulate_JAL(llvm::MCInst &insn) {
2550 bool EmulateInstructionMIPS::Emulate_JALR(llvm::MCInst &insn) {
2585 bool EmulateInstructionMIPS::Emulate_JIALC(llvm::MCInst &insn) {
2623 bool EmulateInstructionMIPS::Emulate_JIC(llvm::MCInst &insn) {
2649 bool EmulateInstructionMIPS::Emulate_JR(llvm::MCInst &insn) {
2676 bool EmulateInstructionMIPS::Emulate_FP_branch(llvm::MCInst &insn) {
2713 bool EmulateInstructionMIPS::Emulate_BC1EQZ(llvm::MCInst &insn) {
2749 bool EmulateInstructionMIPS::Emulate_BC1NEZ(llvm::MCInst &insn) {
2792 bool EmulateInstructionMIPS::Emulate_3D_branch(llvm::MCInst &insn) {
2844 bool EmulateInstructionMIPS::Emulate_BNZB(llvm::MCInst &insn) {
2848 bool EmulateInstructionMIPS::Emulate_BNZH(llvm::MCInst &insn) {
2852 bool EmulateInstructionMIPS::Emulate_BNZW(llvm::MCInst &insn) {
2856 bool EmulateInstructionMIPS::Emulate_BNZD(llvm::MCInst &insn) {
2860 bool EmulateInstructionMIPS::Emulate_BZB(llvm::MCInst &insn) {
2864 bool EmulateInstructionMIPS::Emulate_BZH(llvm::MCInst &insn) {
2868 bool EmulateInstructionMIPS::Emulate_BZW(llvm::MCInst &insn) {
2872 bool EmulateInstructionMIPS::Emulate_BZD(llvm::MCInst &insn) {
2876 bool EmulateInstructionMIPS::Emulate_MSA_Branch_DF(llvm::MCInst &insn,
2936 bool EmulateInstructionMIPS::Emulate_BNZV(llvm::MCInst &insn) {
2940 bool EmulateInstructionMIPS::Emulate_BZV(llvm::MCInst &insn) {
2944 bool EmulateInstructionMIPS::Emulate_MSA_Branch_V(llvm::MCInst &insn,
2979 bool EmulateInstructionMIPS::Emulate_LDST_Imm(llvm::MCInst &insn) {
3012 bool EmulateInstructionMIPS::Emulate_LDST_Reg(llvm::MCInst &insn) {
tools/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h 103 bool Emulate_ADDiu(llvm::MCInst &insn);
105 bool Emulate_SUBU_ADDU(llvm::MCInst &insn);
107 bool Emulate_LUI(llvm::MCInst &insn);
109 bool Emulate_SW(llvm::MCInst &insn);
111 bool Emulate_LW(llvm::MCInst &insn);
113 bool Emulate_ADDIUSP(llvm::MCInst &insn);
115 bool Emulate_ADDIUS5(llvm::MCInst &insn);
117 bool Emulate_SWSP(llvm::MCInst &insn);
119 bool Emulate_SWM16_32(llvm::MCInst &insn);
121 bool Emulate_LWSP(llvm::MCInst &insn);
123 bool Emulate_LWM16_32(llvm::MCInst &insn);
125 bool Emulate_JRADDIUSP(llvm::MCInst &insn);
127 bool Emulate_LDST_Imm(llvm::MCInst &insn);
129 bool Emulate_LDST_Reg(llvm::MCInst &insn);
131 bool Emulate_BXX_3ops(llvm::MCInst &insn);
133 bool Emulate_BXX_3ops_C(llvm::MCInst &insn);
135 bool Emulate_BXX_2ops(llvm::MCInst &insn);
137 bool Emulate_BXX_2ops_C(llvm::MCInst &insn);
139 bool Emulate_Bcond_Link_C(llvm::MCInst &insn);
141 bool Emulate_Bcond_Link(llvm::MCInst &insn);
143 bool Emulate_FP_branch(llvm::MCInst &insn);
145 bool Emulate_3D_branch(llvm::MCInst &insn);
147 bool Emulate_BAL(llvm::MCInst &insn);
149 bool Emulate_BALC(llvm::MCInst &insn);
151 bool Emulate_BC(llvm::MCInst &insn);
153 bool Emulate_J(llvm::MCInst &insn);
155 bool Emulate_JAL(llvm::MCInst &insn);
157 bool Emulate_JALR(llvm::MCInst &insn);
159 bool Emulate_JIALC(llvm::MCInst &insn);
161 bool Emulate_JIC(llvm::MCInst &insn);
163 bool Emulate_JR(llvm::MCInst &insn);
165 bool Emulate_BC1EQZ(llvm::MCInst &insn);
167 bool Emulate_BC1NEZ(llvm::MCInst &insn);
169 bool Emulate_BNZB(llvm::MCInst &insn);
171 bool Emulate_BNZH(llvm::MCInst &insn);
173 bool Emulate_BNZW(llvm::MCInst &insn);
175 bool Emulate_BNZD(llvm::MCInst &insn);
177 bool Emulate_BZB(llvm::MCInst &insn);
179 bool Emulate_BZH(llvm::MCInst &insn);
181 bool Emulate_BZW(llvm::MCInst &insn);
183 bool Emulate_BZD(llvm::MCInst &insn);
185 bool Emulate_MSA_Branch_DF(llvm::MCInst &insn, int element_byte_size,
188 bool Emulate_BNZV(llvm::MCInst &insn);
190 bool Emulate_BZV(llvm::MCInst &insn);
192 bool Emulate_MSA_Branch_V(llvm::MCInst &insn, bool bnz);
194 bool Emulate_B16_MM(llvm::MCInst &insn);
196 bool Emulate_Branch_MM(llvm::MCInst &insn);
198 bool Emulate_JALRx16_MM(llvm::MCInst &insn);
200 bool Emulate_JALx(llvm::MCInst &insn);
202 bool Emulate_JALRS(llvm::MCInst &insn);
tools/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp 959 llvm::MCInst mc_insn;
1075 bool EmulateInstructionMIPS64::Emulate_DADDiu(llvm::MCInst &insn) {
1139 bool EmulateInstructionMIPS64::Emulate_SD(llvm::MCInst &insn) {
1196 bool EmulateInstructionMIPS64::Emulate_LD(llvm::MCInst &insn) {
1242 bool EmulateInstructionMIPS64::Emulate_LUI(llvm::MCInst &insn) {
1259 bool EmulateInstructionMIPS64::Emulate_DSUBU_DADDU(llvm::MCInst &insn) {
1342 bool EmulateInstructionMIPS64::Emulate_BXX_3ops(llvm::MCInst &insn) {
1393 bool EmulateInstructionMIPS64::Emulate_Bcond_Link(llvm::MCInst &insn) {
1438 bool EmulateInstructionMIPS64::Emulate_BAL(llvm::MCInst &insn) {
1469 bool EmulateInstructionMIPS64::Emulate_BALC(llvm::MCInst &insn) {
1504 bool EmulateInstructionMIPS64::Emulate_Bcond_Link_C(llvm::MCInst &insn) {
1572 bool EmulateInstructionMIPS64::Emulate_BXX_2ops(llvm::MCInst &insn) {
1624 bool EmulateInstructionMIPS64::Emulate_BC(llvm::MCInst &insn) {
1657 bool EmulateInstructionMIPS64::Emulate_BXX_3ops_C(llvm::MCInst &insn) {
1736 bool EmulateInstructionMIPS64::Emulate_BXX_2ops_C(llvm::MCInst &insn) {
1796 bool EmulateInstructionMIPS64::Emulate_J(llvm::MCInst &insn) {
1820 bool EmulateInstructionMIPS64::Emulate_JAL(llvm::MCInst &insn) {
1851 bool EmulateInstructionMIPS64::Emulate_JALR(llvm::MCInst &insn) {
1886 bool EmulateInstructionMIPS64::Emulate_JIALC(llvm::MCInst &insn) {
1924 bool EmulateInstructionMIPS64::Emulate_JIC(llvm::MCInst &insn) {
1950 bool EmulateInstructionMIPS64::Emulate_JR(llvm::MCInst &insn) {
1977 bool EmulateInstructionMIPS64::Emulate_FP_branch(llvm::MCInst &insn) {
2023 bool EmulateInstructionMIPS64::Emulate_BC1EQZ(llvm::MCInst &insn) {
2059 bool EmulateInstructionMIPS64::Emulate_BC1NEZ(llvm::MCInst &insn) {
2102 bool EmulateInstructionMIPS64::Emulate_3D_branch(llvm::MCInst &insn) {
2155 bool EmulateInstructionMIPS64::Emulate_BNZB(llvm::MCInst &insn) {
2159 bool EmulateInstructionMIPS64::Emulate_BNZH(llvm::MCInst &insn) {
2163 bool EmulateInstructionMIPS64::Emulate_BNZW(llvm::MCInst &insn) {
2167 bool EmulateInstructionMIPS64::Emulate_BNZD(llvm::MCInst &insn) {
2171 bool EmulateInstructionMIPS64::Emulate_BZB(llvm::MCInst &insn) {
2175 bool EmulateInstructionMIPS64::Emulate_BZH(llvm::MCInst &insn) {
2179 bool EmulateInstructionMIPS64::Emulate_BZW(llvm::MCInst &insn) {
2183 bool EmulateInstructionMIPS64::Emulate_BZD(llvm::MCInst &insn) {
2187 bool EmulateInstructionMIPS64::Emulate_MSA_Branch_DF(llvm::MCInst &insn,
2247 bool EmulateInstructionMIPS64::Emulate_BNZV(llvm::MCInst &insn) {
2251 bool EmulateInstructionMIPS64::Emulate_BZV(llvm::MCInst &insn) {
2255 bool EmulateInstructionMIPS64::Emulate_MSA_Branch_V(llvm::MCInst &insn,
2290 bool EmulateInstructionMIPS64::Emulate_LDST_Imm(llvm::MCInst &insn) {
2323 bool EmulateInstructionMIPS64::Emulate_LDST_Reg(llvm::MCInst &insn) {
tools/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h 92 bool Emulate_DADDiu(llvm::MCInst &insn);
94 bool Emulate_DSUBU_DADDU(llvm::MCInst &insn);
96 bool Emulate_LUI(llvm::MCInst &insn);
98 bool Emulate_SD(llvm::MCInst &insn);
100 bool Emulate_LD(llvm::MCInst &insn);
102 bool Emulate_LDST_Imm(llvm::MCInst &insn);
104 bool Emulate_LDST_Reg(llvm::MCInst &insn);
106 bool Emulate_BXX_3ops(llvm::MCInst &insn);
108 bool Emulate_BXX_3ops_C(llvm::MCInst &insn);
110 bool Emulate_BXX_2ops(llvm::MCInst &insn);
112 bool Emulate_BXX_2ops_C(llvm::MCInst &insn);
114 bool Emulate_Bcond_Link_C(llvm::MCInst &insn);
116 bool Emulate_Bcond_Link(llvm::MCInst &insn);
118 bool Emulate_FP_branch(llvm::MCInst &insn);
120 bool Emulate_3D_branch(llvm::MCInst &insn);
122 bool Emulate_BAL(llvm::MCInst &insn);
124 bool Emulate_BALC(llvm::MCInst &insn);
126 bool Emulate_BC(llvm::MCInst &insn);
128 bool Emulate_J(llvm::MCInst &insn);
130 bool Emulate_JAL(llvm::MCInst &insn);
132 bool Emulate_JALR(llvm::MCInst &insn);
134 bool Emulate_JIALC(llvm::MCInst &insn);
136 bool Emulate_JIC(llvm::MCInst &insn);
138 bool Emulate_JR(llvm::MCInst &insn);
140 bool Emulate_BC1EQZ(llvm::MCInst &insn);
142 bool Emulate_BC1NEZ(llvm::MCInst &insn);
144 bool Emulate_BNZB(llvm::MCInst &insn);
146 bool Emulate_BNZH(llvm::MCInst &insn);
148 bool Emulate_BNZW(llvm::MCInst &insn);
150 bool Emulate_BNZD(llvm::MCInst &insn);
152 bool Emulate_BZB(llvm::MCInst &insn);
154 bool Emulate_BZH(llvm::MCInst &insn);
156 bool Emulate_BZW(llvm::MCInst &insn);
158 bool Emulate_BZD(llvm::MCInst &insn);
160 bool Emulate_MSA_Branch_DF(llvm::MCInst &insn, int element_byte_size,
163 bool Emulate_BNZV(llvm::MCInst &insn);
165 bool Emulate_BZV(llvm::MCInst &insn);
167 bool Emulate_MSA_Branch_V(llvm::MCInst &insn, bool bnz);
tools/llvm-cfi-verify/lib/FileAnalysis.cpp 474 MCInst Instruction;
tools/llvm-cfi-verify/lib/FileAnalysis.h 80 MCInst Instruction; // Instruction.
tools/llvm-exegesis/lib/AArch64/Target.cpp 27 static MCInst loadImmediate(unsigned Reg, unsigned RegBitWidth,
45 std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
tools/llvm-exegesis/lib/Analysis.cpp 107 MCInst MI;
136 const MCInst &MCI = Point.keyInstruction();
225 const MCInst &MCI = Point.keyInstruction();
250 const std::vector<MCInst> &Instructions,
262 const std::vector<MCInst> &Instructions,
265 for (const MCInst &Instr : Instructions) {
tools/llvm-exegesis/lib/Assembler.cpp 93 void BasicBlockFiller::addInstruction(const MCInst &Inst, const DebugLoc &DL) {
117 void BasicBlockFiller::addInstructions(ArrayRef<MCInst> Insts,
119 for (const MCInst &Inst : Insts)
tools/llvm-exegesis/lib/Assembler.h 49 void addInstruction(const MCInst &Inst, const DebugLoc &DL = DebugLoc());
50 void addInstructions(ArrayRef<MCInst> Insts, const DebugLoc &DL = DebugLoc());
tools/llvm-exegesis/lib/BenchmarkResult.cpp 61 void serializeMCInst(const MCInst &MCInst, raw_ostream &OS) {
69 void deserializeMCInst(StringRef String, MCInst &Value) {
196 static void output(const MCInst &Value, void *Ctx, raw_ostream &Out) {
200 static StringRef input(StringRef Scalar, void *Ctx, MCInst &Value) {
tools/llvm-exegesis/lib/BenchmarkResult.h 35 std::vector<MCInst> Instructions;
65 const MCInst &keyInstruction() const { return Key.Instructions[0]; }
tools/llvm-exegesis/lib/BenchmarkRunner.cpp 93 const std::vector<MCInst> &Instructions = BC.Key.Instructions;
tools/llvm-exegesis/lib/CodeTemplate.cpp 57 MCInst InstructionTemplate::build() const {
58 MCInst Result;
tools/llvm-exegesis/lib/CodeTemplate.h 43 MCInst build() const;
tools/llvm-exegesis/lib/LlvmState.cpp 61 bool LLVMState::canAssemble(const MCInst &Inst) const {
tools/llvm-exegesis/lib/LlvmState.h 50 bool canAssemble(const MCInst &mc_inst) const;
tools/llvm-exegesis/lib/MCInstrDescView.cpp 362 const MCInstrInfo &MCInstrInfo, const MCInst &MCInst,
tools/llvm-exegesis/lib/MCInstrDescView.h 205 const MCInstrInfo &MCInstrInfo, const MCInst &MCInst,
tools/llvm-exegesis/lib/Mips/Target.cpp 24 std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
34 static MCInst loadImmediate(unsigned Reg, unsigned RegBitWidth,
46 std::vector<MCInst> ExegesisMipsTarget::setRegTo(const MCSubtargetInfo &STI,
tools/llvm-exegesis/lib/PowerPC/Target.cpp 25 std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
44 static MCInst loadImmediate(unsigned Reg, unsigned RegBitWidth,
53 std::vector<MCInst> ExegesisPowerPCTarget::setRegTo(const MCSubtargetInfo &STI,
tools/llvm-exegesis/lib/SchedClassResolution.cpp 221 const MCInst &MCI) {
232 const MCInst &MCI) {
tools/llvm-exegesis/lib/SchedClassResolution.h 45 const MCInstrInfo &InstrInfo, const MCInst &MCI);
tools/llvm-exegesis/lib/SnippetFile.cpp 37 void EmitInstruction(const MCInst &Instruction,
tools/llvm-exegesis/lib/SnippetRepetitor.cpp 27 FillFunction Repeat(ArrayRef<MCInst> Instructions,
56 FillFunction Repeat(ArrayRef<MCInst> Instructions,
67 for (const MCInst &Inst :
tools/llvm-exegesis/lib/SnippetRepetitor.h 41 virtual FillFunction Repeat(ArrayRef<MCInst> Instructions,
tools/llvm-exegesis/lib/Target.cpp 150 std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
tools/llvm-exegesis/lib/Target.h 72 virtual std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
tools/llvm-exegesis/lib/X86/Target.cpp 376 static MCInst loadImmediate(unsigned Reg, unsigned RegBitWidth,
386 static MCInst allocateStackSpace(unsigned Bytes) {
394 static MCInst fillStackSpace(unsigned MovOpcode, unsigned OffsetBytes,
408 static MCInst loadToReg(unsigned Reg, unsigned RMOpcode) {
420 static MCInst releaseStackSpace(unsigned Bytes) {
433 std::vector<MCInst> loadAndFinalize(unsigned Reg, unsigned RegBitWidth,
436 std::vector<MCInst> loadX87STAndFinalize(unsigned Reg);
438 std::vector<MCInst> loadX87FPAndFinalize(unsigned Reg);
440 std::vector<MCInst> popFlagAndFinalize();
443 ConstantInliner &add(const MCInst &Inst) {
453 std::vector<MCInst> Instructions;
457 std::vector<MCInst> ConstantInliner::loadAndFinalize(unsigned Reg,
467 std::vector<MCInst> ConstantInliner::loadX87STAndFinalize(unsigned Reg) {
482 std::vector<MCInst> ConstantInliner::loadX87FPAndFinalize(unsigned Reg) {
496 std::vector<MCInst> ConstantInliner::popFlagAndFinalize() {
553 std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
663 std::vector<MCInst> ExegesisX86Target::setRegTo(const MCSubtargetInfo &STI,
tools/llvm-mc/Disassembler.cpp 46 MCInst Inst;
tools/llvm-mca/CodeRegion.cpp 109 void CodeRegions::addInstruction(const MCInst &Instruction) {
tools/llvm-mca/CodeRegion.h 54 llvm::SmallVector<llvm::MCInst, 8> Instructions;
66 void addInstruction(const llvm::MCInst &Instruction) {
77 llvm::ArrayRef<llvm::MCInst> getInstructions() const { return Instructions; }
109 void addInstruction(const llvm::MCInst &Instruction);
112 llvm::ArrayRef<llvm::MCInst> getInstructionSequence(unsigned Idx) const {
tools/llvm-mca/CodeRegionGenerator.cpp 50 virtual void EmitInstruction(const MCInst &Inst,
70 ArrayRef<MCInst> GetInstructionSequence(unsigned Index) const {
tools/llvm-mca/Views/BottleneckAnalysis.cpp 289 const MCInst &MCI,
453 ArrayRef<MCInst> S, unsigned NumIter)
tools/llvm-mca/Views/BottleneckAnalysis.h 291 ArrayRef<MCInst> Source;
326 ArrayRef<MCInst> Sequence, unsigned Iterations);
tools/llvm-mca/Views/InstructionInfoView.cpp 40 const MCInst &Inst = Source[I];
tools/llvm-mca/Views/InstructionInfoView.h 57 llvm::ArrayRef<llvm::MCInst> Source;
63 bool ShouldPrintEncodings, llvm::ArrayRef<llvm::MCInst> S,
tools/llvm-mca/Views/ResourcePressureView.cpp 23 ArrayRef<MCInst> S)
159 for (const MCInst &MCI : Source) {
tools/llvm-mca/Views/ResourcePressureView.h 75 llvm::ArrayRef<llvm::MCInst> Source;
92 llvm::ArrayRef<llvm::MCInst> S);
tools/llvm-mca/Views/SummaryView.h 42 llvm::ArrayRef<llvm::MCInst> Source;
69 SummaryView(const llvm::MCSchedModel &Model, llvm::ArrayRef<llvm::MCInst> S,
tools/llvm-mca/Views/TimelineView.cpp 21 llvm::ArrayRef<llvm::MCInst> S, unsigned Iterations,
192 for (const MCInst &Inst : Source) {
302 for (const MCInst &Inst : Source) {
tools/llvm-mca/Views/TimelineView.h 124 llvm::ArrayRef<llvm::MCInst> Source;
169 llvm::ArrayRef<llvm::MCInst> S, unsigned Iterations,
tools/llvm-mca/llvm-mca.cpp 464 ArrayRef<MCInst> Insts = Region->getInstructions();
467 for (const MCInst &MCI : Insts) {
tools/llvm-objdump/MachODump.cpp 7594 MCInst Inst;
7689 MCInst Inst;
tools/llvm-objdump/llvm-objdump.cpp 687 virtual void printInst(MCInstPrinter &IP, const MCInst *MI,
732 void printInst(MCInstPrinter &IP, const MCInst *MI, ArrayRef<uint8_t> Bytes,
802 void printInst(MCInstPrinter &IP, const MCInst *MI, ArrayRef<uint8_t> Bytes,
854 void printInst(MCInstPrinter &IP, const MCInst *MI, ArrayRef<uint8_t> Bytes,
1414 MCInst Inst;
tools/sancov/sancov.cpp 757 MCInst Inst;
unittests/ExecutionEngine/JITLink/JITLinkTestCommon.cpp 200 Expected<std::pair<MCInst, size_t>>
207 MCInst Inst;
unittests/ExecutionEngine/JITLink/JITLinkTestCommon.h 163 static Expected<std::pair<MCInst, size_t>>
unittests/tools/llvm-exegesis/AArch64/TargetTest.cpp 53 std::vector<MCInst> setRegTo(unsigned Reg, const APInt &Value) {
unittests/tools/llvm-exegesis/Common/AssemblerUtils.h 45 inline void Check(ArrayRef<RegisterValue> RegisterInitialValues, MCInst Inst,
unittests/tools/llvm-exegesis/Mips/TargetTest.cpp 43 Matcher<MCInst> OpcodeIs(unsigned Opcode) {
44 return Property(&MCInst::getOpcode, Eq(Opcode));
47 Matcher<MCInst> IsLoadLowImm(int64_t Reg, int64_t Value) {
65 std::vector<MCInst> setRegTo(unsigned Reg, const APInt &Value) {
unittests/tools/llvm-exegesis/X86/BenchmarkResultTest.cpp 35 static std::string Dump(const MCInst &McInst) {
unittests/tools/llvm-exegesis/X86/SnippetFileTest.cpp 57 return Property(&MCInst::getOpcode, Eq(Opcode));
unittests/tools/llvm-exegesis/X86/SnippetRepetitorTest.cpp 46 const std::vector<MCInst> Instructions = {MCInstBuilder(X86::NOOP)};
unittests/tools/llvm-exegesis/X86/TargetTest.cpp 32 bool operator==(const MCInst &a, const MCInst &b) {
32 bool operator==(const MCInst &a, const MCInst &b) {
73 Matcher<MCInst> OpcodeIs(unsigned Opcode) {
74 return Property(&MCInst::getOpcode, Eq(Opcode));
77 Matcher<MCInst> IsMovImmediate(unsigned Opcode, int64_t Reg, int64_t Value) {
81 Matcher<MCInst> IsMovValueToStack(unsigned Opcode, int64_t Value,
88 Matcher<MCInst> IsMovValueFromStack(unsigned Opcode, unsigned Reg) {
94 Matcher<MCInst> IsStackAllocate(unsigned Size) {
99 Matcher<MCInst> IsStackDeallocate(unsigned Size) {
117 std::vector<MCInst> setRegTo(unsigned Reg, const APInt &Value) {
302 const MCInst CopySt0ToSt1 = MCInstBuilder(X86::ST_Frr).addReg(X86::ST1);
usr/include/c++/7.4.0/bits/alloc_traits.h 387 using allocator_type = allocator<_Tp>;
389 using value_type = _Tp;
392 using pointer = _Tp*;
395 using const_pointer = const _Tp*;
474 construct(allocator_type& __a, _Up* __p, _Args&&... __args)
474 construct(allocator_type& __a, _Up* __p, _Args&&... __args)
475 { __a.construct(__p, std::forward<_Args>(__args)...); }
486 destroy(allocator_type& __a, _Up* __p)
usr/include/c++/7.4.0/bits/allocator.h 108 class allocator: public __allocator_base<_Tp>
113 typedef _Tp* pointer;
114 typedef const _Tp* const_pointer;
115 typedef _Tp& reference;
116 typedef const _Tp& const_reference;
117 typedef _Tp value_type;
137 allocator(const allocator<_Tp1>&) throw() { }
158 operator!=(const allocator<_T1>&, const allocator<_T2>&)
158 operator!=(const allocator<_T1>&, const allocator<_T2>&)
164 operator!=(const allocator<_Tp>&, const allocator<_Tp>&)
164 operator!=(const allocator<_Tp>&, const allocator<_Tp>&)
usr/include/c++/7.4.0/bits/move.h 46 inline _GLIBCXX_CONSTEXPR _Tp*
47 __addressof(_Tp& __r) _GLIBCXX_NOEXCEPT
72 constexpr _Tp&&
73 forward(typename std::remove_reference<_Tp>::type& __t) noexcept
83 constexpr _Tp&&
84 forward(typename std::remove_reference<_Tp>::type&& __t) noexcept
98 move(_Tp&& __t) noexcept
104 : public __and_<__not_<is_nothrow_move_constructible<_Tp>>,
105 is_copy_constructible<_Tp>>::type { };
usr/include/c++/7.4.0/bits/ptr_traits.h 126 typedef _Tp* pointer;
128 typedef _Tp element_type;
141 pointer_to(__make_not_void<element_type>& __r) noexcept
141 pointer_to(__make_not_void<element_type>& __r) noexcept
usr/include/c++/7.4.0/bits/range_access.h 58 begin(const _Container& __cont) -> decltype(__cont.begin())
usr/include/c++/7.4.0/bits/stl_construct.h 74 _Construct(_T1* __p, _Args&&... __args)
74 _Construct(_T1* __p, _Args&&... __args)
75 { ::new(static_cast<void*>(__p)) _T1(std::forward<_Args>(__args)...); }
75 { ::new(static_cast<void*>(__p)) _T1(std::forward<_Args>(__args)...); }
97 _Destroy(_Tp* __pointer)
204 allocator<_Tp>&)
usr/include/c++/7.4.0/bits/stl_iterator.h 1224 __make_move_if_noexcept_iterator(_Tp* __i)
usr/include/c++/7.4.0/bits/stl_iterator_base_types.h 181 typedef _Tp value_type;
183 typedef _Tp* pointer;
184 typedef _Tp& reference;
192 typedef _Tp value_type;
194 typedef const _Tp* pointer;
195 typedef const _Tp& reference;
usr/include/c++/7.4.0/bits/stl_pair.h 100 return __and_<is_constructible<_T1, const _U1&>,
100 return __and_<is_constructible<_T1, const _U1&>,
107 return __and_<is_convertible<const _U1&, _T1>,
107 return __and_<is_convertible<const _U1&, _T1>,
114 return __and_<is_constructible<_T1, _U1&&>,
114 return __and_<is_constructible<_T1, _U1&&>,
121 return __and_<is_convertible<_U1&&, _T1>,
121 return __and_<is_convertible<_U1&&, _T1>,
128 using __do_converts = __and_<is_convertible<const _U1&, _T1>,
128 using __do_converts = __and_<is_convertible<const _U1&, _T1>,
133 return __and_<is_constructible<_T1, const _U1&>,
133 return __and_<is_constructible<_T1, const _U1&>,
142 using __do_converts = __and_<is_convertible<_U1&&, _T1>,
142 using __do_converts = __and_<is_convertible<_U1&&, _T1>,
147 return __and_<is_constructible<_T1, _U1&&>,
147 return __and_<is_constructible<_T1, _U1&&>,
209 : private __pair_base<_T1, _T2>
211 typedef _T1 first_type; /// @c first_type is the first bound type
214 _T1 first; /// @c first is a copy of the first object
252 using _PCCP = _PCC<true, _T1, _T2>;
260 constexpr pair(const _T1& __a, const _T2& __b)
269 explicit constexpr pair(const _T1& __a, const _T2& __b)
283 _T1, _T2>;
311 constexpr pair(_U1&& __x, const _T2& __y)
325 constexpr pair(const _T1& __x, _U2&& __y)
332 explicit pair(const _T1& __x, _U2&& __y)
341 constexpr pair(_U1&& __x, _U2&& __y)
379 __and_<is_copy_assignable<_T1>,
390 __and_<is_move_assignable<_T1>,
402 typename enable_if<__and_<is_assignable<_T1&, const _U1&>,
402 typename enable_if<__and_<is_assignable<_T1&, const _U1&>,
405 operator=(const pair<_U1, _U2>& __p)
413 typename enable_if<__and_<is_assignable<_T1&, _U1&&>,
413 typename enable_if<__and_<is_assignable<_T1&, _U1&&>,
416 operator=(pair<_U1, _U2>&& __p)
524 make_pair(_T1&& __x, _T2&& __y)
usr/include/c++/7.4.0/bits/stl_uninitialized.h 288 _ForwardIterator __result, allocator<_Tp>&)
644 allocator<_Tp>&)
usr/include/c++/7.4.0/bits/stl_vector.h 77 rebind<_Tp>::other _Tp_alloc_type;
216 class vector : protected _Vector_base<_Tp, _Alloc>
227 typedef _Vector_base<_Tp, _Alloc> _Base;
232 typedef _Tp value_type;
919 _Tp*
923 const _Tp*
962 emplace_back(_Args&&... __args);
1483 _M_realloc_insert(iterator __position, _Args&&... __args);
1561 _Up*
1562 _M_data_ptr(_Up* __ptr) const _GLIBCXX_NOEXCEPT
usr/include/c++/7.4.0/bits/unique_ptr.h 824 make_unique(_Args&&... __args)
usr/include/c++/7.4.0/bits/vector.tcc 101 std::forward<_Args>(__args)...);
105 _M_realloc_insert(end(), std::forward<_Args>(__args)...);
418 std::forward<_Args>(__args)...);
usr/include/c++/7.4.0/ext/alloc_traits.h 117 { typedef typename _Base_type::template rebind_alloc<_Tp> other; };
usr/include/c++/7.4.0/ext/new_allocator.h 63 typedef _Tp* pointer;
64 typedef const _Tp* const_pointer;
65 typedef _Tp& reference;
66 typedef const _Tp& const_reference;
67 typedef _Tp value_type;
84 new_allocator(const new_allocator<_Tp1>&) _GLIBCXX_USE_NOEXCEPT { }
111 return static_cast<_Tp*>(::operator new(__n * sizeof(_Tp)));
130 { return size_t(-1) / sizeof(_Tp); }
135 construct(_Up* __p, _Args&&... __args)
135 construct(_Up* __p, _Args&&... __args)
136 { ::new((void *)__p) _Up(std::forward<_Args>(__args)...); }
136 { ::new((void *)__p) _Up(std::forward<_Args>(__args)...); }
140 destroy(_Up* __p) { __p->~_Up(); }
160 operator!=(const new_allocator<_Tp>&, const new_allocator<_Tp>&)
160 operator!=(const new_allocator<_Tp>&, const new_allocator<_Tp>&)
usr/include/c++/7.4.0/initializer_list 50 typedef _E value_type;
51 typedef const _E& reference;
52 typedef const _E& const_reference;
54 typedef const _E* iterator;
55 typedef const _E* const_iterator;
usr/include/c++/7.4.0/tuple 56 struct __is_empty_non_tuple : is_empty<_Tp> { };
125 constexpr _Head_base(const _Head& __h)
132 constexpr _Head_base(_UHead&& __h)
159 static constexpr _Head&
162 static constexpr const _Head&
165 _Head _M_head_impl;
186 : public _Tuple_impl<_Idx + 1, _Tail...>,
187 private _Head_base<_Idx, _Head>
191 typedef _Tuple_impl<_Idx + 1, _Tail...> _Inherited;
192 typedef _Head_base<_Idx, _Head> _Base;
194 static constexpr _Head&
197 static constexpr const _Head&
210 constexpr _Tuple_impl(const _Head& __head, const _Tail&... __tail)
210 constexpr _Tuple_impl(const _Head& __head, const _Tail&... __tail)
216 constexpr _Tuple_impl(_UHead&& __head, _UTail&&... __tail)
216 constexpr _Tuple_impl(_UHead&& __head, _UTail&&... __tail)
230 constexpr _Tuple_impl(const _Tuple_impl<_Idx, _UElements...>& __in)
235 constexpr _Tuple_impl(_Tuple_impl<_Idx, _UHead, _UTails...>&& __in)
235 constexpr _Tuple_impl(_Tuple_impl<_Idx, _UHead, _UTails...>&& __in)
242 _Tuple_impl(allocator_arg_t __tag, const _Alloc& __a)
248 const _Head& __head, const _Tail&... __tail)
248 const _Head& __head, const _Tail&... __tail)
262 _Tuple_impl(allocator_arg_t __tag, const _Alloc& __a,
268 _Tuple_impl(allocator_arg_t __tag, const _Alloc& __a,
350 static constexpr _Head&
353 static constexpr const _Head&
360 constexpr _Tuple_impl(const _Head& __head)
365 constexpr _Tuple_impl(_UHead&& __head)
390 const _Head& __head)
473 return __and_<is_constructible<_Elements, const _UElements&>...>::value;
473 return __and_<is_constructible<_Elements, const _UElements&>...>::value;
479 return __and_<is_convertible<const _UElements&, _Elements>...>::value;
479 return __and_<is_convertible<const _UElements&, _Elements>...>::value;
485 return __and_<is_constructible<_Elements, _UElements&&>...>::value;
485 return __and_<is_constructible<_Elements, _UElements&&>...>::value;
491 return __and_<is_convertible<_UElements&&, _Elements>...>::value;
491 return __and_<is_convertible<_UElements&&, _Elements>...>::value;
508 return __not_<is_same<tuple<_Elements...>,
556 class tuple : public _Tuple_impl<0, _Elements...>
558 typedef _Tuple_impl<0, _Elements...> _Inherited;
598 _Elements...>;
608 constexpr tuple(const _Elements&... __elements)
619 explicit constexpr tuple(const _Elements&... __elements)
628 _Elements...>;
636 _Elements...>;
646 constexpr tuple(_UElements&&... __elements)
668 _Elements...>;
730 const _Elements&... __elements)
741 const _Elements&... __elements)
947 constexpr tuple(const _T1& __a1, const _T2& __a2)
947 constexpr tuple(const _T1& __a1, const _T2& __a2)
956 explicit constexpr tuple(const _T1& __a1, const _T2& __a2)
956 explicit constexpr tuple(const _T1& __a1, const _T2& __a2)
971 constexpr tuple(_U1&& __a1, _U2&& __a2)
971 constexpr tuple(_U1&& __a1, _U2&& __a2)
1066 tuple(allocator_arg_t __tag, const _Alloc& __a)
1078 const _T1& __a1, const _T2& __a2)
1078 const _T1& __a1, const _T2& __a2)
1090 const _T1& __a1, const _T2& __a2)
1090 const _T1& __a1, const _T2& __a2)
1280 : tuple_element<__i - 1, tuple<_Tail...> > { };
1288 typedef _Head type;
1302 constexpr _Head&
1303 __get_helper(_Tuple_impl<__i, _Head, _Tail...>& __t) noexcept
1303 __get_helper(_Tuple_impl<__i, _Head, _Tail...>& __t) noexcept
1307 constexpr const _Head&
1308 __get_helper(const _Tuple_impl<__i, _Head, _Tail...>& __t) noexcept
1308 __get_helper(const _Tuple_impl<__i, _Head, _Tail...>& __t) noexcept
1309 { return _Tuple_impl<__i, _Head, _Tail...>::_M_head(__t); }
1309 { return _Tuple_impl<__i, _Head, _Tail...>::_M_head(__t); }
1313 constexpr __tuple_element_t<__i, tuple<_Elements...>>&
1313 constexpr __tuple_element_t<__i, tuple<_Elements...>>&
1313 constexpr __tuple_element_t<__i, tuple<_Elements...>>&
1314 get(tuple<_Elements...>& __t) noexcept
1319 constexpr const __tuple_element_t<__i, tuple<_Elements...>>&
1319 constexpr const __tuple_element_t<__i, tuple<_Elements...>>&
1319 constexpr const __tuple_element_t<__i, tuple<_Elements...>>&
1320 get(const tuple<_Elements...>& __t) noexcept
1325 constexpr __tuple_element_t<__i, tuple<_Elements...>>&&
1325 constexpr __tuple_element_t<__i, tuple<_Elements...>>&&
1325 constexpr __tuple_element_t<__i, tuple<_Elements...>>&&
1326 get(tuple<_Elements...>&& __t) noexcept
usr/include/c++/7.4.0/type_traits 215 : public __is_void_helper<typename remove_cv<_Tp>::type>::type
326 : public __is_integral_helper<typename remove_cv<_Tp>::type>::type
354 : public __is_floating_point_helper<typename remove_cv<_Tp>::type>::type
381 : public __is_pointer_helper<typename remove_cv<_Tp>::type>::type
567 : public __is_null_pointer_helper<typename remove_cv<_Tp>::type>::type
581 : public __or_<is_lvalue_reference<_Tp>,
582 is_rvalue_reference<_Tp>>::type
588 : public __or_<is_integral<_Tp>, is_floating_point<_Tp>>::type
588 : public __or_<is_integral<_Tp>, is_floating_point<_Tp>>::type
601 : public __not_<__or_<is_function<_Tp>, is_reference<_Tp>,
601 : public __not_<__or_<is_function<_Tp>, is_reference<_Tp>,
602 is_void<_Tp>>>::type
611 : public __or_<is_arithmetic<_Tp>, is_enum<_Tp>, is_pointer<_Tp>,
611 : public __or_<is_arithmetic<_Tp>, is_enum<_Tp>, is_pointer<_Tp>,
611 : public __or_<is_arithmetic<_Tp>, is_enum<_Tp>, is_pointer<_Tp>,
612 is_member_pointer<_Tp>, is_null_pointer<_Tp>>::type
612 is_member_pointer<_Tp>, is_null_pointer<_Tp>>::type
631 : public __is_member_pointer_helper<typename remove_cv<_Tp>::type>::type
638 : public __or_<is_object<_Tp>, is_reference<_Tp>>::type
638 : public __or_<is_object<_Tp>, is_reference<_Tp>>::type
777 : public __and_<is_array<_Tp>, __not_<extent<_Tp>>>
777 : public __and_<is_array<_Tp>, __not_<extent<_Tp>>>
798 typedef decltype(__test<_Tp>(0)) type;
811 remove_all_extents<_Tp>::type>::type
825 : public __is_destructible_safe<_Tp>::type
984 typedef decltype(__test<_Tp, _Arg>(0)) type;
989 : public __and_<is_destructible<_Tp>,
990 __is_direct_constructible_impl<_Tp, _Arg>>
1072 __is_direct_constructible_ref_cast<_Tp, _Arg>,
1073 __is_direct_constructible_new_safe<_Tp, _Arg>
1079 : public __is_direct_constructible_new<_Tp, _Arg>::type
1119 : public __is_direct_constructible<_Tp, _Arg>
1130 : public __is_constructible_impl<_Tp, _Args...>::type
1142 : public is_constructible<_Tp, const _Tp&>
1142 : public is_constructible<_Tp, const _Tp&>
1148 : public __is_copy_constructible_impl<_Tp>
1160 : public is_constructible<_Tp, _Tp&&>
1160 : public is_constructible<_Tp, _Tp&&>
1166 : public __is_move_constructible_impl<_Tp>
1215 : public __and_<is_constructible<_Tp, _Args...>,
1216 __is_nt_constructible_impl<_Tp, _Args...>>
1246 : public is_nothrow_constructible<_Tp, _Tp&&>
1246 : public is_nothrow_constructible<_Tp, _Tp&&>
1252 : public __is_nothrow_move_constructible_impl<_Tp>
1286 : public is_assignable<_Tp&, const _Tp&>
1286 : public is_assignable<_Tp&, const _Tp&>
1292 : public __is_copy_assignable_impl<_Tp>
1304 : public is_assignable<_Tp&, _Tp&&>
1304 : public is_assignable<_Tp&, _Tp&&>
1310 : public __is_move_assignable_impl<_Tp>
1526 static void __test_aux(_To1);
1538 typedef decltype(__test<_From, _To>(0)) type;
1545 : public __is_convertible_helper<_From, _To>::type
1554 { typedef _Tp type; };
1558 { typedef _Tp type; };
1563 { typedef _Tp type; };
1574 remove_const<typename remove_volatile<_Tp>::type>::type type;
1629 { typedef _Tp type; };
1633 { typedef _Tp type; };
1659 { typedef _Tp&& type; };
1955 { typedef _Tp type; };
2104 { typedef typename remove_cv<_Up>::type __type; };
2131 typedef _Tp __type;
2171 { typedef _Iffalse type; };
utils/unittest/googlemock/include/gmock/gmock-generated-matchers.h 679 typename internal::DecayArray<T6>::type,
682 const T5& e5, const T6& e6, const T7& e7) {
689 typename internal::DecayArray<T6>::type,
utils/unittest/googlemock/include/gmock/gmock-matchers.h 178 virtual bool MatchAndExplain(T x, MatchResultListener* listener) const = 0;
206 bool operator()(const A& a, const B& b) const { return a == b; }
206 bool operator()(const A& a, const B& b) const { return a == b; }
258 bool MatchAndExplain(T x, MatchResultListener* listener) const {
263 bool Matches(T x) const {
277 void ExplainMatchResultTo(T x, ::std::ostream* os) const {
293 explicit MatcherBase(const MatcherInterface<T>* impl)
310 ::testing::internal::linked_ptr<const MatcherInterface<T> > impl_;
321 class Matcher : public internal::MatcherBase<T> {
329 explicit Matcher(const MatcherInterface<T>* impl)
334 Matcher(T value); // NOLINT
445 operator Matcher<T>() const {
446 return Matcher<T>(new MonomorphicImpl<T>(impl_));
451 class MonomorphicImpl : public MatcherInterface<T> {
463 virtual bool MatchAndExplain(T x, MatchResultListener* listener) const {
486 inline Matcher<T> MakeMatcher(const MatcherInterface<T>* impl) {
486 inline Matcher<T> MakeMatcher(const MatcherInterface<T>* impl) {
519 static Matcher<T> Cast(const M& polymorphic_matcher_or_value) {
519 static Matcher<T> Cast(const M& polymorphic_matcher_or_value) {
536 internal::ImplicitlyConvertible<M, Matcher<T> >::value>());
536 internal::ImplicitlyConvertible<M, Matcher<T> >::value>());
540 static Matcher<T> CastImpl(const M& value, BooleanConstant<false>) {
540 static Matcher<T> CastImpl(const M& value, BooleanConstant<false>) {
547 static Matcher<T> CastImpl(const M& polymorphic_matcher_or_value,
547 static Matcher<T> CastImpl(const M& polymorphic_matcher_or_value,
567 static Matcher<T> Cast(const Matcher<U>& source_matcher) {
574 explicit Impl(const Matcher<U>& source_matcher)
591 const Matcher<U> source_matcher_;
602 static Matcher<T> Cast(const Matcher<T>& matcher) { return matcher; }
602 static Matcher<T> Cast(const Matcher<T>& matcher) { return matcher; }
612 inline Matcher<T> MatcherCast(const M& matcher) {
612 inline Matcher<T> MatcherCast(const M& matcher) {
613 return internal::MatcherCastImpl<T, M>::Cast(matcher);
613 return internal::MatcherCastImpl<T, M>::Cast(matcher);
629 static inline Matcher<T> Cast(const M& polymorphic_matcher_or_value) {
630 return internal::MatcherCastImpl<T, M>::Cast(polymorphic_matcher_or_value);
643 static inline Matcher<T> Cast(const Matcher<U>& matcher) {
643 static inline Matcher<T> Cast(const Matcher<U>& matcher) {
662 return MatcherCast<T>(matcher);
667 inline Matcher<T> SafeMatcherCast(const M& polymorphic_matcher) {
668 return SafeMatcherCastImpl<T>::Cast(polymorphic_matcher);
897 explicit ComparisonBase(const Rhs& rhs) : rhs_(rhs) {}
907 explicit Impl(const Rhs& rhs) : rhs_(rhs) {}
921 Rhs rhs_;
924 Rhs rhs_;
929 class EqMatcher : public ComparisonBase<EqMatcher<Rhs>, Rhs, AnyEq> {
929 class EqMatcher : public ComparisonBase<EqMatcher<Rhs>, Rhs, AnyEq> {
931 explicit EqMatcher(const Rhs& rhs)
1494 class BothOfMatcherImpl : public MatcherInterface<T> {
1496 BothOfMatcherImpl(const Matcher<T>& matcher1, const Matcher<T>& matcher2)
1496 BothOfMatcherImpl(const Matcher<T>& matcher1, const Matcher<T>& matcher2)
1515 virtual bool MatchAndExplain(T x, MatchResultListener* listener) const {
1546 const Matcher<T> matcher1_;
1547 const Matcher<T> matcher2_;
1649 operator Matcher<T>() const {
1650 return Matcher<T>(new BothOfMatcherImpl<T>(SafeMatcherCast<T>(matcher1_),
1650 return Matcher<T>(new BothOfMatcherImpl<T>(SafeMatcherCast<T>(matcher1_),
1651 SafeMatcherCast<T>(matcher2_)));
2261 bool MatchAndExplain(const T&value, MatchResultListener* listener) const {
2272 bool MatchAndExplainImpl(false_type /* is_not_pointer */, const Class& obj,
2288 bool MatchAndExplainImpl(true_type /* is_pointer */, const Class* p,
3113 class ElementsAreMatcherImpl : public MatcherInterface<Container> {
3169 virtual bool MatchAndExplain(Container container,
3454 Matcher<Target> operator()(const Arg& a) const {
3496 operator Matcher<Container>() const {
3509 return MakeMatcher(new ElementsAreMatcherImpl<Container>(
3760 inline internal::EqMatcher<T> Eq(T x) { return internal::EqMatcher<T>(x); }
3760 inline internal::EqMatcher<T> Eq(T x) { return internal::EqMatcher<T>(x); }
3931 internal::PropertyMatcher<Class, PropertyType> > Property(
utils/unittest/googlemock/include/gmock/internal/gmock-internal-utils.h 257 GMOCK_KIND_OF_(From), From, GMOCK_KIND_OF_(To), To> {}; // NOLINT
257 GMOCK_KIND_OF_(From), From, GMOCK_KIND_OF_(To), To> {}; // NOLINT
355 template <typename T> struct DecayArray { typedef T type; }; // NOLINT
410 typedef RawContainer type;
413 static const_reference ConstReference(const RawContainer& container) {
415 testing::StaticAssertTypeEq<RawContainer,
419 static type Copy(const RawContainer& container) { return container; }
utils/unittest/googletest/include/gtest/gtest-printers.h 366 void UniversalPrint(const T& value, ::std::ostream* os);
373 const C& container, ::std::ostream* os) {
377 for (typename C::const_iterator it = container.begin();
439 const T& value, ::std::ostream* os) {
455 void PrintTo(const T& value, ::std::ostream* os) {
478 DefaultPrintTo(IsContainerTest<T>(0), is_pointer<T>(), value, os);
699 static void Print(const T& value, ::std::ostream* os) {
856 typedef T T1;
utils/unittest/googletest/include/gtest/internal/gtest-internal.h 782 struct RemoveReference { typedef T type; }; // NOLINT
795 struct RemoveConst { typedef T type; }; // NOLINT
830 struct AddReference { typedef T& type; }; // NOLINT
863 static typename AddReference<From>::type MakeFrom();
875 static char Helper(To);
933 typename C::iterator* /* it */ = NULL,
934 typename C::const_iterator* /* const_it */ = NULL) {