reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/MachineOperand.h

  796     Op.setSubReg(SubReg);

lib/CodeGen/LiveDebugVariables.cpp

 1044           MO.setSubReg(locations[OldLocNo].getSubReg());
 1195         Loc.setSubReg(0);

lib/CodeGen/MachineOperand.cpp

   81     setSubReg(SubIdx);
   90     setSubReg(0);

lib/CodeGen/MachinePipeliner.cpp

  373       RegOp.setSubReg(0);

lib/CodeGen/MachineSink.cpp

  832     DbgMI->getOperand(0).setSubReg(SrcMO->getSubReg());
 1014     User->getOperand(0).setSubReg(MI.getOperand(1).getSubReg());

lib/CodeGen/PeepholeOptimizer.cpp

  590         Copy->getOperand(0).setSubReg(SubIdx);
  857     MOSrc.setSubReg(NewSubReg);
  947     MO.setSubReg(NewSubReg);
 1074     MO.setSubReg(NewSubReg);
 1240     NewCopy->getOperand(0).setSubReg(Def.SubReg);

lib/CodeGen/RegAllocFast.cpp

  770     MO.setSubReg(0);
  867   MO.setSubReg(0);

lib/CodeGen/RegisterCoalescer.cpp

 1302         DefMO.setSubReg(0);
 1363     NewMI.getOperand(0).setSubReg(NewIdx);

lib/CodeGen/TailDuplicator.cpp

  427             MO.setSubReg(TRI->composeSubRegIndices(MO.getSubReg(),

lib/CodeGen/TargetInstrInfo.cpp

  218     CommutedMI->getOperand(0).setSubReg(SubReg0);
  222   CommutedMI->getOperand(Idx2).setSubReg(SubReg1);
  223   CommutedMI->getOperand(Idx1).setSubReg(SubReg2);

lib/CodeGen/TwoAddressInstructionPass.cpp

 1490       SrcMO.setSubReg(0);
 1606     MO.setSubReg(0);
 1624             MO.setSubReg(0);
 1768         mi->getOperand(0).setSubReg(SubIdx);

lib/CodeGen/VirtRegMap.cpp

  565           MO.setSubReg(0);

lib/Target/AArch64/AArch64InstrInfo.cpp

 3344         LoadDst.setSubReg(DstMO.getSubReg());
 4848       NewMI->getOperand(0).setSubReg(AArch64::sub_32);

lib/Target/AArch64/AArch64InstructionSelector.cpp

 1983         I.getOperand(1).setSubReg(AArch64::sub_32);

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

 1197     I.getOperand(1).setSubReg(SubRegIdx);

lib/Target/AMDGPU/SIFoldOperands.cpp

  677       UseMI->getOperand(1).setSubReg(OpToFold.getSubReg());
  791         UseMI->getOperand(1).setSubReg(0);
  813         UseMI->getOperand(1).setSubReg(OpToFold.getSubReg());

lib/Target/AMDGPU/SIInstrInfo.cpp

 1660   NonRegOp.setSubReg(SubReg);
 2402       Src0->setSubReg(Src1SubReg);
 4113     Src0.setSubReg(Src1.getSubReg());
 4118   Src1.setSubReg(Src0SubReg);
 4293   Op.setSubReg(0);

lib/Target/AMDGPU/SIPeepholeSDWA.cpp

  278   To.setSubReg(From.getSubReg());

lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp

  138           MO.setSubReg(0);

lib/Target/AMDGPU/SIShrinkInstructions.cpp

   91           Src0.setSubReg(0);
   95           Src0.setSubReg(0);

lib/Target/Hexagon/HexagonBitSimplify.cpp

  378     I->setSubReg(NewSR);
  396     I->setSubReg(NewSR);
 1930   ValOp.setSubReg(H.Sub);

lib/Target/Hexagon/HexagonExpandCondsets.cpp

  924       Op.setSubReg(RN.Sub);

lib/Target/Hexagon/HexagonFrameLowering.cpp

 2287           SrcOp.setSubReg(0);

lib/Target/Hexagon/HexagonHardwareLoops.cpp

 1921         MO.setSubReg(PredRSub);

lib/Target/Hexagon/HexagonSplitDouble.cpp

 1095     Op.setSubReg(0);

lib/Target/Hexagon/RDFCopy.cpp

  181         Op.setSubReg(0);

lib/Target/Mips/MipsISelLowering.cpp

 1282     MIB->getOperand(0).setSubReg(Mips::sub_32);

lib/Target/PowerPC/PPCInstrInfo.cpp

  437     MI.getOperand(0).setSubReg(SubReg2);
  441   MI.getOperand(2).setSubReg(SubReg1);
  442   MI.getOperand(1).setSubReg(SubReg2);
 2002     SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);

lib/Target/PowerPC/PPCVSXCopy.cpp

  134           SrcMO.setSubReg(PPC::sub_64);

lib/Target/PowerPC/PPCVSXFMAMutate.cpp

  249         MI.getOperand(0).setSubReg(KilledProdSubReg);
  250         MI.getOperand(1).setSubReg(KilledProdSubReg);
  251         MI.getOperand(3).setSubReg(AddSubReg);
  265           MI.getOperand(2).setSubReg(AddSubReg);
  270           MI.getOperand(2).setSubReg(OtherProdSubReg);

lib/Target/X86/X86DomainReassignment.cpp

  516         MO.setSubReg(0);

lib/Target/X86/X86InstrInfo.cpp

 4932         NewMI->getOperand(0).setSubReg(X86::sub_32bit);

lib/Target/X86/X86InstructionSelector.cpp

  287       I.getOperand(1).setSubReg(getSubRegIndex(DstRC));
  764   I.getOperand(1).setSubReg(SubIdx);