|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/CodeGen/MachineInstr.h 1120 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
1120 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
1136 getOperand(0).getSubReg() == getOperand(1).getSubReg();
1136 getOperand(0).getSubReg() == getOperand(1).getSubReg();
include/llvm/CodeGen/MachineOperand.h 453 return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
lib/CodeGen/CalcSpillWeights.cpp 57 sub = mi->getOperand(0).getSubReg();
59 hsub = mi->getOperand(1).getSubReg();
61 sub = mi->getOperand(1).getSubReg();
63 hsub = mi->getOperand(0).getSubReg();
lib/CodeGen/DetectDeadLanes.cpp 162 unsigned SrcSubIdx = MO.getSubReg();
201 unsigned MOSubReg = MO.getSubReg();
297 TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes);
346 assert(Def.getSubReg() == 0 &&
398 unsigned MOSubReg = MO.getSubReg();
412 assert(Def.getSubReg() == 0 &&
427 unsigned SubReg = MO.getSubReg();
460 unsigned SubReg = MO.getSubReg();
lib/CodeGen/ExpandPostRAPseudos.cpp 84 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
lib/CodeGen/GlobalISel/GISelKnownBits.cpp 134 if (Dst.getSubReg() == 0 /*NoSubRegister*/ && Src.getReg().isVirtual() &&
135 Src.getSubReg() == 0 /*NoSubRegister*/ &&
lib/CodeGen/InlineSpiller.cpp 820 if (!SpillSubRegs && MO.getSubReg())
930 return !Def.getOperand(0).getSubReg();
lib/CodeGen/LiveDebugVariables.cpp 235 locations[i].getSubReg() == LocMO.getSubReg())
235 locations[i].getSubReg() == LocMO.getSubReg())
776 if (MO.getSubReg() || !MI->isCopy())
872 if (LI && !LocMO.getSubReg())
1044 MO.setSubReg(locations[OldLocNo].getSubReg());
1185 bool Success = TII.getStackSlotRange(TRC, Loc.getSubReg(), SpillSize,
lib/CodeGen/LiveInterval.cpp 908 if ((TRI.getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
978 unsigned SubReg = MO.getSubReg();
lib/CodeGen/LiveIntervals.cpp 556 unsigned SubReg = MO.getSubReg();
783 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(MO.getSubReg());
786 } else if (MO.getSubReg() == 0) {
995 unsigned SubReg = MO.getSubReg();
1407 unsigned SubReg = MO.getSubReg();
1517 unsigned SubReg = MO.getSubReg();
1539 if (MO.getSubReg() && !MO.isUndef())
1558 if (MO.getSubReg() && !MO.isUndef())
lib/CodeGen/LiveRangeCalc.cpp 86 unsigned SubReg = MO.getSubReg();
177 unsigned SubReg = MO.getSubReg();
lib/CodeGen/LiveRangeEdit.cpp 202 if (MO.getSubReg())
250 unsigned SubReg = MO.getSubReg();
lib/CodeGen/MachineCSE.cpp 180 if (DefMI->getOperand(0).getSubReg())
194 if (DefMI->getOperand(1).getSubReg())
lib/CodeGen/MachineInstr.cpp 907 if (unsigned SubIdx = MO.getSubReg()) {
977 else if (MO.getSubReg() && !MO.isUndef())
1926 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
1941 MO.getSubReg() == 0)
lib/CodeGen/MachineOperand.cpp 77 if (SubIdx && getSubReg())
78 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
86 if (getSubReg()) {
87 Reg = TRI.getSubReg(Reg, getSubReg());
282 getSubReg() == Other.getSubReg();
282 getSubReg() == Other.getSubReg();
347 return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
781 if (unsigned SubReg = getSubReg()) {
lib/CodeGen/MachinePipeliner.cpp 354 assert(DefOp.getSubReg() == 0);
359 if (RegOp.getSubReg() == 0)
370 RegOp.getSubReg());
lib/CodeGen/MachineSink.cpp 821 if (!PostRA && (DbgMO.getSubReg() != SrcMO->getSubReg() ||
821 if (!PostRA && (DbgMO.getSubReg() != SrcMO->getSubReg() ||
822 DbgMO.getSubReg() != DstMO->getSubReg()))
822 DbgMO.getSubReg() != DstMO->getSubReg()))
832 DbgMI->getOperand(0).setSubReg(SrcMO->getSubReg());
1014 User->getOperand(0).setSubReg(MI.getOperand(1).getSubReg());
lib/CodeGen/MachineVerifier.cpp 1561 if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
1561 if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
1683 unsigned SubIdx = MO->getSubReg();
1928 if (SubRangeCheck || MO->getSubReg() == 0) {
1975 unsigned SubRegIdx = MO->getSubReg();
2078 unsigned SubRegIdx = MO->getSubReg();
2427 (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
2558 unsigned Sub = MOI->getSubReg();
lib/CodeGen/OptimizePHIs.cpp 118 if (SrcMI && SrcMI->isCopy() && !SrcMI->getOperand(0).getSubReg() &&
119 !SrcMI->getOperand(1).getSubReg() &&
lib/CodeGen/PHIElimination.cpp 251 assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
377 unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg();
lib/CodeGen/PeepholeOptimizer.cpp 510 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
845 Src = RegSubRegPair(MOSrc.getReg(), MOSrc.getSubReg());
848 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg());
891 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg());
928 Src = RegSubRegPair(MOInsertedReg.getReg(), MOInsertedReg.getSubReg());
933 if (MODef.getSubReg())
976 if (MOExtractedReg.getSubReg())
984 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg());
1053 if ((Src.SubReg = MOInsertedReg.getSubReg()))
1063 return MODef.getSubReg() == 0;
1150 return RegSubRegPair(MODef.getReg(), MODef.getSubReg());
1322 if (!MI.getOperand(0).getSubReg() && Register::isVirtualRegister(Reg) &&
1411 unsigned SrcSubReg = MI.getOperand(1).getSubReg();
1412 unsigned PrevSrcSubReg = PrevCopy->getOperand(1).getSubReg();
1817 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
1825 return ValueTrackerResult(Src.getReg(), Src.getSubReg());
1839 if (DefOp.getSubReg() != DefSubReg)
1875 return ValueTrackerResult(Src.getReg(), Src.getSubReg());
1882 if (Def->getOperand(DefIdx).getSubReg())
1926 if (Def->getOperand(DefIdx).getSubReg())
2017 if (Def->getOperand(2).getSubReg())
2031 if (Def->getOperand(0).getSubReg() != DefSubReg)
2042 Res.addSource(MO.getReg(), MO.getSubReg());
lib/CodeGen/RegAllocFast.cpp 767 unsigned SubRegIdx = MO.getSubReg();
858 if (!MO.getSubReg()) {
865 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : Register());
896 (MO.getSubReg() && MI.readsVirtualRegister(Reg))) {
935 } else if (MO.getSubReg() && MI.readsVirtualRegister(Reg)) {
1023 CopyDstSub = MI.getOperand(0).getSubReg();
1024 CopySrcSub = MI.getOperand(1).getSubReg();
1056 if (MO.getSubReg() && MI.readsVirtualRegister(Reg))
lib/CodeGen/RegisterCoalescer.cpp 367 DstSub = MI->getOperand(0).getSubReg();
369 SrcSub = MI->getOperand(1).getSubReg();
372 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(),
375 SrcSub = MI->getOperand(2).getSubReg();
889 UseMI->getOperand(0).getSubReg())
1198 if (Op.getSubReg() == 0 || Op.isUndef())
1244 if (DstOperand.getSubReg() && !DstOperand.isUndef())
1261 DefMI->getOperand(0).getSubReg());
1293 if (DefMO.getSubReg() == DstIdx) {
1345 unsigned NewIdx = NewMI.getOperand(0).getSubReg();
1459 if (NewMI.getOperand(0).getSubReg())
1592 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(MO.getSubReg());
1659 unsigned SubReg = MO.getSubReg();
2397 TRI->composeSubRegIndices(SubIdx, MO.getSubReg()));
2832 unsigned S = TRI->composeSubRegIndices(SubIdx, MO.getSubReg());
2945 if (MO.getSubReg() != 0 && MO.isUndef() && !EraseImpDef)
lib/CodeGen/RegisterPressure.cpp 534 unsigned SubRegIdx = MO.getSubReg();
1233 unsigned SubRegIdx = MO.getSubReg();
lib/CodeGen/RenameIndependentSubregs.cpp 181 unsigned SubRegIdx = MO.getSubReg();
225 unsigned SubRegIdx = MO.getSubReg();
347 unsigned SubRegIdx = MO.getSubReg();
lib/CodeGen/ScheduleDAGInstrs.cpp 369 unsigned SubReg = MO.getSubReg();
396 bool IsKill = MO.getSubReg() == 0 || MO.isUndef();
402 if (MO.getSubReg() != 0 && MO.isUndef()) {
lib/CodeGen/SplitKit.cpp 443 if (unsigned SR = DefOp.getSubReg())
1347 if (!MO.getSubReg() && !MO.isEarlyClobber())
1376 Register Reg = EP.MO.getReg(), Sub = EP.MO.getSubReg();
lib/CodeGen/StackMaps.cpp 154 assert(!MOI->getSubReg() && "Physical subreg still around.");
lib/CodeGen/TailDuplicator.cpp 347 unsigned SrcSubReg = MI->getOperand(SrcOpIdx).getSubReg();
427 MO.setSubReg(TRI->composeSubRegIndices(MO.getSubReg(),
644 if (PU.getSubReg() != 0)
lib/CodeGen/TargetInstrInfo.cpp 176 unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0;
177 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg();
178 unsigned SubReg2 = MI.getOperand(Idx2).getSubReg();
443 if (FoldOp.getSubReg() || LiveOp.getSubReg())
443 if (FoldOp.getSubReg() || LiveOp.getSubReg())
517 TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF);
557 if (auto SubReg = MI.getOperand(OpIdx).getSubReg()) {
896 if (Register::isVirtualRegister(DefReg) && MI.getOperand(0).getSubReg() &&
1187 InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(),
1213 InputReg.SubReg = MOReg.getSubReg();
1238 BaseReg.SubReg = MOBaseReg.getSubReg();
1241 InsertedReg.SubReg = MOInsertedReg.getSubReg();
lib/CodeGen/TwoAddressInstructionPass.cpp 1483 if (SrcMO.isUndef() && !DstMO.getSubReg()) {
1527 SubRegB = MI->getOperand(SrcIdx).getSubReg();
1618 if (MO.getSubReg() == SubRegB) {
1767 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
1802 if (MI.getOperand(0).getSubReg() || Register::isPhysicalRegister(DstReg) ||
lib/CodeGen/UnreachableBlockElim.cpp 179 assert(Output.getSubReg() == 0 && "Cannot have output subregister");
184 unsigned InputSub = Input.getSubReg();
lib/CodeGen/VirtRegMap.cpp 363 unsigned SubRegIdx = MO.getSubReg();
524 unsigned SubReg = MO.getSubReg();
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp 144 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),
146 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI))
148 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),
150 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(),
152 SubReg = MI->getOperand(1).getSubReg();
lib/Target/AArch64/AArch64AsmPrinter.cpp 507 assert(!MO.getSubReg() && "Subregs should be eliminated!");
lib/Target/AArch64/AArch64FastISel.cpp 4544 LoadMI->getOperand(1).getSubReg() == AArch64::sub_32) {
4568 MI->getOperand(1).getSubReg() == AArch64::sub_32) &&
lib/Target/AArch64/AArch64InstrInfo.cpp 1663 if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
1686 if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
3250 if (DstMO.getSubReg() == 0 && SrcMO.getSubReg() == 0) {
3250 if (DstMO.getSubReg() == 0 && SrcMO.getSubReg() == 0) {
3273 assert(SrcMO.getSubReg() == 0 &&
3277 switch (DstMO.getSubReg()) {
3319 if (IsFill && SrcMO.getSubReg() == 0 && DstMO.isUndef()) {
3321 switch (DstMO.getSubReg()) {
3343 assert(LoadDst.getSubReg() == 0 && "unexpected subreg on fill load");
3344 LoadDst.setSubReg(DstMO.getSubReg());
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 224 unsigned ComposedSubIdx = TRI.composeSubRegIndices(MO.getSubReg(), SubIdx);
lib/Target/AMDGPU/GCNDPPCombine.cpp 480 if (Op.getSubReg() == FwdSubReg)
lib/Target/AMDGPU/GCNNSAReassign.cpp 194 if (MRI->getRegClass(Reg) != &AMDGPU::VGPR_32RegClass || Op.getSubReg())
lib/Target/AMDGPU/GCNRegBankReassign.cpp 373 if (Bank != -1 && R == Reg && Op.getSubReg()) {
374 unsigned LM = TRI->getSubRegIndexLaneMask(Op.getSubReg()).getAsInteger();
390 unsigned Mask = getRegBankMask(R, Op.getSubReg(),
394 OperandMasks.push_back(OperandMask(Op.getReg(), Op.getSubReg(), Mask));
lib/Target/AMDGPU/GCNRegPressure.cpp 205 return MO.getSubReg() == 0 ?
207 MRI.getTargetRegisterInfo()->getSubRegIndexLaneMask(MO.getSubReg());
215 if (auto SubReg = MO.getSubReg())
lib/Target/AMDGPU/R600MachineScheduler.cpp 258 unsigned DestSubReg = MI->getOperand(0).getSubReg();
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 270 unsigned SubReg = CopyUse.getOperand(1).getSubReg();
289 unsigned SrcSubReg = MI.getOperand(I).getSubReg();
339 if (Copy->getOperand(0).getSubReg())
724 MO->getSubReg() == Def.getSubReg()) {
724 MO->getSubReg() == Def.getSubReg()) {
lib/Target/AMDGPU/SIFixupVectorISel.cpp 113 if (DefInst->getOperand(2).getSubReg() != AMDGPU::NoSubRegister)
116 if (DefInst->getOperand(3).getSubReg() != AMDGPU::NoSubRegister)
lib/Target/AMDGPU/SIFoldOperands.cpp 302 Old.substVirtReg(New->getReg(), New->getSubReg(), TRI);
461 SubDef && Sub->isReg() && !Sub->getSubReg() &&
554 if (UseOp.isImplicit() || UseOp.getSubReg() != AMDGPU::NoSubRegister)
577 if (RSUse->getSubReg() != RegSeqDstSubReg)
671 !UseMI->getOperand(1).getSubReg()) {
677 UseMI->getOperand(1).setSubReg(OpToFold.getSubReg());
813 UseMI->getOperand(1).setSubReg(OpToFold.getSubReg());
845 if (UseOp.getSubReg() && AMDGPU::getRegBitWidth(FoldRC->getID()) == 64) {
853 if (UseOp.getSubReg() == AMDGPU::sub0) {
856 assert(UseOp.getSubReg() == AMDGPU::sub1);
947 if (Op.getSubReg() != AMDGPU::NoSubRegister ||
1255 Src0->getSubReg() != Src1->getSubReg() ||
1255 Src0->getSubReg() != Src1->getSubReg() ||
1256 Src0->getSubReg() != AMDGPU::NoSubRegister)
1400 Src0->getSubReg() == Src1->getSubReg() &&
1400 Src0->getSubReg() == Src1->getSubReg() &&
1420 RegOp->getSubReg() != AMDGPU::NoSubRegister ||
lib/Target/AMDGPU/SIFormMemoryClauses.cpp 233 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(MO.getSubReg());
273 ? TRI->getSubRegIndexLaneMask(MO.getSubReg())
lib/Target/AMDGPU/SIISelLowering.cpp 3208 .addReg(IdxReg.getReg(), 0, IdxReg.getSubReg());
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 471 assert(!Op.getSubReg() || !Op.isUndef());
lib/Target/AMDGPU/SIInstrInfo.cpp 1646 unsigned SubReg = RegOp.getSubReg();
2400 unsigned Src1SubReg = Src1->getSubReg();
3186 return SubReg.getSubReg() != AMDGPU::NoSubRegister &&
3863 if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) {
3876 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
3925 if (MO.getSubReg()) {
3931 DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg());
3969 SGPRsUsed.insert(RegSubRegPair(MO->getReg(), MO->getSubReg()));
3976 RegSubRegPair SGPR(Op.getReg(), Op.getSubReg());
4106 unsigned Src0SubReg = Src0.getSubReg();
4113 Src0.setSubReg(Src1.getSubReg());
4279 unsigned OpSubReg = Op.getSubReg();
lib/Target/AMDGPU/SIInstrInfo.h 820 if (unsigned SubReg = MO.getSubReg()) {
1047 return TargetInstrInfo::RegSubRegPair(O.getReg(), O.getSubReg());
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 152 AddrReg[i]->getSubReg() != AddrRegNext.getSubReg()) {
152 AddrReg[i]->getSubReg() != AddrRegNext.getSubReg()) {
908 unsigned BaseSubReg = AddrReg->getSubReg();
1001 unsigned BaseSubReg = AddrReg->getSubReg();
1510 Addr.Base.LoSubReg = BaseLo.getSubReg();
1511 Addr.Base.HiSubReg = BaseHi.getSubReg();
lib/Target/AMDGPU/SILowerControlFlow.cpp 183 assert(SaveExec.getSubReg() == AMDGPU::NoSubRegister);
204 assert(Cond.getSubReg() == AMDGPU::NoSubRegister);
lib/Target/AMDGPU/SILowerI1Copies.cpp 522 assert(!MI.getOperand(0).getSubReg());
583 assert(!IncomingDef->getOperand(1).getSubReg());
698 assert(!MI.getOperand(1).getSubReg());
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 215 unsigned CmpSubReg = AndCC->getSubReg();
219 CmpSubReg = AndCC->getSubReg();
238 auto *Sel = TRI->findReachingDef(SelReg, Op1->getSubReg(), *Cmp, MRI, LIS);
262 .addReg(CCReg, getUndefRegState(CC->isUndef()), CC->getSubReg());
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 278 To.setSubReg(From.getSubReg());
291 LHS.getSubReg() == RHS.getSubReg();
291 LHS.getSubReg() == RHS.getSubReg();
512 getPreservedOperand()->getSubReg());
1199 Op.getSubReg());
lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp 135 const unsigned SubReg = MO.getSubReg();
lib/Target/AMDGPU/SIShrinkInstructions.cpp 402 TRI.getSubRegIndexLaneMask(MO.getSubReg());
461 unsigned Tsub = MovT.getOperand(0).getSubReg();
467 unsigned Xsub = Xop.getSubReg();
476 if (YTop.getSubReg() != Tsub)
482 MovY.getOperand(1).getSubReg() != Tsub)
486 unsigned Ysub = MovY.getOperand(0).getSubReg();
512 I->getOperand(0).getSubReg() != Xsub) {
lib/Target/ARM/A15SDOptimizer.cpp 170 if (MO->getSubReg() == ARM::ssub_1) return ARM::ssub_1;
265 EC->getOperand(1).getSubReg() == ARM::ssub_0) {
lib/Target/ARM/ARMAsmPrinter.cpp 208 assert(!MO.getSubReg() && "Subregs should be eliminated!");
lib/Target/ARM/ARMBaseInstrInfo.cpp 1239 if (MI.getOperand(0).isFI() && MI.getOperand(2).getSubReg() == 0) {
1245 if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1482 if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1488 if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
5180 if (!MO.getSubReg() || MI.readsVirtualRegister(Reg))
5265 MOReg->getSubReg(), ARM::ssub_0));
5270 MOReg->getSubReg(), ARM::ssub_1));
5292 InputReg.SubReg = MOReg.getSubReg();
5314 BaseReg.SubReg = MOBaseReg.getSubReg();
5317 InsertedReg.SubReg = MOInsertedReg.getSubReg();
lib/Target/ARM/ARMMCInstLower.cpp 80 assert(!MO.getSubReg() && "Subregs should be eliminated!");
lib/Target/ARM/Thumb2ITBlockPass.cpp 144 assert(MI->getOperand(0).getSubReg() == 0 &&
145 MI->getOperand(1).getSubReg() == 0 &&
lib/Target/Hexagon/BitTracker.cpp 804 assert(MD.getSubReg() == 0 && "Unexpected sub-register in definition");
lib/Target/Hexagon/BitTracker.h 144 : Reg(MO.getReg()), Sub(MO.getSubReg()) {}
lib/Target/Hexagon/HexagonBitSimplify.cpp 393 if (I->getSubReg() != OldSR)
944 return Op.getSubReg() != NewSub && Op.isTied();
978 assert(!UseI->getOperand(0).getSubReg());
1667 assert(MI.getOperand(0).getSubReg() == 0);
2281 if (Op1.getReg() != SrcR || Op1.getSubReg() != SrcSR)
2293 assert(Op0.getSubReg() == 0);
3096 MIB.addReg(UseR, 0, Op.getSubReg());
lib/Target/Hexagon/HexagonBitTracker.cpp 199 assert(MO.getSubReg() == 0);
lib/Target/Hexagon/HexagonBlockRanges.cpp 323 RegisterRef R = { Op.getReg(), Op.getSubReg() };
339 RegisterRef R = { Op.getReg(), Op.getSubReg() };
lib/Target/Hexagon/HexagonConstExtenders.cpp 233 : Reg(Op.getReg()), Sub(Op.getSubReg()) {}
237 Sub = Op.getSubReg();
1928 assert(Op.getSubReg() == 0 && "Predicate register with a subregister");
lib/Target/Hexagon/HexagonConstPropagation.cpp 90 : Reg(MO.getReg()), SubReg(MO.getSubReg()) {}
2837 assert(!MO.getSubReg());
3015 .addReg(Src1.getReg(), getRegState(Src1), Src1.getSubReg())
3016 .addReg(OpR2.getReg(), getRegState(OpR2), OpR2.getSubReg())
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 475 if (RA.getSubReg() != 0 || RB.getSubReg() != 0) {
475 if (RA.getSubReg() != 0 || RB.getSubReg() != 0) {
821 SR = RO.getReg(), SSR = RO.getSubReg();
823 TR = RO.getReg(), TSR = RO.getSubReg();
825 FR = RO.getReg(), FSR = RO.getSubReg();
991 Register UseR = UO.getReg(), UseSR = UO.getSubReg();
lib/Target/Hexagon/HexagonExpandCondsets.cpp 178 Sub(Op.getSubReg()) {}
323 LaneBitmask SLM = getLaneMask(Reg, Op.getSubReg());
375 Register DR = Op.getReg(), DSR = Op.getSubReg();
647 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
648 .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg());
652 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
674 Register DR = MD.getReg(), DSR = MD.getSubReg();
884 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg());
886 PredOp.getSubReg());
953 if (MD.getSubReg() && !MRI->shouldTrackSubRegLiveness(MD.getReg()))
lib/Target/Hexagon/HexagonFrameLowering.cpp 2254 SrcOp.getSubReg() };
2283 if (unsigned SR = SrcOp.getSubReg())
2303 assert(MI.getOperand(0).getSubReg() == 0);
lib/Target/Hexagon/HexagonGenInsert.cpp 610 assert(MO.getSubReg() == 0 && "Unexpected subregister in definition");
lib/Target/Hexagon/HexagonGenMux.cpp 367 assert(Op.getSubReg() == 0 && "Should have physical registers only");
lib/Target/Hexagon/HexagonGenPredicate.cpp 53 RegisterSubReg(const MachineOperand &MO) : R(MO.getReg()), S(MO.getSubReg()) {}
lib/Target/Hexagon/HexagonHardwareLoops.cpp 889 SR = Start->getSubReg();
892 SR = End->getSubReg();
907 DistSR = End->getSubReg();
918 SubIB.addReg(End->getReg(), 0, End->getSubReg())
919 .addReg(Start->getReg(), 0, Start->getSubReg());
922 .addReg(Start->getReg(), 0, Start->getSubReg());
930 EndValInstr->getOperand(1).getSubReg() == 0 &&
937 SubIB.addReg(End->getReg(), 0, End->getSubReg())
1564 switch (MO.getSubReg()) {
1915 unsigned PredRSub = PN->getOperand(i).getSubReg();
lib/Target/Hexagon/HexagonInstrInfo.cpp 1260 assert(Op1.getSubReg() == 0);
1294 assert(Op1.getSubReg() == 0);
1885 unsigned BaseSubA = BaseA.getSubReg();
1893 unsigned BaseSubB = BaseB.getSubReg();
3183 if (BaseOp.getSubReg() != 0)
lib/Target/Hexagon/HexagonPeephole.cpp 208 if (Src.getSubReg() != Hexagon::isub_lo)
lib/Target/Hexagon/HexagonRDFOpt.cpp 123 assert(DstOp.getSubReg() == 0 && "Unexpected subregister");
125 DFG.makeRegRef(HiOp.getReg(), HiOp.getSubReg()));
127 DFG.makeRegRef(LoOp.getReg(), LoOp.getSubReg()));
139 mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()),
140 DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg()));
lib/Target/Hexagon/HexagonSplitDouble.cpp 259 if (&MO == &Op || !MO.isReg() || MO.getSubReg())
321 if (!Op.getSubReg())
325 if (MI->getOperand(1).getSubReg() != 0)
444 if (Op.getSubReg())
607 unsigned SR = Op.getSubReg();
653 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
656 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
662 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
666 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
678 assert(!UpdOp.getSubReg() && "Def operand with subreg");
745 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg());
753 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg());
771 .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg());
773 .addReg(Op1.getReg(), RS, Op1.getSubReg())
1080 if (!Op.isReg() || !Op.isUse() || !Op.getSubReg())
1087 switch (Op.getSubReg()) {
1110 if (MRI->getRegClass(R) != DoubleRC || Op.getSubReg())
lib/Target/Hexagon/HexagonStoreWidening.cpp 435 .addReg(MR.getReg(), getKillRegState(MR.isKill()), MR.getSubReg())
458 .addReg(MR.getReg(), getKillRegState(MR.isKill()), MR.getSubReg())
lib/Target/Hexagon/HexagonVExtract.cpp 73 unsigned ExtIdxS = ExtI->getOperand(2).getSubReg();
142 unsigned SR = ExtI->getOperand(1).getSubReg();
lib/Target/Hexagon/RDFCopy.cpp 46 RegisterRef DstR = DFG.makeRegRef(Dst.getReg(), Dst.getSubReg());
47 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg());
lib/Target/Hexagon/RDFGraph.cpp 634 if (Op.getSubReg() != 0)
976 return makeRegRef(Op.getReg(), Op.getSubReg());
lib/Target/PowerPC/PPCInstrInfo.cpp 398 unsigned SubReg1 = MI.getOperand(1).getSubReg();
399 unsigned SubReg2 = MI.getOperand(2).getSubReg();
409 assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
1710 unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1889 unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
2832 unsigned CRSubReg = CompareUseMI.getOperand(3).getSubReg();
lib/Target/PowerPC/PPCMCInstLower.cpp 169 assert(!MO.getSubReg() && "Subregs should be eliminated!");
lib/Target/PowerPC/PPCReduceCRLogicals.cpp 545 Subreg = Copy->getOperand(1).getSubReg();
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 220 unsigned AddSubReg = AddendMI->getOperand(1).getSubReg();
221 unsigned KilledProdSubReg = MI.getOperand(KilledProdOp).getSubReg();
222 unsigned OtherProdSubReg = MI.getOperand(OtherProdOp).getSubReg();
lib/Target/SystemZ/SystemZInstrInfo.cpp 978 Src.getSubReg())
lib/Target/SystemZ/SystemZRegisterInfo.cpp 35 MO.getSubReg() == SystemZ::subreg_l32 ||
36 MO.getSubReg() == SystemZ::subreg_hl32)
39 MO.getSubReg() == SystemZ::subreg_h32 ||
40 MO.getSubReg() == SystemZ::subreg_hh32)
175 if (MO->getSubReg())
176 PhysReg = getSubReg(PhysReg, MO->getSubReg());
177 if (VRRegMO->getSubReg())
178 PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(),
lib/Target/X86/X86InstrInfo.cpp 109 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
109 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
406 if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
440 if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
3854 if (MO.getSubReg() || MO.isDef())
4912 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
4912 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
5018 auto SubReg = MO.getSubReg();
5199 if (MI.getOperand(Op).getSubReg())
5273 if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
5273 if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
6676 MI.getOperand(0).getSubReg() == 0 &&
6677 MI.getOperand(1).getSubReg() == 0 &&
6678 MI.getOperand(2).getSubReg() == 0)
6794 MI.getOperand(0).getSubReg() == 0 &&
6795 MI.getOperand(1).getSubReg() == 0 &&
6796 MI.getOperand(2).getSubReg() == 0) {
unittests/CodeGen/MachineOperandTest.cpp 75 ASSERT_TRUE(MO.getSubReg() == 5);