reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/X86/X86GenAsmMatcher.inc

 8026   { 83 /* addq */, X86::ADD64rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
22615   { 57 /* add */, X86::ADD64rr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GR64, MCK_GR64 }, },

gen/lib/Target/X86/X86GenDAGISel.inc

19646 /* 39648*/          OPC_MorphNodeTo2, TARGET_VAL(X86::ADD64rr), 0,
39392 /* 82480*/          OPC_MorphNodeTo2, TARGET_VAL(X86::ADD64rr), 0,
42937 /* 89813*/          OPC_MorphNodeTo2, TARGET_VAL(X86::ADD64rr), 0,

gen/lib/Target/X86/X86GenFastISel.inc

 6010   return fastEmitInst_rr(X86::ADD64rr, &X86::GR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);

gen/lib/Target/X86/X86GenGlobalISel.inc

 1177         GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD64rr,
11900         GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD64rr,

lib/Target/X86/X86DomainReassignment.cpp

  671     createReplacer(X86::ADD64rr, X86::KADDQrr);

lib/Target/X86/X86FixupLEAs.cpp

  175   case X86::ADD64rr:
  322     return X86::ADD64rr;

lib/Target/X86/X86FrameLowering.cpp

  124   return isLP64 ? X86::ADD64rr : X86::ADD32rr;
  304       MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(X86::ADD64rr), Rax)

lib/Target/X86/X86ISelDAGToDAG.cpp

 4589       case ISD::ADD: ROpc = X86::ADD64rr; MOpc = X86::ADD64rm; break;

lib/Target/X86/X86ISelLowering.cpp

29422     BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
31082       BuildMI(DispContBB, DL, TII->get(X86::ADD64rr), TReg)

lib/Target/X86/X86InstrFoldTables.cpp

   67   { X86::ADD64rr,     X86::ADD64mr,    0 },
 1211   { X86::ADD64rr,                  X86::ADD64rm,                  0 },

lib/Target/X86/X86InstrInfo.cpp

 1033   case X86::ADD64rr:
 1039     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
 3428   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
 4859       MI.getOpcode() != X86::ADD64rr)
 7801           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD64rr), PC)

lib/Target/X86/X86MacroFusion.cpp

  112   case X86::ADD64rr:

lib/Target/X86/X86SpeculativeLoadHardening.cpp

 1316   case X86::ADD64rr:  case X86::ADD64ri8:  case X86::ADD64ri32:

unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp

  413     InstructionTemplate Add(Generator.createInstruction(X86::ADD64rr));