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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/R600GenInstrInfo.inc 1047 { 409, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #409 = RAT_ATOMIC_ADD_NORET
1048 { 410, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #410 = RAT_ATOMIC_ADD_RTN
1049 { 411, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #411 = RAT_ATOMIC_AND_NORET
1050 { 412, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #412 = RAT_ATOMIC_AND_RTN
1051 { 413, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #413 = RAT_ATOMIC_CMPXCHG_INT_NORET
1052 { 414, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #414 = RAT_ATOMIC_CMPXCHG_INT_RTN
1053 { 415, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #415 = RAT_ATOMIC_DEC_UINT_NORET
1054 { 416, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #416 = RAT_ATOMIC_DEC_UINT_RTN
1055 { 417, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #417 = RAT_ATOMIC_INC_UINT_NORET
1056 { 418, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #418 = RAT_ATOMIC_INC_UINT_RTN
1057 { 419, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #419 = RAT_ATOMIC_MAX_INT_NORET
1058 { 420, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #420 = RAT_ATOMIC_MAX_INT_RTN
1059 { 421, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #421 = RAT_ATOMIC_MAX_UINT_NORET
1060 { 422, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #422 = RAT_ATOMIC_MAX_UINT_RTN
1061 { 423, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #423 = RAT_ATOMIC_MIN_INT_NORET
1062 { 424, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #424 = RAT_ATOMIC_MIN_INT_RTN
1063 { 425, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #425 = RAT_ATOMIC_MIN_UINT_NORET
1064 { 426, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #426 = RAT_ATOMIC_MIN_UINT_RTN
1065 { 427, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #427 = RAT_ATOMIC_OR_NORET
1066 { 428, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #428 = RAT_ATOMIC_OR_RTN
1067 { 429, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #429 = RAT_ATOMIC_RSUB_NORET
1068 { 430, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #430 = RAT_ATOMIC_RSUB_RTN
1069 { 431, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #431 = RAT_ATOMIC_SUB_NORET
1070 { 432, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #432 = RAT_ATOMIC_SUB_RTN
1071 { 433, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #433 = RAT_ATOMIC_XCHG_INT_NORET
1072 { 434, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #434 = RAT_ATOMIC_XCHG_INT_RTN
1073 { 435, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #435 = RAT_ATOMIC_XOR_NORET
1074 { 436, 3, 1, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #436 = RAT_ATOMIC_XOR_RTN