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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/R600GenInstrInfo.inc 870 { 232, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #232 = ADD
871 { 233, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #233 = ADDC_UINT
872 { 234, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #234 = ADD_INT
874 { 236, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #236 = AND_INT
875 { 237, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #237 = ASHR_eg
876 { 238, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #238 = ASHR_r600
881 { 243, 21, 1, 0, 2, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #243 = BFM_INT_eg
920 { 282, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #282 = CUBE_eg_real
921 { 283, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #283 = CUBE_r600_real
922 { 284, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #284 = DOT4_eg
923 { 285, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #285 = DOT4_r600
948 { 310, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #310 = INTERP_XY
949 { 311, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #311 = INTERP_ZW
952 { 314, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #314 = KILLGT
991 { 353, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #353 = LSHL_eg
992 { 354, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #354 = LSHL_r600
993 { 355, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #355 = LSHR_eg
994 { 356, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #356 = LSHR_r600
995 { 357, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #357 = MAX
996 { 358, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #358 = MAX_DX10
997 { 359, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #359 = MAX_INT
998 { 360, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #360 = MAX_UINT
999 { 361, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #361 = MIN
1000 { 362, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #362 = MIN_DX10
1001 { 363, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #363 = MIN_INT
1002 { 364, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #364 = MIN_UINT
1005 { 367, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #367 = MUL
1012 { 374, 21, 1, 0, 4, 0|(1ULL<<MCID::Predicable), 0x4a40ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #374 = MULHI_INT_cm
1013 { 375, 21, 1, 0, 2, 0|(1ULL<<MCID::Predicable), 0x4a40ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #375 = MULHI_INT_cm24
1014 { 376, 21, 1, 0, 4, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #376 = MULHI_INT_eg
1015 { 377, 21, 1, 0, 4, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #377 = MULHI_INT_r600
1016 { 378, 21, 1, 0, 2, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #378 = MULHI_UINT24_eg
1017 { 379, 21, 1, 0, 4, 0|(1ULL<<MCID::Predicable), 0x4a40ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #379 = MULHI_UINT_cm
1018 { 380, 21, 1, 0, 2, 0|(1ULL<<MCID::Predicable), 0x4a40ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #380 = MULHI_UINT_cm24
1019 { 381, 21, 1, 0, 4, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #381 = MULHI_UINT_eg
1020 { 382, 21, 1, 0, 4, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #382 = MULHI_UINT_r600
1021 { 383, 21, 1, 0, 4, 0|(1ULL<<MCID::Predicable), 0x4a40ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #383 = MULLO_INT_cm
1022 { 384, 21, 1, 0, 4, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #384 = MULLO_INT_eg
1023 { 385, 21, 1, 0, 4, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #385 = MULLO_INT_r600
1024 { 386, 21, 1, 0, 4, 0|(1ULL<<MCID::Predicable), 0x4a40ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #386 = MULLO_UINT_cm
1025 { 387, 21, 1, 0, 4, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #387 = MULLO_UINT_eg
1026 { 388, 21, 1, 0, 4, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #388 = MULLO_UINT_r600
1027 { 389, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #389 = MUL_IEEE
1028 { 390, 21, 1, 0, 2, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #390 = MUL_INT24_cm
1031 { 393, 21, 1, 0, 2, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #393 = MUL_UINT24_eg
1033 { 395, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #395 = OR_INT
1037 { 399, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #399 = PRED_SETE
1038 { 400, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #400 = PRED_SETE_INT
1039 { 401, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #401 = PRED_SETGE
1040 { 402, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #402 = PRED_SETGE_INT
1041 { 403, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #403 = PRED_SETGT
1042 { 404, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #404 = PRED_SETGT_INT
1043 { 405, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #405 = PRED_SETNE
1044 { 406, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #406 = PRED_SETNE_INT
1099 { 461, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #461 = SETE
1100 { 462, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #462 = SETE_DX10
1101 { 463, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #463 = SETE_INT
1102 { 464, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #464 = SETGE_DX10
1103 { 465, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #465 = SETGE_INT
1104 { 466, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #466 = SETGE_UINT
1105 { 467, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #467 = SETGT_DX10
1106 { 468, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #468 = SETGT_INT
1107 { 469, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #469 = SETGT_UINT
1108 { 470, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #470 = SETNE_DX10
1109 { 471, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #471 = SETNE_INT
1110 { 472, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #472 = SGE
1111 { 473, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #473 = SGT
1116 { 478, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #478 = SNE
1117 { 479, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #479 = SUBB_UINT
1118 { 480, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #480 = SUB_INT
1151 { 513, 21, 1, 0, 3, 0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #513 = XOR_INT