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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc 2863 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
2884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
2904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
2924 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
3032 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
3053 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
3073 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
3093 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
3375 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
3396 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
3416 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
3436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
3544 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
3565 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
3585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
3605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
4060 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
4081 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
4101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
4121 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
4142 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
4162 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
4182 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
4203 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
5672 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
5693 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
5713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
5733 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
5754 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
5774 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
5794 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
5815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
15439 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32_XM0_XEXECRegClassID,
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc15546 static const MCOperandInfo OperandInfo204[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15547 static const MCOperandInfo OperandInfo205[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15547 static const MCOperandInfo OperandInfo205[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15548 static const MCOperandInfo OperandInfo206[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15549 static const MCOperandInfo OperandInfo207[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15549 static const MCOperandInfo OperandInfo207[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15563 static const MCOperandInfo OperandInfo221[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15564 static const MCOperandInfo OperandInfo222[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15564 static const MCOperandInfo OperandInfo222[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15565 static const MCOperandInfo OperandInfo223[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15566 static const MCOperandInfo OperandInfo224[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15566 static const MCOperandInfo OperandInfo224[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15583 static const MCOperandInfo OperandInfo241[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15584 static const MCOperandInfo OperandInfo242[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15589 static const MCOperandInfo OperandInfo247[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
15598 static const MCOperandInfo OperandInfo256[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15599 static const MCOperandInfo OperandInfo257[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
gen/lib/Target/AMDGPU/AMDGPUGenRegisterBank.inc 43 (1u << (AMDGPU::SReg_32_XM0_XEXECRegClassID - 0)) |
62 (1u << (AMDGPU::SReg_32_XM0_XEXECRegClassID - 0)) |
172 (1u << (AMDGPU::SReg_32_XM0_XEXECRegClassID - 0)) |
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc11261 { SReg_32_XM0_XEXEC, SReg_32_XM0_XEXECBits, 3272, 141, sizeof(SReg_32_XM0_XEXECBits), AMDGPU::SReg_32_XM0_XEXECRegClassID, 1, true },
20552 &AMDGPUMCRegisterClasses[SReg_32_XM0_XEXECRegClassID],