reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc

17341   extern const TargetRegisterClass SGPR_32RegClass;

References

gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc

21726     &AMDGPU::SGPR_32RegClass,

lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp

   94                           &AMDGPU::SGPR_32RegClass);
   98                           &AMDGPU::SGPR_32RegClass);
  101                           &AMDGPU::SGPR_32RegClass);
  105       &AMDGPU::SGPR_32RegClass);

lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

  674     for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

   84     if (RC != &AMDGPU::SGPR_32RegClass)
 1575     ConstrainRC = &AMDGPU::SGPR_32RegClass;

lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

 1057       !AMDGPU::SGPR_32RegClass.contains(MFI->ScratchWaveOffsetReg)) {
 1062       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
 1067       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
 1118                              AMDGPU::SGPR_32RegClass,
 1121                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
 1124                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
 1127                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
 1130                              AMDGPU::SGPR_32RegClass,
 1133                              AMDGPU::SGPR_32RegClass,

lib/Target/AMDGPU/GCNRegBankReassign.cpp

  449   return AMDGPU::SGPR_32RegClass.contains(PhysReg);

lib/Target/AMDGPU/GCNSchedStrategy.cpp

   44     ->getNumAllocatableRegs(&AMDGPU::SGPR_32RegClass) - ErrorMargin;

lib/Target/AMDGPU/SIFormMemoryClauses.cpp

  321   MaxSGPRs = TRI->getAllocatableSet(MF, &AMDGPU::SGPR_32RegClass).count();

lib/Target/AMDGPU/SIFrameLowering.cpp

   35   return makeArrayRef(AMDGPU::SGPR_32RegClass.begin(),
  972         TRI->getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
  976         TRI->getSpillSize(AMDGPU::SGPR_32RegClass),
  977         TRI->getSpillAlignment(AMDGPU::SGPR_32RegClass),

lib/Target/AMDGPU/SIISelLowering.cpp

  104   unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
 1692   return allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_32RegClass, 32);
 1819     MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
 1825     MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
 1831     MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
 1837     MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
 1858     MF.addLiveIn(PrivateSegmentWaveByteOffsetReg, &AMDGPU::SGPR_32RegClass);
 1926       for (unsigned Reg : AMDGPU::SGPR_32RegClass) {
 1999       RC = &AMDGPU::SGPR_32RegClass;
 3186   Register CurrentIdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
 3223       IdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
 3679     Register CountReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
10642       RC = &AMDGPU::SGPR_32RegClass;

lib/Target/AMDGPU/SIInstrInfo.cpp

  758       RegClass == &AMDGPU::SGPR_32RegClass ||
 1266       unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
 1267       unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
 2219       EltRC = &AMDGPU::SGPR_32RegClass;
 4236     Register SGPR = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
 4343   Register SRsrcSub0 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
 4344   Register SRsrcSub1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
 4345   Register SRsrcSub2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
 4346   Register SRsrcSub3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
 4484   Register SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
 4485   Register SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
 5301     &AMDGPU::SGPR_32RegClass;
 5428     &AMDGPU::SGPR_32RegClass;
 5433     &AMDGPU::SGPR_32RegClass;
 5532     &AMDGPU::SGPR_32RegClass;

lib/Target/AMDGPU/SIRegisterInfo.cpp

  112   unsigned BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx));
  136   return AMDGPU::SGPR_32RegClass.getRegister(Reg);
  193   unsigned TotalNumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
  195     unsigned Reg = AMDGPU::SGPR_32RegClass.getRegister(i);
  663       SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0, false);
 1384     return &AMDGPU::SGPR_32RegClass;
 1414       return &AMDGPU::SGPR_32RegClass;
 1756     return getRegPressureLimit(&AMDGPU::SGPR_32RegClass,
 1796       return &AMDGPU::SGPR_32RegClass;